Semiconductor device

Abstract

Some embodiments described herein provide semiconductor devices including optical devices having backside transmissive regions and methods of manufacture. The semiconductor devices include a first semiconductor device stacked over a second semiconductor device, where the first semiconductor device includes a photodiode, and the second semiconductor device includes a backside transmissive region. The backside transmissive region is located below the photodiode in the first semiconductor device and includes a trench structure having a highly reflective structure, and / or the trench structure has a property of maintaining the intensity of light transmitted by the light wave through the backside transmissive region. The vacancy within the trench structure reduces the likelihood of interference, which may result in other transmission losses (e.g., reflection losses, absorption losses, scattering losses, and / or modal mismatch losses) associated with a transmissive region adjacent to the photodiode structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] A photodetector is a semiconductor device that can receive photons of incident light and convert the photons into an electrical signal. The electrical signal can include a current (called photocurrent) and / or a voltage, among other examples. Photons generate electron / hole pairs for an absorption region in the photodetector. The electrons and holes are separated and collected at opposite doped and collection regions. The photodetector can be a semiconductor device including a photodiode structure, possibly including in a photonic element and applied in an optical communication system. SUMMARY

[0003] In an embodiment, a semiconductor device includes a first semiconductor device and a second semiconductor device, where the second semiconductor device is located below the first semiconductor device and is bonded to the first semiconductor device along a bonding line. The first semiconductor device includes a photodiode structure. The second semiconductor device includes a backside transmission region including a trench structure. The trench structure is configured in a direction orthogonal to the bonding line. The trench structure is configured to transmit a plurality of light waves into the first semiconductor device for transmission to the photodiode structure.

[0004] In an embodiment, a semiconductor device includes a first semiconductor device and a second semiconductor device, where the second semiconductor device is located below the first semiconductor device and is bonded to the first semiconductor device along a bonding line. The first semiconductor device includes a photodiode structure. The second semiconductor device includes a backside transmission region including a trench structure. The trench structure is configured in a direction orthogonal to the bonding line. The trench structure is configured to transmit a plurality of light waves into the first semiconductor device for transmission to the photodiode structure. The trench structure further includes a portion through a dielectric layer of the second semiconductor device and including a gas that is transparent to the light waves, and a distributed Bragg reflector structure on sidewalls of the portion along the direction orthogonal to the bonding line to reflect and redirect the light.

[0005] In one embodiment, a semiconductor device includes a first semiconductor device and a second semiconductor device, where the second semiconductor device is located below the first semiconductor device and is bonded to the first semiconductor device along a bonding line. The first semiconductor device includes a photodiode structure. The second semiconductor device includes a backside transmissive region including a trench structure. Where the trench structure is configured in a direction orthogonal to the bonding line. Where the trench structure is configured to transmit a plurality of light waves into the first semiconductor device for transmission to the photodiode structure. Where the trench structure includes a first portion through a dielectric layer of the second semiconductor device and includes a gas that is transparent to the light waves, and a second portion in a substrate layer of the second semiconductor device above the dielectric layer, where the second portion is aligned with the first portion. BRIEF DESCRIPTION OF DRAWINGS

[0006] The nature of the disclosure will be appreciated as the detailed description proceeds in connection with the accompanying drawings, in which:

[0007] Figure 1 Example process flow diagrams for environments to which systems and / or methods described herein can be applied;

[0008] Figures 2A-2C Example photovoltaic elements including a backside transmissive region described herein;

[0009] Figures 3A-3I Example semiconductor manufacturing operation series to fabricate a semiconductor device including a photodiode structure described herein;

[0010] Figures 4A-4E Example semiconductor manufacturing operation series to fabricate a photovoltaic element including a backside transmissive region described herein;

[0011] Figures 5A-5E Example semiconductor manufacturing operation series to fabricate a photovoltaic element including a backside transmissive region described herein;

[0012] Figure 6 Example elements of devices described herein;

[0013] Figure 7 Example process flow diagrams for fabricating a photovoltaic element including a backside transmissive region described herein;

[0014] Figure 8 Example operation flow diagrams for a photovoltaic element including a backside transmissive region described herein.

[0015] NOTATION

[0016] 100: environment

[0017] 102: deposition tool / semiconductor process tool

[0018] 104: exposure tool

[0019] 106: development tool

[0020] 108: etching tool

[0021] 110: planarization tool

[0022] 112: plating process tool

[0023] 114: ion implant tool

[0024] 116: bonding / debonding tool

[0025] 118: wafer / die transport tool

[0026] 200: optoelectronic element

[0027] 202: semiconductor device

[0028] 204: semiconductor device

[0029] 206: bond wire

[0030] 208: substrate layer

[0031] 208a: substrate layer

[0032] 208b: substrate layer

[0033] 210: layer stack

[0034] 212: photodiode structure

[0035] 214: doped region

[0036] 214a: doped region

[0037] 214b: doped region

[0038] 216: connection structure

[0039] 218: metal pad

[0040] 220: under bump metal (UBM) pad

[0041] 224: striated waveguide structure

[0042] 226: striated waveguide structure

[0043] 228: waveguide transition structure

[0044] 230: distributed Bragg reflector structure

[0045] 232: substrate layer

[0046] 234: dielectric layer

[0047] 236: transmission region

[0048] 236a: transmission region

[0049] 236b: transmission region

[0050] 236c: transmission region

[0051] 236d: transmission region

[0052] 238: trench structure

[0053] 238a: trench structure

[0054] 238b: trench structure

[0055] 238c: trench structure

[0056] 238d: trench structure

[0057] 238e: trench structure

[0058] 238f: trench structure

[0059] 238g: trench structure

[0060] 238h: trench structure

[0061] 238i: trench structure

[0062] 238j: trench structure

[0063] 238k: trench structure

[0064] 2381: trench structure

[0065] 240: semiconductor device

[0066] 240a: portion

[0067] 240b: portion

[0068] 240c: portion

[0069] 242a: optical structure

[0070] 242b: optical structure

[0071] 242c: optical structure

[0072] 244a: light wave

[0073] 244b: light wave

[0074] 244c: light wave

[0075] 244d: light wave

[0076] 246: microlens structure

[0077] 248: central axis

[0078] 300: semiconductor process operation

[0079] 302: void

[0080] 304: polysilicon layer

[0081] 308: layer stack

[0082] 310: void

[0083] 312: void

[0084] 314: void

[0085] 316: void

[0086] 318: transmission region filler

[0087] 320: interlayer dielectric layer

[0088] 322: void

[0089] 400: semiconductor manufacturing operation

[0090] 402: void

[0091] 404: void

[0092] 500: semiconductor manufacturing operation

[0093] 502: void

[0094] 504: conformal layer

[0095] 506: optical structure

[0096] 600: device element

[0097] 610: bus

[0098] 620: processor

[0099] 630: memory

[0100] 640: input element

[0101] 650: output element

[0102] 660: communication element

[0103] 700: process

[0104] 710: block

[0105] 720: block

[0106] 730: block

[0107] 800: process

[0108] 810: block

[0109] 820: block

[0110] H1: height

[0111] H2: height DETAILED DESCRIPTION

[0112] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described herein to facilitate discussion of the present disclosure. It should be understood by those skilled in the art, however, that these specific examples and configurations do not limit the present disclosure in any way. For example, in the following description, formation of a first feature over or on a second feature can include embodiments in which the first and second features are formed directly contacting each other, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not directly contact each other. Additionally, in various examples, reference is made to repeated use of reference numerals and / or letters in the description. This repetition of reference numerals and / or letters is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the elements and / or configurations discussed.

[0113] Also for ease of description, spatial terms such as "beneath", "below", "lower", "above", "upper", and like terms can be used herein with respect to the orientation of one element or feature relative to another element or feature as illustrated in the figures. Such spatial terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0114] In some embodiments, the design of the optoelectronic element includes a transmission region (e.g., a light transmission region) adjacent to the photodiode structure. Structures in the transmission region may interfere with the reception of light waves entering a semiconductor device, which includes a photodiode structure, through which the light waves propagate laterally. This structural interference may result in light transmission losses (e.g., optical power (in decibels (dB)) caused by one or more reflection losses, absorption losses, scattering losses, and / or mode mismatch losses), and reduced optoelectronic element performance (e.g., reduced efficiency and / or sensitivity of the photodiode structure in other embodiments). Furthermore, the design of the optoelectronic element with a transmission region adjacent to the photodiode structure may consume planar area, leading to an increase in the system size using the optoelectronic element and consequently increasing the overall cost of the module.

[0115] In some embodiments, a semiconductor device comprising a photoelectric element having a back-side transmission region and a method of manufacturing thereof are described. The semiconductor device includes a first semiconductor device above a second semiconductor device, wherein the first semiconductor device includes a photodiode structure, and the second semiconductor device includes a back-side transmission region. The back-side transmission region is located below the photodiode structure of the first semiconductor device and includes a trench structure. Vacancies within the trench structure reduce the possibility of interference, which could lead to other transmission losses associated with the transmission region (such as reflection loss, absorption loss, scattering loss, and / or mode mismatch loss), wherein the transmission region is adjacent to the photodiode structure. In some embodiments, the trench structure includes optical structures with metal layers and / or reflective coating layers to maintain the light intensity transmitted through the transmission region. Additionally, or in some embodiments, the semiconductor device includes a microlens structure located between the trench structure and the photodiode structure. The reflective and concentrating properties of the optical structures and / or the microlens structure minimize transmission losses of light transmitted through the semiconductor device to the photodiode.

[0116] Therefore, improved performance of optoelectronic components may enable them to achieve better performance than other optoelectronic components that do not include the trench structure and / or microlens structure in the back-side transmission region. By increasing the yield of optoelectronic components, their classification into higher-performance and / or higher-quality product categories may be improved.

[0117] Figure 1 This is a schematic diagram of the embodiment environment 100, in which the systems and / or processes described may be implemented. Figure 1As shown, the environment 100 can include a variety of semiconductor process tools 102-116 and wafer / die transport tools 118. The variety of semiconductor process tools 102-116 can include deposition tools 102, exposure tools 104, development tools 106, etching tools 108, planarization tools 110, plating tools 112, ion implantation tools 114, bonding / delamination tools 116, and / or other semiconductor process tools. The example environment 100 can be located in a semiconductor clean room, a semiconductor wafer foundry, a semiconductor process equipment factory, and / or other manufacturing facilities in other embodiments.

[0118] The deposition tools 102 are semiconductor process tools that include semiconductor process chambers and one or more devices capable of depositing a variety of types of materials on a substrate. In some embodiments, the deposition tools 102 include spin-on tools that can be used to deposit a photoresist layer on a substrate, such as a wafer. In some embodiments, the deposition tools 102 include chemical vapor deposition process tools (CVD), such as plasma chemical vapor deposition process tools (PECVD), low pressure chemical vapor deposition process tools (LPCVD), high density plasma chemical vapor deposition process tools (HDP-CVD), sub-atmospheric chemical vapor deposition process tools (SACVD), atomic layer deposition process tools (ALD), plasma enhanced atomic layer deposition process tools (PEALD), or other types of chemical vapor deposition process tools. In some embodiments, the deposition tools 102 include physical vapor deposition process tools (PVD), such as sputtering process tools or other types of physical vapor deposition process tools. In some embodiments, the environment 100 includes a variety of types of deposition tools 102.

[0119] The exposure tools 104 are semiconductor process tools that can be used to expose a photoresist layer to a source of radiation, such as an ultraviolet light source (UV) (e.g., a deep ultraviolet light source, an extreme ultraviolet light source (EUV), and / or the like), an x-ray source, an e-beam source, and / or the like. The exposure tools 104 can expose the photoresist layer to the source of radiation and transfer a pattern from a mask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns to form one or more semiconductor devices, a pattern to form one or more semiconductor device structures, a pattern to perform etching different portions of a semiconductor device, and / or the like. In some embodiments, the exposure tools 104 include scanners, steppers, or the like.

[0120] The developing tool 106 is a semiconductor process tool that is capable of developing a photoresist layer with a source of radiation, where the photoresist layer has been exposed to develop a pattern transferred to the photoresist layer by the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing portions of the photoresist layer that were not exposed. In some embodiments, the developing tool 106 develops the pattern by removing portions of the photoresist layer that were exposed. In some embodiments, the developing tool 106 develops the pattern by dissolving portions of the photoresist layer that were exposed or not exposed using a chemical developer.

[0121] The etching tool 108 is a semiconductor process tool that is capable of etching different types of materials such as substrates, wafers, or semiconductor devices. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, and / or other similar tools. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a certain period of time to remove a certain amount of a portion or portions of the substrate. In some embodiments, the etching tool 108 can use a plasma etching or a plasma-assisted etching process to etch a portion or portions of the substrate, which can include using ionized gas to isotropically or directionally etch a portion or portions of the substrate.

[0122] The planarization tool 110 is a semiconductor process tool that is capable of polishing or planarizing different layers of a wafer or semiconductor device. For example, the planarization tool 110 can include a chemical mechanical planarization tool (CMP) and / or other planarization tools that can polish or planarize a layer or surface of deposited or plated material. The planarization tool 110 can polish or planarize a surface layer of a semiconductor device using a combination of chemical and mechanical forces, such as chemical etching and abrasive-free polishing. The planarization tool 110 can use abrasive and corrosive chemical slurries in combination with a polishing pad and a wafer chuck, such as a wafer chuck that is typically larger in diameter than the semiconductor device. The polishing pad and the semiconductor device can be pressed together by a dynamic polishing head and using the wafer chuck. The dynamic polishing head can be rotated on different axes to remove material and even any irregular topography from the semiconductor device so that the semiconductor device is planar or flat.

[0123] The electroplating process tool 112 is a semiconductor process tool that is capable of electroplating one or more metals onto a substrate (e.g., a wafer, a semiconductor device, and / or other similar devices) or portions thereof. For example, the electroplating process tool 112 can include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a composite or alloy (e.g., tin silver, tin lead, and / or other similar alloys) electroplating device, and / or one or more types of conductive material, metal, and / or other similar material electroplating devices.

[0124] The ion implantation tool 114 is a semiconductor process tool that is capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a material source, such as a gas or a solid, in an arc chamber. The material source can be provided in the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing ions of the material source. One or more extraction electrodes can be used in the arc chamber to extract ions from the plasma and accelerate the ions to form an ion beam. The ion beam can be directed toward a substrate, such that the ions are implanted below a surface of the substrate.

[0125] The bonding / detachment tool 116 is a semiconductor process tool that is capable of bonding two or more wafers (or two or more semiconductor substrates, or two or more semiconductor devices) together. For example, the bonding / detachment tool 116 can include a eutectic bonding tool that is capable of forming a eutectic bond between two or more wafers. In some examples, the bonding / detachment tool 116 can heat the two or more wafers to form a eutectic system between the materials of the two or more wafers. In another example, the bonding / detachment tool 116 can include a hybrid bonding tool, a direct bonding tool, and / or other types of bonding tools. In some embodiments, the bonding / detachment tool 116 can heat the two or more wafers to detach the two or more wafers.

[0126] The wafer / die transport 118 can be included in a cluster tool or other tool that includes multiple process chambers, and the wafer / die transport 118 can be used to transport substrates and / or semiconductor devices in the process chambers, in the process chambers and the buffer, in the process chambers and the interface tool (e.g., an EFEM), and / or in the process chambers and the transport carriers (e.g., FOUPs), among other examples. In some embodiments, the wafer / die transport 118 can be included in a multi-chamber (or cluster) deposition tool 102 that can include process chambers for pre-cleaning (e.g., cleaning or removing oxides, oxidelayers, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple deposition process chamber types (e.g., process chambers for depositing different types of materials and process chambers for performing different types of deposition operations).

[0127] In some embodiments, as described in more detail below Figures 3A-7 and elsewhere herein, one or more of the semiconductor process tools 102-116 and / or the wafer / die transport 118 can be used to perform a sequence of semiconductor process operations. The sequence of semiconductor process operations includes forming a photodiode structure in a first semiconductor device. The sequence of semiconductor process operations includes forming a transmission region including a vertically-arranged trench structure in a second semiconductor device, the transmission region being transmissive to light waves. The sequence of semiconductor process operations includes bonding the first semiconductor device and the second semiconductor device along a bond line to position the transmission region including the vertically-arranged trench structure below the photodiode structure.

[0128] Figure 1 The number and arrangement of devices shown is provided as one or more examples. In practice, there can be additional devices, fewer devices, different devices, or differently arranged devices than those shown. Figure 1 Furthermore, two or more devices shown in Figure 1 may be implemented in a single device, or Figure 1 a single device shown in may be implemented in multiple, distributed devices. In addition, environmental 100 can include any number of devices not explicitly shown in

[0129] Figures 2A-2C An embodiment of a backside transmission region in a photonic element 200 is shown. In some embodiments, the photonic element 200 is included as part of a light communication system to generate light waves for communication with a laser.Figures 2A-2C In each of Figures 2A-2D, the optoelectronic element 200 includes a semiconductor device 202 (e.g., a higher layer semiconductor device) bonded to a semiconductor device 204 (e.g., a lower layer semiconductor device) along a bond wire 206 (e.g., a region can include a metal bond pad bonded by a eutectic bond, among other examples).

[0130] As shown in Figure 2A, the semiconductor device 202 includes a substrate layer 208 (e.g., a silicon (Si) material layer or other suitable semiconductor material, among other examples), a layer stack 210 (e.g., a layer stack can include a combination of dielectric layers, conductive layers, and / or etch stop layers (ESLs), among other examples), and a photodiode structure 212. The photodiode structure 212 can include a combination of doped regions 214 (e.g., N-type doped regions and / or P-type doped regions) forming a p-n junction of the photodiode structure 212. Figure 2A In some embodiments, as shown in Figure 2B, the photodiode structure 212 includes a connection structure 216 (e.g., a vertical via structure) connected to a metal pad 218. The connection structure 216 and / or the metal pad 218 can include a conductive metal material, such as a tungsten (W) material, an aluminum (Al) material, or a copper (Cu) material, among other examples. In addition, as shown in Figure 2B, an under bump metal (UBM) pad 220 can be connected to the metal pad 218 to provide a signal path from the photodiode structure 212 to a solder bump or other external connection type of structure.

[0131] Figure 2A In some embodiments, as shown in Figure 2C, the semiconductor device 202 includes a layer stack 222 (e.g., a layer stack can include a combination of dielectric layers, conductive layers, and / or etch stop layers (ESLs), among other examples) connected to the photodiode structure 212. The layer stack 222 can include a combination of materials, such as a silicon (Si) material, a silicon dioxide (SiO2) material, or a gallium arsenide (GaAs), among other examples. Figure 2A In some embodiments, as shown in Figure 2D, the semiconductor device 202 includes a layer stack 222 (e.g., a layer stack can include a combination of dielectric layers, conductive layers, and / or etch stop layers (ESLs), among other examples) connected to the photodiode structure 212. The layer stack 222 can include a combination of materials, such as a silicon (Si) material, a silicon dioxide (SiO2) material, or a gallium arsenide (GaAs), among other examples.

[0132] Figure 2A In some embodiments, as shown in Figure 2E, the semiconductor device 202 can include a strip waveguide structure 224 and 226, a waveguide transition structure 228, and / or a distributed Bragg reflector (DBR) structure 230. Each of the strip waveguide structure 224 and 226, the waveguide transition structure 228, and / or the DBR structure 230 can include respective configurations, and / or a combination of a light-transmissive material (e.g., a silicon (Si) material, a silicon dioxide (SiO2) material, or a gallium arsenide (GaAs), among other examples), and / or a light-reflective material (e.g., an aluminum (Al) material, a chromium (Cr) material, and / or a nickel (Ni) material, among other examples).

[0133] In some embodiments, as shown in Figure 2F, the semiconductor device 202 can include a strip waveguide structure 224 and 226, a waveguide transition structure 228, and / or a DBR structure 230. Each of the strip waveguide structure 224 and 226, the waveguide transition structure 228, and / or the DBR structure 230 can include respective configurations, and / or a combination of a light-transmissive material (e.g., a Si material, a SiO2 material, or a GaAs, among other examples), and / or a light-reflective material (e.g., an Al material, a Cr material, and / or a Ni material, among other examples). Figure 2A ​​As shown, the semiconductor device 204 includes a substrate layer 232 (e.g., a layer of silicon material). The semiconductor device 204 also includes a dielectric layer 234 (e.g., a layer of an oxide material such as silicon dioxide (SiO2) or aluminum oxide (Al2O3), among other examples) positioned below the substrate layer 232.

[0134] In some embodiments, as shown, Figure 2A As shown, the semiconductor device 204 includes a transmissive region 236a (e.g., a backside transmissive region). The transmissive region 236a includes trench structures 238a-c, and each of the trench structures is vertically aligned in a direction that is approximately orthogonal to the bonding wire 206. Each of the trench structures 238a-c includes a portion 240a that penetrates the dielectric layer 234, and a portion 240b that partially penetrates the substrate layer 232. In addition, each of the trench structures 238a-c can include a gas (e.g., air) that is transparent to light waves.

[0135] In some embodiments, as shown, Figure 2A As shown, the optical structure 242a can be on and / or within sidewalls of the portion 240b. As shown, Figure 2A As shown, the optical structure 242a can be an echelle grating structure (e.g., a structure for light diffraction). Alternatively, the optical structure 242a can be a distributed Bragg reflector (DBR) structure or a metal reflector structure. In some embodiments, the metal pattern of the optical structure 242a includes one or more of the following materials: aluminum (Al) material, aluminum copper (AlCu) material, aluminum copper silicon (AlSiCu) material, aluminum silicon (AlSi) material, or aluminum chromium (AlCr) material, among other examples.

[0136] As shown, Figure 2A The trench structures 238a-c are used to transmit and / or transfer light waves 244a-c into the semiconductor device 202 for transmission to the photodiode structure 212. In some embodiments, the light waves 244a-c pass through the trench structures 238a-c unimpeded. In some embodiments, the light waves 244a-c originate from a laser element that is included in a portion of an optical communication system (the laser element uses a group III / group V element laser diode, among other examples). In some embodiments, each of the light waves 244a-c includes a different wavelength of electromagnetic waves.

[0137] In some embodiments, as shown, Figure 2AAs shown, adjacent trench structures can penetrate into the semiconductor device 204 to different heights. For example, the trench structure 238a can penetrate into the semiconductor device 204 to a height Hl, while the trench structure 238b (as an adjacent trench structure) can penetrate into the semiconductor device 204 to a height H2, where the height H2 is less than the height Hl.

[0138] In some embodiments, the design or selected height of the trench structures are used to filter and / or reflect light, as well as to transmit certain wavelengths of electromagnetic waves (in other words, the light waves 244a-c can include different wavelengths of electromagnetic waves). For example, the light wave 244a that penetrates the trench structure 238a can include electromagnetic waves having a wavelength of approximately 850 nm, the light wave 244b that penetrates the trench structure 238b can include electromagnetic waves having a wavelength of approximately 1300 nm, and the light wave 244c that penetrates the trench structure 238c can include electromagnetic waves having a wavelength of approximately 1500 nm, among other examples. However, combinations of different wavelengths are within the scope of the disclosure.

[0139] As shown in the embodiment of FIG. 2B, the semiconductor device 204 includes a transmission region 236b. In contrast to the transmission region 236a described above, the transmission region 236b includes trench structures 238d, 238e, 238f, each of which includes a portion 240c (e.g., a single portion) that penetrates the dielectric layer 234, e.g., each of the trench structures 238d-f does not include a portion that penetrates into the substrate layer 232. In addition, each of the trench structures 238d-f can include a gas (e.g., air) that is transparent to light waves. Figure 2B Figure 2A In some embodiments, as shown in FIG. 2B, the optical structure 242b can be on the sidewalls and / or inner surface of the portion 240c. As shown in FIG. 2B, the optical structure 242b can be a reflective coating layer that includes one or more of the following materials: silicon dioxide (Si02) material, titanium dioxide (Ti02), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum nitride (AIN), or gallium nitride (GaN), among other examples.

[0140] In some embodiments, as shown in FIG. 2B, the optical structure 242b can be on the sidewalls and / or inner surface of the portion 240c. As shown in FIG. 2B, the optical structure 242b can be a reflective coating layer that includes one or more of the following materials: silicon dioxide (Si02) material, titanium dioxide (Ti02), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum nitride (AIN), or gallium nitride (GaN), among other examples. Figure 2B Figure 2B In some embodiments, as shown in FIG. 2B, the optical structure 242b can be on the sidewalls and / or inner surface of the portion 240c. As shown in FIG. 2B, the optical structure 242b can be a reflective coating layer that includes one or more of the following materials: silicon dioxide (Si02) material, titanium dioxide (Ti02), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum nitride (AIN), or gallium nitride (GaN), among other examples.

[0141] ​​Each of trench structures 238d to 238f may penetrate into the semiconductor device 240 at approximately the same height H3. Additionally, each of trench structures 238d to 238f may transmit and / or penetrate light wave 244d into the semiconductor device 202 for transmission to the photodiode structure 212. In some embodiments, light wave 244d penetrates unimpeded through trench structures 238d to 238f. In some embodiments, light wave 244d originates from a laser element, which is part of an optical communication system (the laser element uses a group III / V element laser diode, and other examples). In some embodiments, light wave 244d may contain electromagnetic waves of different wavelengths.

[0142] like Figure 2C As shown in the embodiment, the semiconductor device 204 includes a transmissive region 236c. Relative to Figure 2A The transmission region 236a and Figure 2B The transmission regions 236b and 236c include trench structures 238g, 238h, and 238i, each of which includes a microlens structure 246 aligned with approximately the central axis 248 of portion 240c. The microlens structure 246 may be located near one end of portion 240c close to the bonding line 206. Furthermore, in some embodiments, such as... Figure 2C As shown, the microlens structure 246 has a convex shape.

[0143] In some embodiments, such as Figure 2C As shown, optical structure 242c may be on the sidewall and / or inner surface of portion 240c, and close to microlens structure 246. For example... Figure 2C As shown, the optical structure 242c may be a reflective coating layer comprising one or more of the following materials: silicon dioxide (SiO2), titanium dioxide (TiO2), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum nitride (AlN), or gallium nitride (GaN), and other examples.

[0144] Each of the trench structures 238d to 238f may be used to transmit and / or transfer light wave 244d into the semiconductor device 202 for transmission to the photodiode structure 212. Furthermore, each of the trench structures 238ad to 238f may contain a gas (such as air) that is permeable to light waves.

[0145] In some embodiments, the light waves 244d pass through the trench structures 238d- 238f unimpeded. In some embodiments, the light waves 244d originate from a laser element, which is included in a portion of an optical communication system (laser elements using Group III / Group V element laser diodes, among other examples). In some embodiments, the light waves 244d include electromagnetic waves of similar and proximate wavelengths. In some embodiments, the light waves 244d can include electromagnetic waves of different wavelengths. In some embodiments, when the light waves 244d enter the semiconductor device 202, the microlens structure 246 can concentrate and / or redirect the light waves 244d.

[0146] As Figures 2A-2C As described elsewhere herein, a device (e.g., optoelectronic element 200) includes a first semiconductor device (e.g., semiconductor device 202) including a photodiode structure (e.g., photodiode structure 212). The device includes a second semiconductor device (e.g., semiconductor device 204) positioned below the first semiconductor device, bonded to the first semiconductor device along a bond line (e.g., bond line 206), and including a trench structure (e.g., trench structure 238) arranged in approximately orthogonal relation to the bond line, wherein the trench structure can transmit light waves (e.g., light waves 244a, 244b, 244c, or 244d) into the first semiconductor device for transmission to the photodiode structure 212.

[0147] Additionally, as Figures 2A-2C As described elsewhere herein, a device (e.g., optoelectronic element 200) can perform a series of operations. The series of operations can include receiving light (e.g., light waves 244) through a vertically arranged trench structure (e.g., trench structure 238) into a lower semiconductor device (e.g., semiconductor device 204). The method can include transferring the light to a photodiode structure (e.g., photodiode structure 212) into a higher semiconductor device (semiconductor device 202) bonded to the lower semiconductor device.

[0148] As such, the performance of the optoelectronic element 200 can be increased, which can result in the optoelectronic element 200 achieving better performance (e.g., increased efficiency and / or sensitivity of the photodiode structure 212) than other optoelectronic elements that do not include a trench structure. By increasing the yield of the optoelectronic element, the optoelectronic element can be classified into a higher performance category and / or a higher quality product category can be improved.

[0149] Figures 2A-2C The number and arrangement of devices shown is provided as one or more examples. In practice, there can be additional devices, fewer devices, different devices, or differently arranged devices than those shown. Figures 2A-2C As shown, there can be additional devices, fewer devices, different devices, or differently arranged devices than those shown. For example, Figures 2A-2CThe back-side transmission region 236 may include a different number (e.g., 1, 2, 3, 4, etc.) of vertically arranged groove structures 238. Furthermore, Figures 2A-2C Two or more devices may be implemented in a single device, or Figures 2A-2C A single device in a system may be implemented in multiple distributed devices.

[0150] As mentioned above, Figures 2A-2C The embodiments provided are examples. Other examples may be similar. Figures 3A-3I The descriptions are different.

[0151] In this article, Figure 3A These are examples of semiconductor process operations 300 to manufacture semiconductor devices (such as semiconductor device 202), wherein the semiconductor device includes a photodiode structure (such as photodiode structure 212).

[0152] like Figure 3B As shown, a void 302 is formed in substrate layer 208a (such as a first portion of substrate layer 208) and penetrates the substrate layer to the polysilicon layer 304 located below it, wherein substrate layer 208a may be formed above polysilicon layer 304. In some embodiments, the pattern within the photoresist layer is used to etch substrate layer 208a and / or polysilicon layer 304 to form void 302. In these embodiments, deposition tool 102 may be used to form photoresist layer on substrate layer 208a. Exposure tool 104 may be used to expose and pattern the photoresist layer with a radiation source. Development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. Etching tool 108 may be used to etch substrate layer 208a and / or polysilicon layer 304 to form void 302. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, a photoresist removal tool may be used to remove portions remaining on the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other methods). In some embodiments, a hard mask is used as an alternative method to etch the substrate layer 208a and / or the polysilicon layer 304 according to the pattern.

[0153] like Figure 1 As shown, substrate layer 208b (such as a second portion of substrate layer 208) is formed above and / or directly on substrate layer 208a. Deposition tool 102 may be used to deposit substrate layer 208b using operations including physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), epitaxy, oxidation, and others. Figure 3BThe aforementioned deposition operation, and / or other suitable deposition operations. In some embodiments, the planarization tool 110 may be used to planarize the deposited substrate layer 208b. For example... Figure 3A As shown, forming substrate layer 208b may include bonding with substrate layer 208a to complete substrate layer 208. Additionally, forming substrate layer 208b may form striped waveguide structure 224 (such as filling...). Figure 3C The aforementioned void 302 is used to form a striped waveguide structure 224.

[0154] like Figure 1 As shown, a layer stack 308 (which may include multiple layers, such as dielectric layers, conductive layers, polysilicon layers, and / or etch stop layers (ESLs)) is formed on and / or above the substrate layer 208. The deposition tool 102 and / or the electroplating tool 112 may deposit one or more layers of the layer stack 308 using operations including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, and others. Figure 3C The aforementioned deposition operation, and / or other suitable deposition operations. In some embodiments, the planarization tool 110 may be used to planarize the deposited layer stack 308.

[0155] In addition, such as Figure 3D As shown, voids 310, 312, 314, and 316 are formed and penetrate the layer stack 308 into the substrate layer 208. Voids 310, 312, 314, and 316 may have combinations of features and / or depths. In some embodiments, a combination and / or series of patterns within the photoresist layer may be used to etch the substrate layer 208 to form voids 310 to 316. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on the layer stack 308. An exposure tool 104 may be used to expose the photoresist layer with a radiation source to create a combination and / or series of patterns within the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to expose the combination and / or series of patterns within the photoresist layer. An etching tool 108 may be used to etch the layer stack 308 and the substrate layer 208 according to the combination and / or series of patterns to form voids 310 to 316 in the layer stack 308 and the substrate layer 208. In some embodiments, the etching operation is performed using an etching tool 108, which includes plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, a photoresist removal tool may be used to remove portions remaining on the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other methods). In some embodiments, a hard mask is used as an alternative method to etch the substrate layer 208 according to a combination and / or series of patterns.

[0156] like Figure 1As shown, doped regions 214a and 214b are formed in substrate layer 208. Doped region 214a may be an N-type doped region, and doped region 214b may be a P-type doped region. As part of forming doped regions 214a and 214b, ion implantation tool 114 may be used to perform, for example... Figure 3E The aforementioned ion implantation procedure, and / or other suitable implantation procedures.

[0157] like Figure 1 As shown, a transmission region filler 318 (such as borosilicate glass) is formed (e.g., formed in voids 310 to 316). The deposition tool 102 may deposit a layer of the transmission region filler 318 using operations including physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), epitaxy, oxidation, and others. Figure 3F The aforementioned deposition operation, and / or other suitable deposition operations. In some embodiments, the planarization tool 110 may be used to planarize the previously deposited transmissive area filler 318.

[0158] like Figure 3G As shown, an etch-back operation is performed to remove a portion of the layer stack 308. In some embodiments, the pattern in the photoresist layer is used to etch and / or remove portions of the layer stack 308. In such embodiments, a deposition tool 102 may be used to form the photoresist layer and / or over the transmissive region filler 318. An exposure tool 104 may expose the photoresist layer with a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 may be used to remove portions of the layer stack 308, which may include removing all of the layer stack 308. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool may be used to remove portions remaining in the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other methods).

[0159] like Figure 1 As shown, the planarization operation may be used to perform the formation of a striped waveguide structure 226, a waveguide transfer structure 228, and / or a distributed Bragg reflector structure 230. The planarization tool 110 may be used to perform, for example... Figure 3H The flattening operation described above, and / or other suitable flattening operations.

[0160] like Figure 2A As shown, the interlayer dielectric layer 320 (ILD) (as shown) Figure 1One layer of the aforementioned layer stack 210 may be formed on and / or above the substrate layer 208. The deposition tool 102 may deposit the interlayer dielectric layer 320 using operations including physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), epitaxy, oxidation, and others. Figure 3H The aforementioned deposition operation, and / or other suitable deposition operations. In some embodiments, the planarization tool 110 may be used to planarize the deposited interlayer dielectric layer 320.

[0161] like Figure 3I As shown, the void 322 penetrates the interlayer dielectric layer 320 and extends to the doped regions 214a and 214b. In some embodiments, the pattern in the photoresist layer is used to etch the interlayer dielectric layer 320 to form the void 322. In these embodiments, the deposition tool 102 may be used to form the photoresist layer on the interlayer dielectric layer 320. The exposure tool 104 may expose the photoresist layer with a radiation source to pattern the photoresist layer. The development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 may etch the interlayer dielectric layer 320 according to the pattern to form the void 322 in the interlayer dielectric layer 320. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, the photoresist removal tool may be used to remove portions remaining in the photoresist layer (e.g., using chemical photoresist solutions, plasma cleaning, and / or other methods). In some embodiments, a hard mask is used as an alternative method to etch the interlayer dielectric layer 320 according to a pattern.

[0162] like Figure 1 As shown, a connection structure 216 is formed. As part of forming the connection structure, the deposition tool 102 and / or electroplating tool 112 may deposit a conductive material layer and apply it to the connection structure 216 using operations including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, and others. Figure 3I The aforementioned deposition operation, and / or other suitable deposition operations. In some embodiments, the planarization tool 110 may be used to planarize the deposited transmissive region filler 318. In some embodiments, the planarization tool 110 may be used to planarize the deposited conductive material layer.

[0163] In addition, such as Figure 1As shown, the remaining layers of the layer stack 210 are formed on and / or over the substrate layer 208. The deposition tool 102 and / or the plating tool 112 can deposit additional layers with operations including chemical vapor deposition operations (CVD), physical vapor deposition operations (PVD), atomic layer deposition operations (ALD), plating operations, other Figure 3I The described deposition operations, and / or other suitable deposition operations. In some embodiments, the planarization tool 110 can be used to planarize the layer stack 210 after the layers have been deposited.

[0164] Additionally, as Figures 3A-3I shown, the metal pad 218 is formed in the layer stack 210. The deposition tool 102, the exposure tool 104, the development tool 106, and / or the etching tool 108 can be used to perform a series of operations including deposition, patterning, and etching operations to form the metal pad 218 in the layer stack 210.

[0165] As noted previously, a series of examples of semiconductor manufacturing operations are provided as Figures 3A-3I shown. Other examples can differ from Figures 4A-4E the described examples.

[0166] Figure 4A For the example of the semiconductor manufacturing operation 400, for manufacturing a portion of the optoelectronic element (such as the optoelectronic element 200), a backside transmission region (such as the transmission region 236a) is included herein.

[0167] As Figure 4B shown, the void 402 is formed in the substrate layer 232. In some embodiments, a pattern in a photoresist layer is used to etch the substrate layer 232 to form the void 402. In these embodiments, the deposition tool 102 can be used to form the photoresist layer on the substrate layer 232. The exposure tool 104 can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can etch the substrate layer 232 according to the pattern to form the void 402 in the substrate layer 232. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (such as using a chemical photoresist stripper, a plasma clean, and / or other methods). In some embodiments, a hard mask is used as an alternative method to etch the substrate layer 232 according to the pattern.

[0168] As Figure 4CAs shown, an optical structure 242a is formed as part of a forming portion 240b. Deposition tool 102, exposure tool 104, development tool 106, etching tool 108, and / or planarization tool 110 may be used to perform a series of operations, including deposition, patterning, etching, and / or planarization operations, to form the optical structure 242a. In some embodiments, the series of operations, including deposition, patterning, etching, and / or planarization operations, depends on the configuration and / or type of the optical structure 242a (e.g., a stepped grating structure, a Bragg reflector structure, or a metallic reflective structure). In some embodiments, forming the optical structure 242a involves using one or more of the following materials: aluminum (Al), aluminum-copper (AlCu), aluminum-copper-silicon (AlSiCu), aluminum-silicon (AlSi), or aluminum-chromium (AlCr), and other examples.

[0169] like Figure 4C As shown, dielectric layer 234 is formed on and / or above substrate layer 232. Furthermore, in some embodiments, for example... Figure 1 As shown, the dielectric layer filling portion 240b. The deposition tool 102 may deposit the dielectric layer 234 using operations including physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), epitaxy, oxidation, and others. Figure 4D The aforementioned deposition operation, and / or other suitable deposition operations. In some embodiments, the planarization tool 110 may be used to planarize the deposited dielectric layer 234.

[0170] like Figure 4EAs shown, forming the trench structures 238a-c in the transmission region 236a can include forming voids 404 that penetrate the dielectric layer 234 into the portion 240b. In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer 234 to form the voids 404. In these embodiments, the deposition tool 102 can be used to form the photoresist layer over the dielectric layer 234. The exposure tool 104 can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can etch the dielectric layer 234 according to the pattern to form the voids 404 in the dielectric layer 234. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical photoresist stripper, a plasma clean, and / or other methods). In some embodiments, a hard mask is used as an alternative method to etch the dielectric layer 234 according to the pattern. The transmission region 236a can be included in the semiconductor device 204.

[0171] As shown, the semiconductor device 204 is bonded to the semiconductor device 202 (e.g., formed as the semiconductor device 202 by the operations of Figures 3A-3I In some embodiments, the bonding / delamination tool 116 can be used to form a eutectic bond between the semiconductor device 202 and the semiconductor device 204 along the bond line 206. The bonded semiconductor devices 202 and 204 can be part of the optoelectronic element 200, as described above and elsewhere herein. Figures 2A-2C Figures 4A-4E As noted above, an example sequence of semiconductor manufacturing operations is provided as shown in FIG. 4. Other examples can differ from the example described in FIG. 4.

[0172] As noted above, an example sequence of semiconductor manufacturing operations is provided as shown in FIG. 4. Other examples can differ from the example described in FIG. 4. Figures 4A-4E Figures 5A-5E

[0173] Figures 5A-5E As an example of semiconductor manufacturing operations, to manufacture an optoelectronic element, a backside transmission region is included herein.

[0174] Figure 5A As an example of semiconductor manufacturing operations 500, to manufacture a portion of an optoelectronic element (e.g., the optoelectronic element 200), a backside transmission region (e.g., the transmission region 236a) is included herein. As shown in FIG. 5, the semiconductor manufacturing operations 500 include operations to form a backside transmission region in a semiconductor device (e.g., the semiconductor device 204). Figure 5B ​​​As shown, a void 502 is formed in the dielectric layer 234. In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer 234 to form the void 502. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on the dielectric layer 234. An exposure tool 104 may be used to expose the photoresist layer with a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 may etch the dielectric layer 234 according to the pattern to form the void 502 in the dielectric layer 234. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool may be used to remove portions remaining in the photoresist layer (e.g., using chemical photoresist solutions, plasma cleaning, and / or other methods). In some embodiments, a hard mask is used as an alternative method to etch the dielectric layer 234 according to the pattern.

[0175] like Figure 5A As shown, a conformal layer 504 (such as one or more layers of a transmission region and / or reflective material according to a selected optical structure type, such as a stepped grating structure, a Bragg reflector structure, or a metallic reflective structure) is formed on the dielectric layer 234 (such as containing...). Figure 1 Above the surface of the cavity 502. The deposition tool 102 may deposit a conformal layer using operations including physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), epitaxy, oxidation, and others. Figure 5C The aforementioned deposition operation, and / or other suitable deposition operations. In some embodiments, the planarization tool 110 may be used to planarize the conformal layer 504 that has already been deposited.

[0176] like Figure 5D As shown, a portion of the conformal layer 504 may be removed to expose the surface of the substrate layer 232. In some embodiments, the pattern in the photoresist layer is used to etch the conformal layer 504 to expose the surface of the substrate layer 232. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on the conformal layer 504. An exposure tool 104 may be used to expose the photoresist layer with a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 may expose the surface of the substrate layer 232 according to the pattern to etch the conformal layer 504. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, a photoresist removal tool may be used to remove portions remaining in the photoresist layer (e.g., using chemical photoresist solutions, plasma cleaning, and / or other methods). In some embodiments, a hard mask is used as an alternative method to etch the conformal layer 504 according to the pattern.

[0177] As shown in Figure 5E , trench structures 238j, 238k, 238l are formed to form transmission region 236d. As part of forming trench structures 238j-238l, planarization tool 110 can be used to remove portions of conformal layer 504 to form optical structures 506 (e.g., portions of echelette structures, Bragg reflector structures, or metal reflective structures) on surfaces of one or more of trench structures 238j-238l. Additionally, or alternatively as part of forming trench structures 238j-238l, deposition tool 102 can deposit (e.g., epitaxially grow) microlens structures 246 on surfaces of one or more of trench structures 238j-238l where substrate layer 232 is exposed.

[0178] As shown in Figures 5A-5D , semiconductor device 204 formed by Figures 3A-3I the operations described is bonded to semiconductor device 202 (e.g., semiconductor device 202 is formed by the operations described in Figures 2A-2C ). In some embodiments, bonding / detaching tool 116 can be used to form a eutectic bond between semiconductor device 202 and semiconductor device 204 along bond line 206. Bonded semiconductor devices 202 and 204 can be part of optoelectronic element 200, as described in Figures 5A-5E and elsewhere herein.

[0179] As noted previously, an example sequence of semiconductor manufacturing operations is provided as shown in Figures 5A-5E . Other sequences can differ from those described in Figure 6 .

[0180] Figure 6 is an example diagram of a device element 600. Device element 600 can be applied to one or more of semiconductor process tools 102-116 and / or wafer / die transport tool 118. In some embodiments, one or more of semiconductor process tools 102-116 and / or wafer / die transport tool 118 can include one or more device elements 600 and / or elements of one or more device elements 600. As shown in Figure 6 , device element 600 can include a bus 610, a processor 620, a memory 630, an input element 640, an output element 650, and / or a communication element 660.

[0181] Bus 610 can include one or more elements such that wired and / or wireless communication can be used for elements of device element 600. Bus 610 can couple Figure 6Two or more elements from among those in the system 600 can be coupled to one another, such as through operative coupling, communicative coupling, electronic coupling, and / or other electric coupling. For example, the bus 610 can include an electrical connection (such as a wire, trace, and / or pin) and / or a wireless bus. The processor 620 can include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, a special-purpose application integrated circuit chip, and / or other types of processing elements. The processor 620 can be implemented in hardware, firmware, and / or a combination of hardware and software. In some embodiments, the processor 620 can include one or more processors, where the multiple processors can perform one or more operations or processes as described elsewhere herein.

[0182] The memory 630 can include memory with and / or without volatility. For example, the memory 630 can include random access memory (RAM), read-only memory (ROM), a hard disk, and / or other types of memory (such as flash memory, magnetic memory, and / or optical memory). The memory 630 can include internal memory (such as access memory, read-only memory, or a hard disk) and / or removable memory (such as removable via a universal serial bus connection). The memory 630 can be a non-transitory computer-readable medium. The memory 630 can store information, one or more instructions, and / or software (such as one or more applications) related to the operation of the device elements 600. In some embodiments, the memory 630 can include one or more memories (such as communicatively coupled) with one or more processors (such as the processor 620), such as through the bus 610. The communicative coupling between the processor 620 and the memory 630 can enable the processor 620 to read and / or process data stored in the memory 630 and / or store data in the memory 630.

[0183] Input element 640 can enable device element 600 to receive input elements, such as user input and / or sensed input. For example, input element 640 can include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, a satellite navigation system sensor, an accelerometer, a gyroscope, and / or an actuator. Output element 650 can enable device element 600 to provide output elements, such as through a display, an audio speaker, and / or a light emitting diode. Communication element 660 can enable device element 600 to communicate with other devices through wired and / or wireless connections. For example, communication element 660 can include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0184] Device element 600 can perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium, such as memory 630, can store a series of instructions, such as one or more instructions or code, for execution by processor 620. Processor 620 can execute the series of instructions to perform one or more operations or processes described herein. In some embodiments, execution of the series of instructions by one or more processors 620 causes one or more processors 620 and / or device element 600 to perform one or more operations or processes described herein. In some embodiments, hardwired circuitry can be used in place of or in combination with instructions to perform one or more operations or processes described herein. Additionally or alternatively, processor 620 can be configured to perform one or more operations or processes described herein. Thus, embodiments described herein are not limited to any particular

[0185] Figure 6 The number and arrangement of components shown in FIG. 6 is provided as an example. Device element 600 can include additional devices, fewer devices, different devices, or differently arranged devices than those shown in FIG. 6. Additionally or alternatively, a set of elements (e.g., one or more elements) of device element 600 can perform one or more functions described as being performed by another set of elements of device element 600. Figure 7 Additionally or alternatively, a set of elements (e.g., one or more elements) of device element 600 can perform one or more functions described as being performed by another set of elements of device element 600.

[0186] Figure 7For an example flow of processes 700, which can relate to manufacturing optoelectronic elements including backside transmission regions as described herein, one or more processes can be performed Figure 7 using one or more semiconductor processing tools, such as one or more semiconductor processing tools 102-116. Additionally or alternatively, one or more processes can be performed Figure 7 using one or more elements of device element 600, such as processor 620, memory 630, input element 640, output element 650, and / or communication element 660.

[0187] As shown in Figure 7 processes 700 can include forming an optoelectronic diode structure in a first semiconductor device (block 710). For example, as described herein, one or more semiconductor processing tools 102-116 can be used to form an optoelectronic diode structure, such as optoelectronic diode structure 212, in a first semiconductor device, such as semiconductor device 202.

[0188] As further shown in Figure 7 processes 700 can include forming a transmission region including vertically aligned trench structures in a second semiconductor device (block 720). For example, as described herein, one or more semiconductor processing tools 102-116 can be used to form a transmission region including vertically aligned trench structures, such as trench structures 238, in a second semiconductor device, such as semiconductor device 204. In some embodiments, the transmission region can be transmissive to light waves, such as light waves 244.

[0189] As further shown in Figure 7 processes 700 can include bonding the first semiconductor device and the second semiconductor device along a bond line to position the transmission region and the vertically aligned trench structures beneath the optoelectronic diode structure (block 730). For example, as described herein, one or more semiconductor processing tools 102-116 can be used to bond the first semiconductor device and the second semiconductor device along a bond line, such as bond line 206, to position the transmission region and the vertically aligned trench structures beneath the optoelectronic diode structure.

[0190] Processes 700 can include additional embodiments, such as any of the embodiments of one or more processes described below and / or any combination of one or more process embodiments described elsewhere herein.

[0191] In a first embodiment, forming a transmissive region comprising a vertically aligned trench structure in a second semiconductor device includes forming a first void (e.g., void 402) in a substrate layer (e.g., substrate layer 232), forming a stepped grating structure (e.g., in the form of optical structure 242a) in the first void, forming a dielectric layer (e.g., dielectric layer 234) over the stepped grating structure and above the substrate layer, and forming a second void (e.g., void 404) through the dielectric layer to the stepped grating structure.

[0192] A second embodiment, which can be independent or in combination with the first embodiment, includes forming a transmissive region comprising a vertically aligned trench structure in a second semiconductor device includes forming a first void (e.g., void 502) in a dielectric layer (e.g., dielectric layer 234), and forming a reflective structure (e.g., optical structure 506) in the void.

[0193] A third embodiment, which can be independent or in combination with one or more of the first and second embodiments, includes forming a transmissive region comprising a vertically aligned trench structure, and further includes forming a microlens structure (e.g., microlens structure 246) over a substrate layer (e.g., substrate layer 232) and exposed to a bottom of the void.

[0194] A fourth embodiment, which can be independent or in combination with one or more of the first through third embodiments, includes forming a reflective structure in a void, including forming one or more conformal layers (e.g., conformal layer 504) of the reflective structure on a surface of a dielectric layer and the void, and removing portions of the one or more conformal layers from a bottom surface of the void.

[0195] A fifth embodiment, which can be independent or in combination with one or more of the first through fourth embodiments, includes forming a reflective structure in a void, including forming a Bragg reflector structure in the void.

[0196] Although Figure 7 An example of blocks of process 700 is shown. In some embodiments, process 700 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those shown in FIG. 7. Additionally, two or more of the blocks of process 700 can be performed concurrently. Figure 8 An example of blocks of process 700 is shown. In some embodiments, process 700 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those shown in FIG. 7. Additionally, two or more of the blocks of process 700 can be performed concurrently.

[0197] Figures 2A-2C An operational flow of a photovoltaic element including a backside transmissive region. As described herein and elsewhere, the photovoltaic element can be photovoltaic element 200. Additionally, as described herein and elsewhere, the backside transmissive region can be backside transmissive region 236. Figures 2A-2C An operational flow of a photovoltaic element including a backside transmissive region. As described herein and elsewhere, the photovoltaic element can be photovoltaic element 200. Additionally, as described herein and elsewhere, the backside transmissive region can be backside transmissive region 236. Figure 8 An operational flow of a photovoltaic element including a backside transmissive region. As described herein and elsewhere, the photovoltaic element can be photovoltaic element 200. Additionally, as described herein and elsewhere, the backside transmissive region can be backside transmissive region 236.

[0198] As Figure 8As shown, process 800 can include receiving light via a vertically aligned trench structure within a lower layer semiconductor device (block 810). For example, optoelectronic component 200 can receive light (e.g., light wave 244) via a vertically aligned trench structure (e.g., trench structure 238) within a lower layer semiconductor device (e.g., semiconductor device 204), as previously described.

[0199] As Figure 8 As further shown, process 800 can include delivering light to a photodiode structure of a higher layer semiconductor device bonded to the lower layer semiconductor device (block 820). For example, optoelectronic component 200 can deliver light to a photodiode structure (e.g., photodiode structure 212) within a higher layer semiconductor device (e.g., semiconductor device 202) bonded to the lower layer semiconductor device, as previously described.

[0200] Process 800 can include other additional embodiments, such as any single embodiment, or any combination of one or more embodiments of processes mentioned below and / or elsewhere herein.

[0201] In a first embodiment, receiving light via a vertically aligned trench structure within a lower layer semiconductor device includes receiving light via the vertically aligned trench structure, wherein the light is unobstructed in the vertically aligned trench structure.

[0202] A second embodiment, which can be independent or in combination with the first embodiment, includes, in the second embodiment, receiving light via a vertically aligned trench structure within a lower layer semiconductor device includes using a microlens structure (e.g., microlens structure 246) in the vertically aligned trench structure to concentrate the light.

[0203] A third embodiment, which can be independent or in combination with the first and second embodiments, includes, in the third embodiment, delivering light to a photodiode structure within a higher layer semiconductor device bonded to the lower layer semiconductor device includes delivering the light through or around a striated waveguide structure (e.g., striated waveguide structure 224) within the higher layer semiconductor device.

[0204] A fourth embodiment, which can be independent or in combination with one or more of the first through third embodiments, includes, in the fourth embodiment, delivering light to a photodiode structure within a higher layer semiconductor device bonded to the lower layer semiconductor device includes using a reflective coating layer to reflect the light into the vertically aligned trench structure, wherein the reflective coating layer includes one or more of a silicon dioxide (SiO2) material, a titanium dioxide (TiO2) material, an aluminum arsenide (AlAs) material, a gallium arsenide (GaAs) material, an aluminum nitride (AIN) material, or a gallium nitride (GaN) material.

[0205] Although Figure 8An example of the blocks of process 800 is shown. In some embodiments, process 800 includes additional blocks, fewer blocks, different blocks, or blocks in a different order than those shown in FIG. 8. Additionally, two or more of the blocks of process 800 can be performed concurrently. ​ An example of the blocks of process 800 is shown. In some embodiments, process 800 includes additional blocks, fewer blocks, different blocks, or blocks in a different order than those shown in FIG. 8. Additionally, two or more of the blocks of process 800 can be performed concurrently.

[0206] Techniques and apparatuses provided in some embodiments described herein provide semiconductor devices including photovoltaic elements with backside transmission regions and methods of manufacture. A semiconductor device includes a first semiconductor device stacked over a second semiconductor device, where the first semiconductor device includes a photovoltaic diode and the second semiconductor device includes a backside transmission region. The backside transmission region is positioned below the photovoltaic diode in the first semiconductor device and includes a trench structure with a high reflectivity structure and / or the trench structure has properties that maintain light intensity of light waves transmitted through the backside transmission region. The voids within the trench structure reduce the likelihood of interference that can cause other transmission losses (e.g., reflection losses, absorption losses, scattering losses, and / or modal mismatch losses) associated with the transmission region adjacent to the photovoltaic diode structure. In some embodiments, the trench structure includes one or more reflective properties to maintain light intensity of light waves transmitted through the transmission region.

[0207] As such, the performance of the photovoltaic elements can be increased, which can result in the photovoltaic elements outperforming other photovoltaic elements that do not include the trench structure and / or the microlens structure in the backside transmission region. By increasing the yield of the photovoltaic elements, the photovoltaic elements can be classified into a higher performance category and / or a higher quality product category can be improved.

[0208] As shown by the details described above, some embodiments herein provide a device. The device includes a first semiconductor device that also includes a photovoltaic diode structure. The device includes a second semiconductor device positioned below the first semiconductor device and bonded to the first semiconductor device along a bonding wire, and includes a trench structure configured in a direction approximately orthogonal to the bonding wire and configured to transmit a plurality of light waves into the first semiconductor device to the photovoltaic diode.

[0209] As shown by the details described above, some embodiments herein provide a method. The method includes forming a photovoltaic diode structure in a first semiconductor device. The method includes forming a transmission region in a second semiconductor device, the transmission region including a vertically arranged trench structure, where the transmission region is transparent to light waves. The method includes bonding the first semiconductor device and the second semiconductor device along a bonding wire to position the transmission region including the vertically arranged trench structure below the photovoltaic diode structure.

[0210] As shown by the details previously described, some embodiments herein provide a method. The method includes receiving light via a vertically aligned trench structure of a lower layer semiconductor device. The method includes transmitting the light to a photodiode structure within an upper layer semiconductor device, where the upper layer semiconductor device is bonded to the lower layer semiconductor device.

[0211] References to "satisfying a threshold" herein can refer to being greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, or other similar, depending on the context.

[0212] References to the term "and / or" herein when used in connection with a list of items, tend to encompass each of the items in the list, as well as independent combinations of the items in the list. For example, "A and / or B" indicates that the group includes "A and B," "A and not B," "B and not A," as well as the individual items A and B.

[0213] In one embodiment, an apparatus includes a first semiconductor device and a second semiconductor device, where the second semiconductor device is located below the first semiconductor device and bonded to the first semiconductor device along a bond line. The first semiconductor device includes a photodiode structure. The second semiconductor device includes a backside transmission region of a trench structure, where the trench structure is configured in a direction approximately orthogonal to the bond line. The trench structure is configured to transmit a plurality of light waves into the first semiconductor device for transmission to the photodiode.

[0214] In some embodiments, the trench structure includes a portion of a dielectric layer through the second semiconductor device, and the portion includes a gas that is transparent to the light waves, and a distributed Bragg reflector structure that reflects and redirects light along a direction approximately orthogonal to the bond line on sidewalls of the portion.

[0215] In some embodiments, the trench structure further includes a microlens structure aligned with an approximate central axis of the portion and located near an end of the portion closest to the bond line.

[0216] In some embodiments, the trench structure includes a first portion of a dielectric layer through the second semiconductor device, and the first portion includes a gas that is transparent to the light waves, and a second portion in a substrate layer of the second semiconductor device above the dielectric layer, where the second portion is aligned with the first portion.

[0217] In some embodiments, inner surfaces of the second portion include a metal coating layer to reflect and redirect light along a direction approximately orthogonal to the bond line.

[0218] In some embodiments, the trench structure is a first trench structure, the direction is along a first direction that is approximately orthogonal to the bonding wire, the light wave is a first light wave of a plurality of first light waves, and the device further includes a second trench structure adjacent to the first trench structure, wherein the second trench structure is configured in a second direction that is approximately orthogonal to the bonding wire, and wherein the second trench structure is configured to transmit a second light wave of a plurality of second light waves into the first semiconductor device for transmission to the photodiode.

[0219] In some embodiments, the first trench extends through a first height of the second semiconductor device, and wherein the second trench structure extends through a second height of the second semiconductor device, wherein the second height is less than the first height.

[0220] In some embodiments, the first trench extends through a first height of the second semiconductor device, and wherein the second trench structure extends through a second height of the second semiconductor device, wherein the second height is approximately the same as the first height.

[0221] In some embodiments, the first light wave corresponds to a first wavelength of the plurality of light waves, and the second light wave corresponds to a second wavelength of the plurality of light waves.

[0222] In one embodiment, a method includes forming a photodiode structure in a first semiconductor device, forming a transmission region in a second semiconductor device, the transmission region including vertically-arranged trench structures, wherein the transmission region is transparent to a plurality of light waves; and bonding the first semiconductor device and the second semiconductor device along a bonding wire at the transmission region to position the transmission region including the vertically-arranged trench structures underneath the photodiode structure.

[0223] In some embodiments of the method, forming the transmission region including the vertically-arranged trench structures in the second semiconductor device includes forming a first cavity in a substrate layer, forming a stepped grating structure within the first cavity, forming a dielectric layer over the stepped grating structure and above the substrate layer, and forming a second cavity through the dielectric layer to the stepped grating structure.

[0224] In some embodiments of the method, forming the transmission region including the vertically-arranged trench structures in the second semiconductor device includes forming a cavity in the dielectric layer, and forming a reflective structure within the cavity.

[0225] In some embodiments of the method, forming the transmission region including the vertically-arranged trench structures further includes forming a microlens structure over the substrate layer exposed at a bottom of the cavity.

[0226] In some embodiments of the method, forming the reflective structure within the cavity includes forming one or more conformal layers of the reflective structure on a surface of the dielectric layer and the cavity, and removing a portion of the one or more conformal layers from a bottom surface of the cavity.

[0227] In some embodiments of the method, forming a reflective structure within the cavity includes forming a distributed Bragg reflector structure within the cavity.

[0228] In one embodiment, the method includes receiving light via the vertically aligned trench structures of the lower layer semiconductor device and transmitting the light to a photodiode structure within a higher layer semiconductor device bonded to the lower layer semiconductor device.

[0229] In some embodiments of the method, receiving light via the vertically aligned trench structures of the lower layer semiconductor device includes receiving light via the vertically aligned trench structures, wherein a plurality of the structures in the vertically aligned trench structures are open.

[0230] In some embodiments of the method, receiving light via the vertically aligned trench structures of the lower layer semiconductor device includes concentrating the light by a microlens structure in the vertically aligned trench structures.

[0231] In some embodiments of the method, transmitting light to a photodiode structure within a higher layer semiconductor device bonded to the lower layer semiconductor device includes propagating the light via or around a waveguide layer structure in the higher layer semiconductor device.

[0232] In some embodiments of the method, transmitting light to a photodiode structure within a higher layer semiconductor device bonded to the lower layer semiconductor device includes reflecting the light into the vertically aligned trench structures with a reflective coating layer, wherein the reflective coating layer includes one or more of a silicon dioxide (SiO2) material, a titanium dioxide (TiO2) material, an aluminum arsenide (AlAs) material, a gallium arsenide (GaAs) material, an aluminum nitride (AIN) material, or a gallium nitride (GaN) material.

[0233] In one embodiment, a semiconductor device includes a first semiconductor device and a second semiconductor device, wherein the second semiconductor device is located below the first semiconductor device and bonded to the first semiconductor device along a bond line. The first semiconductor device includes a photodiode structure. The second semiconductor device includes a backside transmissive region including trench structures. The trench structures are configured in a direction approximately orthogonal to the bond line. The trench structures are configured to transmit a plurality of light waves into the first semiconductor device for transmission to the photodiode. The trench structures further include a portion through a dielectric layer of the second semiconductor device and including a gas that is transparent to the light waves, and a distributed Bragg reflector structure that reflects and redirects light along a direction orthogonal to the bond line on a plurality of sidewalls of the portion.

[0234] In one embodiment, a semiconductor device includes a first semiconductor device and a second semiconductor device, where the second semiconductor device is located below the first semiconductor device and is bonded to the first semiconductor device along a bonding line. The first semiconductor device includes a photodiode structure. The second semiconductor device includes a backside transmissive region including a trench structure. Where the trench structure is configured in a direction approximately orthogonal to the bonding line. Where the trench structure is configured to transmit a plurality of light waves into the first semiconductor device for transmission to the photodiode. Where the trench structure includes a first portion through a dielectric layer of the second semiconductor device and includes a gas that is transparent to the light waves, and a second portion in a substrate layer of the second semiconductor device above the dielectric layer, where the second portion is aligned with the first portion.

[0235] The foregoing outlines features of several embodiments so that a thorough comprehension of the disclosure can be attained. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor device, characterized by comprising: Comprising: A first semiconductor device comprising: A photodiode structure; and A second semiconductor device underlying the first semiconductor device bonded to the first semiconductor device along a bond wire and comprising: A backside transmission region comprising a trench structure, wherein the trench structure is configured in a direction orthogonal to the bond wire, and wherein the trench structure is configured to transmit a plurality of light waves into the first semiconductor device for transmission to the photodiode structure.

2. The semiconductor device according to claim 1, wherein wherein the trench structure comprises: a portion through a dielectric layer of the second semiconductor device and comprising a gas transparent to the plurality of light waves, and a distributed Bragg reflector structure on sidewalls of the portion to reflect and redirect light along the direction orthogonal to the bond wire.

3. The semiconductor device according to claim 2, wherein further comprising: a microlens structure aligned with an approximate central axis of the portion and located proximate an endpoint of the portion nearest the bond wire.

4. The semiconductor device according to claim 1, wherein wherein the trench structure comprises: a first portion through a dielectric layer of the second semiconductor device and comprising a gas transparent to the plurality of light waves, and a second portion in a substrate layer of the second semiconductor device above the dielectric layer, wherein the second portion is aligned with the first portion.

5. The semiconductor device according to claim 4, wherein wherein interior surfaces of the second portion comprise a metal coating to reflect and redirect light along the direction orthogonal to the bond wire.

6. The semiconductor device according to claim 1, wherein wherein the trench structure is a first trench structure, the direction is along a first direction orthogonal to the bond wire, the plurality of light waves are a first plurality of light waves, and the device further comprises: a second trench structure adjacent to the first trench structure, wherein the second trench structure is configured in a second direction orthogonal to the bond wire, and wherein the second trench structure is configured to transmit a second plurality of light waves into the first semiconductor device for transmission to the photodiode.

7. The semiconductor device according to claim 6, wherein wherein the first trench passes through the second semiconductor device a first height, and wherein the second trench structure passes through the second semiconductor device a second height, wherein the second height is less than the first height.

8. The semiconductor device according to claim 6, wherein wherein the first trench passes through the second semiconductor device a first height, and wherein the second trench structure passes through the second semiconductor device a second height, wherein the second height is the same as the first height.

9. A semiconductor device, characterized by comprising: Comprising: A first semiconductor device comprising: A photodiode structure; and A second semiconductor device underlying the first semiconductor device bonded to the first semiconductor device along a bond wire and comprising: A backside transmission region comprising a trench structure, wherein the trench structure is configured in a direction orthogonal to the bond wire, wherein the trench structure is configured to transmit a plurality of light waves into the first semiconductor device for transmission to the photodiode structure, and wherein the trench structure further comprises a portion through a dielectric layer of the second semiconductor device and comprising a gas transparent to the plurality of light waves, and a distributed Bragg reflector structure on sidewalls of the portion to reflect and redirect light along the direction orthogonal to the bond wire.

10. A semiconductor device, characterized by comprising: Comprising: A first semiconductor device comprising: A photodiode structure; and A second semiconductor device underlying the first semiconductor device bonded to the first semiconductor device along a bond wire and comprising: A backside transmission region comprising a trench structure, wherein the trench structure is configured in a direction orthogonal to the bond wire, wherein the trench structure is configured to transmit a plurality of light waves into the first semiconductor device for transmission to the photodiode structure. A second semiconductor device is located below the first semiconductor device, bonded with the first semiconductor device along a bonding wire, and includes: a backside transmission region including a trench structure, wherein the trench structure is configured in a direction orthogonal to the bonding wire, wherein the trench structure is configured to transmit a plurality of light waves into the first semiconductor device for transmission to the photodiode structure, and wherein the trench structure includes a first portion passing through a dielectric layer of the second semiconductor device and including a gas that is transparent to the plurality of light waves, and a second portion located in a substrate layer of the second semiconductor device above the dielectric layer, wherein the second portion is aligned with the first portion.

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