Silicon wafer, battery piece and battery assembly

Abstract

The embodiment of the utility model provides a silicon wafer, a battery piece and a battery assembly. At least one surface of the silicon wafer is provided with a plurality of stripes, the stripes extend by taking a first direction as a reference, and the plurality of stripes are arranged at intervals along a second direction; the height difference Rt of the wave crest and the wave trough of the surface profile of the middle area of the surface meets the condition that Rt is larger than or equal to 2 micrometers and smaller than or equal to 8.5 micrometers. The first direction is the extension direction of the first side edge of the silicon wafer, and the second direction is the extension direction of the second side edge of the silicon wafer; the middle region refers to a region which is at least L / 3 away from the first side edge of the silicon wafer along the second direction, and L is the length of the second side edge. The flatness of the surface of the silicon wafer is relatively uniform, and the photoelectric conversion efficiency of a battery using the silicon wafer can be improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of photovoltaic processing, and particularly relates to a silicon wafer, a cell wafer and a cell assembly. BACKGROUND

[0002] In the processing of a solar silicon wafer, a cutting line is used to cut a silicon rod into a silicon wafer. However, in the process of cutting the silicon rod into the silicon wafer by using the cutting line, line marks are easily formed on the silicon wafer, resulting in unevenness of the surface profile of the silicon wafer in the direction perpendicular to the line marks.

[0003] In the prior art, attention is paid to the TTV (thickness variation of the silicon wafer) of the surface of the silicon wafer, and the TTV reflects the uniformity of the thickness of the silicon wafer and cannot reflect the uniformity of the flatness of the surface of the silicon wafer. The uniformity of the flatness of the surface of the silicon wafer can more directly reflect the quality of the surface profile of the silicon wafer. In the cell link, after the film layer on the silicon wafer is prepared, electrode grid lines are printed on the film layer. The thickness of the film layer is usually several nanometers to several hundred nanometers, and the thickness of the electrode grid lines is generally about 7 microns. The unevenness of the surface profile of the silicon wafer will lead to uneven width and thickness of the electrode grid lines, increase the resistance of the grid lines, and affect the current conduction, thereby affecting the photoelectric conversion efficiency of the cell. CONTENT OF THE UTILITY MODEL

[0004] The application aims to provide a silicon wafer, a cell wafer and a cell assembly to solve the problem of unevenness of the surface profile of the existing silicon wafer, which affects the photoelectric conversion efficiency.

[0005] To solve the above technical problem, the application is implemented as follows:

[0006] In a first aspect, the application discloses a silicon wafer, at least one surface of the silicon wafer has a plurality of stripes, the stripes extend in a first direction, and the plurality of stripes are arranged at intervals along a second direction; wherein the surface profile of a middle region of the surface satisfies 2 microns≤Rt≤8.5 microns.

[0007] The first direction is the extension direction of a first side edge of the silicon wafer, and the second direction is the extension direction of a second side edge of the silicon wafer; the middle region refers to a region at a distance of at least L / 3 from the first side edge of the silicon wafer along the second direction, and L is the length of the second side edge.

[0008] Optionally, the peak distance D of the surface profile of the middle region satisfies 1.4 millimeters≤D≤3.9 millimeters.

[0009] Optionally, the maximum line mark value Rmax of the surface of the silicon wafer is less than or equal to 17 microns.

[0010] Optionally, the stripe extends in an arc shape on the middle region, and a vertex of the stripe is located at the middle region of the surface along the first direction, and an end point of the stripe is located at the second side edge, wherein a distance between the vertex and the end point along the second direction is L2, and 1.5 mm < L2 < 2.5 mm is satisfied.

[0011] Optionally, a line connecting the vertex and the end point of the stripe is a first line, a line extending from the vertex of the stripe to the second side edge along the first direction is a second line, and an included angle between the first line and the second line is a, and 1° ≤ a ≤ 8° is satisfied.

[0012] Optionally, the surface has a damage layer, and a thickness of the damage layer is 3-5 microns.

[0013] Optionally, along the second direction, the surface is sequentially arranged with a first region, a second region and a third region; the middle region is located within the range of the second region; wherein a stripe density on the first region and the third region is greater than a stripe density on the second region.

[0014] The stripe density refers to a number of stripes within at least 5 mm along the second direction.

[0015] Optionally, a width of the first region along the second direction is a first width, a width of the second region along the second direction is a second width, and a width of the third region along the second direction is a third width; wherein,

[0016] The second width is greater than the first width and the third width.

[0017] Optionally, a total width of the silicon wafer along the second direction is a total width, a proportion of the first width in the total width is 25%-35%, a proportion of the second width in the total width is 54%-65%, and a proportion of the third width in the total width is 10%-20%.

[0018] Optionally, the first width is at least greater than 10 mm, and the third width is at least greater than 5 mm.

[0019] In a second aspect, the application further discloses a battery piece, comprising the silicon wafer.

[0020] In a third aspect, the application further discloses a photovoltaic module, comprising the battery piece.

[0021] In the embodiment of the present application, when adopting the diamond wire for line net cutting, the unevenness of the middle region of the silicon wafer is relatively larger than that of the two end regions of the silicon wafer. The present application limits the surface profile peak-valley height difference of the surface of the silicon wafer in the middle region, and the middle region is at least 1 / 3L away from the edge of the silicon wafer, so as to limit the surface profile peak-valley height difference of the middle region which can reflect the flatness quality of the surface of the silicon wafer, and then control the flatness quality of the whole surface of the silicon wafer.

[0022] In the embodiment of the present application, the middle region of the surface of the silicon wafer occupies a larger part of the surface of the silicon wafer, and the surface profile peak-valley height difference Rt of the middle region satisfies 2 microns≤Rt≤8.5 microns, so that the flatness of the surface of the silicon wafer is relatively uniform. In this way, after processing a film layer on the surface of the silicon wafer, in the process of printing the electrode grid lines on the film layer, due to the relatively uniform flatness of the silicon wafer, the width and thickness of the electrode grid lines are correspondingly relatively uniform, the grid line resistance is relatively small, and the current conduction on the grid lines is facilitated. Therefore, the photoelectric conversion efficiency of the battery using the silicon wafer can be improved.

[0023] The additional aspects and advantages of the present application will be partially given in the following description, and some will become apparent from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0024] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the following drawings, in which:

[0025] Figure 1 is a schematic diagram of a structure of a silicon wafer according to the embodiment of the present application;

[0026] Figure 2 is Figure 1 a simple schematic diagram of a structure of a silicon wafer;

[0027] Figure 3 is Figure 2 a cross-sectional structure schematic diagram of the silicon wafer from another angle;

[0028] Reference signs: 10-middle region, 11-first side, 12-second side, 13-stripe, 14-first region, 15-third region, 16-second region, x-first direction, y-second direction. DETAILED DESCRIPTION

[0029] The embodiments of the present application will be described in detail below, examples of which are shown in the drawings, wherein the same or similar notations represent the same or similar elements having the same or similar functions throughout. The embodiments described below by reference to the drawings are exemplary only, and are intended to explain the present application, and should not be understood as a limitation to the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work under the premise that the scope of protection of the present application.

[0030] The terms "first", "second" in the description and claims of the present application can explicitly or implicitly include one or more features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / ", generally indicates that the front and rear associated objects are in a "or" relationship.

[0031] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0032] In the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0033] Referring to Figure 1 , a schematic diagram of a silicon wafer structure according to an embodiment of the present application is shown; referring to Figure 2 , a simple schematic diagram of the structure of the silicon wafer shown in Figure 1 ; referring to Figure 3 , a schematic diagram of the cross-sectional structure of the silicon wafer from another angle shown in Figure 2 . In this embodiment, Figure 1A schematic diagram of a silicon wafer structure can be obtained through a silicon wafer sorting machine. For example... Figures 1 to 3 As shown, the silicon wafer specifically includes: at least one surface of the silicon wafer has a plurality of stripes 13, the stripes 13 extending with a first direction x as a reference, and the plurality of stripes 13 being spaced apart along a second direction y; wherein, the surface profile peak-valley height difference Rt in the middle region of the surface satisfies 2 micrometers ≤ Rt ≤ 8.5 micrometers; the first direction x is the extension direction of the first side 11 of the silicon wafer, and the second direction y is the extension direction of the second side 12 of the silicon wafer; the middle region 10 refers to the region along the second direction y that is at least 1 / 3L away from the first side 11 of the silicon wafer, where L is the length of the second side 12. Specifically, as one embodiment, the silicon wafer surface with a plurality of stripes refers to one or both surfaces that are disposed opposite to each other along the thickness direction of the silicon wafer.

[0034] In this embodiment, when using diamond wire for wire mesh cutting, the unevenness in the middle region of the silicon wafer is relatively greater than that at the two ends. This application addresses this by adjusting the slicing process to limit the peak-to-trough height difference of the surface profile on the silicon wafer surface within the middle region, and ensuring that the middle region is at least 1 / 3L from the edge of the silicon wafer. This limits the peak-to-trough height difference of the surface profile in the middle region, which reflects the surface flatness quality of the silicon wafer, thereby controlling the overall surface flatness quality of the silicon wafer.

[0035] This application controls the peak-to-trough height difference Rt of the surface profile in the intermediate region 10 to satisfy 2 μm ≤ Rt ≤ 8.5 μm. As an optional implementation, Rt can also be limited to 2 μm-4.5 μm or 4.5 μm-8.5 μm, etc.; the distance between the intermediate region and the edge of the silicon wafer can also be at least 2L / 5, thereby making the flatness of the silicon wafer surface more uniform. Thus, after processing the film layer on the silicon wafer surface, during the printing of electrode grid lines on the film layer, because the silicon wafer exhibits more uniform flatness, the width and thickness of the electrode grid lines are correspondingly more uniform, resulting in lower grid line resistance, which is beneficial for current conduction on the grid lines. Therefore, the photoelectric conversion efficiency of the battery using the silicon wafer can be improved.

[0036] In specific applications, the silicon wafer can be made by wire cutting a silicon rod. The silicon rod is fed perpendicular to the wire mesh, thereby cutting the silicon rod into silicon wafers. During the process of wire cutting the silicon rod to obtain the silicon wafer, stripes 13 are formed on the surface of the silicon wafer, and the density of the stripes 13 is related to the feed speed of the silicon rod. During silicon rod cutting, the silicon rod moves perpendicular to the wire mesh, and the feed speed of the silicon rod refers to the speed perpendicular to the stripe direction, that is, along the y-direction.

[0037] In practical applications, the cutting speed of the cutting line and the feeding speed of the silicon rod are usually not constant, but are adjusted according to actual conditions during the process of cutting the silicon rod to obtain the silicon wafer. Generally, the feeding speed of the silicon rod is adjusted at the infeed side, the middle position, and the outfeed side of the silicon rod, and accordingly, the strip 13 with different densities is formed at the infeed side, the middle region 10, and the outfeed side of the silicon wafer surface. In addition, the cutting line reciprocatingly cuts the silicon rod, that is, the cutting line has acceleration motion, uniform motion, and deceleration motion, and the cutting speed of the cutting line is along the X direction. When the linear speed of the cutting line accelerates from 0 to the set target speed, the appearance of the strip 13 (i.e., the bright strip with high brightness) is cut on the silicon wafer, and the width is equal to the acceleration process time multiplied by the feeding speed; when the line cuts at the target linear speed, the appearance between the textures (i.e., the dark strip with low brightness) is cut on the silicon wafer, and the width is equal to the cutting time of the target linear speed multiplied by the feeding speed. The bright strip and the dark strip are alternately distributed.

[0038] Specifically, in the embodiment of the present application, the cutting line can cut the silicon rod along the first direction x to form the strip 13 extending along the first direction x on the silicon wafer. The silicon rod can be fed along the second direction y to form a plurality of strips 13 distributed along the second direction y on the silicon wafer. As a cutting method, because the cutting line cuts the middle position of the silicon rod for the longest time, the feeding speed of the middle region of the silicon rod is the largest, and the linear speed is the largest, the surface profile of the middle region 10 of the silicon wafer is larger than the surface profile value Rt of the infeed region and the outfeed region of the silicon wafer. Therefore, the surface profile condition of the middle region 10 of the silicon wafer can be used to characterize the overall surface profile condition of the silicon wafer.

[0039] As shown in Figure 3 The cross-sectional shape of the plurality of strips 13 distributed along the second direction y of the middle region 10 of the silicon wafer is alternately arranged as wave peaks and wave troughs; wherein, Figure 3 It is only a schematic diagram of the surface profile data, which can also be alternately arranged as wave peaks and wave troughs. The wave peak is the center of the strip 13 or close to the center of the strip 13, and the wave trough can be formed between the adjacent two strips 13, and the surface profile wave peak-wave trough height difference Rt can be formed between the wave peak and the wave trough. Because the value of Rt satisfies 2 microns≤Rt≤8.5 microns, that is, the distribution range of the surface profile wave peak-wave trough height difference is small, and the flatness of the surface of the silicon wafer is relatively uniform. In this way, after the surface of the silicon wafer is processed with a film layer, and the electrode grid lines are printed on the film layer, because the silicon wafer has a relatively uniform flatness, the width and thickness of the electrode grid lines of the grid lines are correspondingly relatively uniform, and the grid line resistance is small, which is beneficial to the conduction of the current on the grid lines. Therefore, the photoelectric conversion efficiency of the battery using the silicon wafer can be improved.

[0040] In a specific application, as a detection method: the laser vertically scans the surface of the silicon wafer in a 11 mm window, uniformly taking points at intervals of 6 μm, about 1800 points in the 11 mm window, to form the corresponding profile in this window range; wherein the laser uses the triangulation displacement principle to obtain the profile data of the surface of the silicon wafer. In this embodiment, the laser displacement sensor is used to move in the direction perpendicular to the surface of the silicon wafer (knife mark), i.e. in the second direction, to select a region with a measurement range of 11 mm in the middle region 10, and to collect profile data of 1800 measurement points on the surface of the silicon wafer. Of course, according to the different models of the laser, such as the different powers of the laser, other window ranges can be selected, such as 15 mm, 20 mm window, etc., and other point densities can also be selected. The data collected by the laser displacement measurement sensor presents alternating peaks and valleys along the measurement direction, the difference values of a plurality of adjacent peaks and valleys are calculated, and the average value of the difference values is Rt, which is the height difference between the peaks and valleys of the profile of the surface of the silicon wafer; or the average value of a plurality of peak data and the average value of a plurality of valley data are calculated, and the difference is Rt. Preferably, at least 3 groups of data can be measured for each silicon wafer to obtain the average value. In this embodiment, the Rt is the data collected in a certain range of the profile of the surface of the silicon wafer, rather than a single point of random selection; therefore, it can be used to represent the flatness of the profile of the surface of the silicon wafer, and reflect the uniformity of the flatness of the surface of the silicon wafer.

[0041] In some optional embodiments of the present application, as shown in Figure 2 The peak distance D of the surface profile of the middle region 10 satisfies 1.4 mm≤D≤3.9 mm. The peak distance D can be the width between two adjacent valleys or two adjacent peaks in the obtained profile data along the measurement direction, which is approximately the distance between the centers of two adjacent stripes 13.

[0042] In actual application, during the process of cutting the silicon rod to obtain the silicon wafer, a damage layer is easily formed on the surface of the silicon wafer. The greater the depth of the damage layer, the lower the strength of the silicon wafer. In actual application, the serious area of the damage layer on the surface of the silicon wafer is prone to exist in the valley area, and by controlling the peak distance D, the width of the serious area of the damage layer along the second direction y can be controlled, so as to reasonably control the strength of the silicon wafer.

[0043] In the embodiments of the present application, by controlling the peak distance D of the surface profile of the middle region 10 to be between 1.4 mm and 3.9 mm, the peak distance D can neither be too large to affect the strength of the silicon wafer, nor be too small to affect the cutting efficiency of the silicon wafer, that is, the cutting efficiency and the strength of the silicon wafer can be considered at the same time.

[0044] For example, the crest spacing D of the surface profile of the intermediate region 10 can be any one of 1.4mm, 2.0mm, 2.7mm, 3.2mm and 3.9mm. In this embodiment of the application, the specific value of the crest spacing D of the surface profile of the intermediate region 10 is not limited.

[0045] In specific applications, the peak spacing D of the surface profile of the intermediate region 10 can be measured using tools such as a sorting machine or vernier calipers, or it can be obtained from the spacing between adjacent peaks or troughs arranged alternately along the measurement direction, as collected by a displacement sensor. This application embodiment does not specifically limit the method for measuring the peak spacing D of the surface profile of the intermediate region 10.

[0046] Optionally, the silicon wafer surface has a damage layer with a thickness of 3-5 micrometers to keep the thickness of the damage layer within a reasonable range. This avoids the damage layer being too deep and affecting the strength of the silicon wafer, while also preventing the damage layer from being too shallow and affecting the cutting efficiency of the silicon wafer. In practical applications, the thickness of the damage layer can be controlled by adjusting the cutting speed and quality of the cutting lines.

[0047] For example, the thickness of the damage layer on the silicon wafer surface can be 3 mm, 3.5 mm, 4.2 mm, 4.6 mm or 5 mm, etc. The embodiments of this application do not specifically limit the thickness of the damage layer.

[0048] like Figure 1 and Figure 2 As shown, stripe 13 extends in an arc shape on the middle region 10, with the vertex of stripe 13 located in the middle region 10 along the first direction x, and the endpoint of stripe 13 located on the second side 12. The distance between the vertex and the endpoint along the second direction y is L2, satisfying: 1.5 mm < L2 < 2.5 mm. Since L2 can be used to characterize the maximum span of a single stripe 13 along the second direction y, satisfying 1.5 mm < L2 < 2.5 mm allows for a smaller area spanned by a single stripe 13.

[0049] In practical applications, when printing gate lines on the silicon wafer, the gate lines can extend along the first direction x. When the peak spacing D on the silicon wafer surface satisfies 1.4mm ≤ D ≤ 3.9mm, and the distance L2 between the apex and the endpoint along the second direction y satisfies 1.5mm < L2 < 2.5mm, it facilitates the printing of gate lines on the silicon wafer surface while minimizing the peak and trough areas that a single gate line needs to cross, thus avoiding breakage of the gate line when crossing areas. Specifically, as one implementation, by controlling the peak spacing D and the distance L2, any gate line crosses no more than three stripes.

[0050] In practical applications, the dicing lines that form marks on the silicon wafer can affect the uniformity of the texturing pyramid and the depth of the etching process. The morphology of the peak regions on the silicon wafer surface (e.g., those cut at linear speed acceleration) is similar, as are the morphologies of the valley regions (e.g., those cut at a uniform speed). Controlling the width of the peak or valley regions allows most or all of a single cell gate line to be located within a single peak or valley region, ensuring better contact between the gate line and the silicon substrate in that region and thus preventing breakage when the gate line crosses regions.

[0051] For example, the distance L2 between the vertex and the endpoint of stripe 13 along the second direction y can be 1.5 mm, 1.8 mm, 1.9 mm, 2.0 mm, 2.3 mm or 2.5 mm, etc. In this embodiment of the application, the distance L2 between the vertex and the endpoint along the second direction y is not specifically limited.

[0052] like Figure 2 As shown, the line connecting the vertex and the endpoint of stripe 13 is the first line, and the line extending from the vertex of stripe 13 along the first direction x to the second side 12 is the second line. The angle between the first line and the second line is α, satisfying: 1°≤α≤8°. In practical applications, by controlling the size of the angle α, the distance L2 between the vertex and the endpoint of stripe 13 along the second direction y can be controlled to satisfy 1.5 mm < L2 < 2.5 mm. Furthermore, during the process of cutting the silicon wafer with a dicing wire, considering the direction of movement of the dicing wire, the dicing wire first contacts the second side 12. The angle between the extension direction of stripe 13 and the first direction x is the largest. If the maximum angle α is less than 45°, the 45° dissociation angle of the silicon rod can be avoided, reducing edge defects of the silicon wafer. That is, under the condition of satisfying 1°≤α≤8°, edge defects of the silicon wafer can also be avoided, reducing the breakage rate of the silicon wafer. Meanwhile, the angle between the first line and the second line on the silicon wafer is α, which can reflect the bow of the cutting line when the silicon rod is cut. The bow is the degree of curvature of the cutting line. The smaller the angle α, the smaller the bow; the smaller the bow, the stronger the cutting ability of the cutting line, resulting in a smoother silicon wafer surface.

[0053] For example, α can be 1°, 3°, 4°, 6° or 8°, etc. The specific value range of α is not limited in this embodiment of the application.

[0054] In practical applications, during the process of cutting the silicon wafer by the cutting line, line marks are also formed on the surface of the silicon wafer. The line mark is a combination of cutting lines with macroscopic undulating morphology on the surface of the silicon wafer. They are lower than the surface plane, similar to the gullies below the ground level, and arranged in the cutting direction. The line mark is due to the accumulation of abrasive particles on the line, and during cutting, a large amount of material is removed, resulting in a deep groove. In the embodiments of the present application, the maximum value of the line mark on the surface of the silicon wafer can be less than or equal to 17 microns, and further can be limited to less than or equal to 13 microns, so as to reduce the impact of the line mark on the strength of the silicon wafer, thereby reducing the breakage rate of the silicon wafer. Based on the limitation of the surface profile peak-to-valley height difference Rt, that is, the limitation of the uniformity of the surface flatness, the maximum value of the line mark is further limited, so as to limit the maximum value of the thickness direction unevenness, thereby further controlling the quality of the surface of the silicon wafer.

[0055] In some optional embodiments of the present application, as shown in Figure 1 and Figure 2 , the surface sequentially has a first region 14, a second region 16 and a third region 15, and the first region 14, the second region and the third region 15 are sequentially arranged along the second direction y; wherein the stripe density on the first region 14 and the third region 15 is greater than that on the second region. The stripe density refers to the number of stripes within at least 5 mm along the second direction. In actual silicon wafer products, according to the adjustment of the actual process and the distribution of the stripe density, the number of stripes within a range such as 8 mm, 10 mm, 12 mm, etc. can also be selected as the stripe density. Specifically, the first region 14 can be the infeed region of the surface of the silicon wafer, and the third region 15 can be the outfeed region of the surface of the silicon wafer. Wherein, the middle region 10 is located in the second region.

[0056] In practical applications, during the process of cutting the silicon rod to obtain the silicon wafer by the cutting line, when the cutting line is cut from the infeed surface, the silicon rod has a chamfer. In order to reduce the breakage rate of the chamfer area, the feeding speed of the silicon rod is slower, the number of reciprocating cutting cycles of the wire mesh is higher, and the corresponding cutting forms a denser stripe 13. In the middle position of the cutting, the cutting speed of the wire mesh is faster, the feeding speed of the silicon rod is faster, and the corresponding cutting forms a sparse stripe 13 arrangement. When cutting to the outfeed position, the silicon rod has a chamfer area and is close to the resin plate. In order to reduce the breakage rate when outfeeding, the cutting speed is very slow, the number of reciprocating cutting cycles of the wire mesh is also higher, and the corresponding cutting forms a dense stripe 13 arrangement.

[0057] Optionally, the first region 14 has a first width along the second direction y, the second region has a second width along the second direction y, and the third region 15 has a third width along the second direction y; wherein the second width is greater than the first width and the third width. Since the cutting speed of the second region is faster, by controlling the second width of the second region to be greater than the width of the infeed position and the outfeed position, the overall cutting speed of the silicon wafer can be made faster.

[0058] Optionally, the silicon wafer has a total width along the second direction y, the first width accounts for 25%-35% of the total width, the second width accounts for 54%-65% of the total width, and the third width accounts for 10%-20% of the total width. In actual slicing, the first width corresponds to the width of the infeed region, and the third width corresponds to the width of the outfeed region.

[0059] In a specific application, in the process of cutting the silicon wafer, by controlling the proportions of the first region 14, the second region, and the third region 15, the production cost is controlled by using new and old lines together while ensuring the surface topography quality of the silicon wafer, and then a silicon wafer product with three regions is produced. Since the infeed and outfeed regions of the silicon wafer are provided with chamfers, in order to reduce the problems such as edge defects, damage, and fragments in the chamfer region when the diamond wire cuts in the infeed and outfeed regions, the feed speed of the infeed and outfeed regions is different from that of the second region. Due to the different feed speeds of the infeed and outfeed regions and the second region, the width and number of the generated stripes 13 are different. In addition, considering the existence of chamfers in the four corner regions of the silicon wafer, by adjusting the widths of the first region 14 and the third region 15, the defect rate during slicing of the chamfer region of the silicon wafer can be reduced. At the same time, in the second region, the feed speed during slicing is adjusted to improve the cutting efficiency. That is, by adjusting the cutting speed of the cutting wire, three regions with different widths and densities of the stripes 13 can be formed on the surface of the silicon wafer, so as to balance the cutting efficiency and the cutting quality.

[0060] For example, the first width is at least greater than 10 mm, and specifically can be greater than 10 mm and less than 50 mm; and the third width is at least greater than 5 mm, and specifically can be greater than 5 mm and less than 35 mm. In actual application, by controlling the first width and the third width, the cutting defects of the silicon wafer caused by too small first width and third width can be avoided, and the low cutting efficiency of the silicon wafer caused by too large first width and third width can also be avoided. That is, by controlling the first width and the third width, the cutting quality and the cutting efficiency can be balanced.

[0061] The following provides an example of a cutting process of a silicon wafer according to an embodiment of the present application:

[0062] Step 1: providing a square bar, wherein the square bar is provided with chamfer on the infeed and outfeed side, and the first side length of the square bar is 182.2-210; the second side length of the square bar is 182.2-210.

[0063] Step 2: cutting the square bar to prepare a silicon wafer by using a slicing machine, wherein the slicing process specifically comprises:

[0064] ① the table speed (the feeding speed of the silicon rod) in the infeed area is 1.8-2.2 mm / min, the acceleration of the diamond wire is 5-6.5 m / s2, the depth of the feeding area is 3-7 mm, and the cutting wire is used for reciprocating and cyclic cutting.

[0065] ② after the cutting in the infeed area is completed, the table speed is adjusted to 2.0-2.5 mm / min, the acceleration of the cutting wire is 4.5-7 m / s2, the depth of the feeding area is 155-175 mm, and the cutting wire is used for reciprocating and cyclic cutting.

[0066] ③ in the outfeed area, the table speed is adjusted to 0.2-1.0 mm / min, the acceleration of the cutting wire is 5-6.5 m / s2, the depth of the feeding area is 10-20 mm, and the cutting wire is used for reciprocating and cyclic cutting.

[0067] The silicon wafer obtained through the above process satisfies 2 microns≤Rt≤8.5 microns for the surface profile peak-valley height difference Rt of the middle area of the surface of the silicon wafer. The surface profile peak distance D of the middle area satisfies 1.4 millimeters≤D≤3.9 millimeters. The maximum line scratch value Rmax of the surface of the silicon wafer is ≤17 microns, and Rmax can be further limited to ≤13 microns. The distance L2 between the vertex of the stripe 13 and the endpoint along the second direction y satisfies 1.5 millimeters

[0068] In summary, the silicon wafer described in the embodiments of the present application can at least have the following advantages:

[0069] In the embodiments of the present application, the middle area of the surface of the silicon wafer occupies most of the surface of the silicon wafer, and the unevenness of the middle area of the silicon wafer is relatively large compared with the area at both ends of the silicon wafer due to the wire mesh cutting of the diamond wire. By controlling the surface profile peak-valley height difference Rt of the middle area to satisfy 2 microns≤Rt≤8.5 microns, the uniformity of the surface of the silicon wafer can be made more uniform. After the surface of the silicon wafer is processed with a film layer, in the process of printing electrode grid lines on the film layer, the uniformity of the silicon wafer is relatively uniform, the width and thickness of the electrode grid lines are correspondingly uniform, and the grid line resistance is small, which is conducive to the conduction of the current on the grid line. Therefore, the photoelectric conversion efficiency of the battery using the silicon wafer can be improved.

[0070] The application further provides a battery piece, which can be made of the silicon piece.

[0071] In a specific application, in the process of making the battery piece from the silicon piece, a film layer needs to be formed on the surface of the silicon piece, and then a grid line is printed on the film layer. The middle region of the surface of the silicon piece can reflect the uniformity of the flatness of the surface of the silicon piece. Since the surface profile of the middle region has a height difference Rt of 2 microns≤Rt≤8.5 microns, the flatness of the surface of the silicon piece is relatively uniform. In the battery manufacturing process, the silicon piece will be subjected to wet processing, such as damage layer removal and etching processing, to remove a part of the thickness of the surface of the silicon piece, such as about 1 micron. In this way, after the film layer is processed on the surface of the silicon piece, in the process of printing the electrode grid line on the film layer, since the flatness of the surface of the silicon piece is relatively uniform, the flatness of the surface of the silicon piece after wet processing is more uniform, the width and thickness of the electrode grid line are correspondingly more uniform, the grid line resistance is smaller, and the current conduction on the grid line is facilitated. Therefore, the photoelectric conversion efficiency of the battery piece using the silicon piece can be improved.

[0072] The application further provides a photovoltaic module, which specifically can include the battery piece according to any one of the above embodiments.

[0073] In the embodiments of the application, the structure of the battery piece is the same as that of the battery piece according to any one of the above embodiments, and the beneficial effects are similar, which will not be described here.

[0074] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the application. In the specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0075] Although the embodiments of the application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and purposes of the application, and the scope of the application is defined by the claims and their equivalents.

Claims

1. A silicon wafer, characterized by, The silicon wafer has a plurality of stripes on at least one surface of the silicon wafer, the stripes extending along a first direction, and the plurality of stripes being spaced apart along a second direction; wherein a surface profile of a middle region of the surface satisfies 2 microns≤Rt≤8.5 microns. The first direction is an extension direction of a first side edge of the silicon wafer, and the second direction is an extension direction of a second side edge of the silicon wafer; and the middle region refers to a region at a distance of at least L / 3 from the first side edge of the silicon wafer along the second direction, L being a length of the second side edge.

2. The silicon wafer of claim 1, wherein A peak-to-peak distance D of the surface profile of the middle region satisfies 1.4 millimeters≤D≤3.9 millimeters.

3. The silicon wafer of claim 1, wherein, A maximum line scratch value Rmax of the surface of the silicon wafer is less than or equal to 17 microns.

4. The silicon wafer according to claim 1 or 2, wherein The stripes extend in an arc shape on the middle region, and a vertex of the stripe is located in the middle region of the surface along the first direction, and an end point of the stripe is located at the second side edge, wherein a distance between the vertex and the end point along the second direction is L2, and 1.5 millimeters 5. The silicon wafer of claim 4, wherein, A line connecting the vertex and the end point of the stripe is a first line, a line extending from the vertex of the stripe to the second side edge along the first direction is a second line, and an included angle between the first line and the second line is α, and 1°≤α≤8°.

6. The silicon wafer of claim 1, wherein, The surface has a damage layer, and a thickness of the damage layer is 3-5 microns.

7. The silicon wafer of claim 1, wherein The surface has a first region, a second region, and a third region arranged in sequence along the second direction; the middle region is at least partially located within the range of the second region; wherein a stripe density on the first region and the third region is greater than a stripe density on the second region. The stripe density refers to a number of stripes within a range of at least 5 mm along the second direction.

8. The silicon wafer of claim 7, wherein, A width of the first region along the second direction is a first width, a width of the second region along the second direction is a second width, and a width of the third region along the second direction is a third width; wherein The second width is greater than the first width and the third width.

9. The silicon wafer of claim 8, wherein, A total width of the silicon wafer along the second direction is the total width, a proportion of the first width in the total width is 25%-35%, a proportion of the second width in the total width is 54%-65%, and a proportion of the third width in the total width is 10%-20%.

10. The silicon wafer of claim 8, wherein, The first width is at least greater than 10 millimeters, and the third width is at least greater than 5 millimeters.

11. A battery sheet, characterized by The battery piece comprises the silicon wafer according to any one of claims 1-10.

12. A photovoltaic module, characterized by The photovoltaic module comprises the battery piece according to claim 11.

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