Display panel and display device

Abstract

The embodiment of the utility model provides a display panel and a display device. According to the display panel, a first inverting transistor and a second inverting transistor are connected in series between a first high-potential end and a first low-potential end, a grid electrode of the first inverting transistor is connected with the first high-potential end, and the first inverting transistor and the second inverting transistor are connected to a first pull-down node, and / or a second pull-down node is connected to a second low-potential end. The third inverting transistor and the fourth inverting transistor are connected in series between the first high-potential end and the first low-potential end, the grid electrode of the third inverting transistor is connected with the first high-potential end, and the third inverting transistor and the fourth inverting transistor are connected to the second pull-down node, and / or the grid electrode of the third inverting transistor is connected with the second low-potential end. The seventh inverting transistor is connected in series between the first high-potential end and the third pull-down node, and at least one of the fifth inverting transistor and the sixth inverting transistor is directly connected with the seventh inverting transistor, so that some transistors in the gate drive circuit can be reduced, the occupied space of the gate drive circuit is reduced, and the frame is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to display technical field especially is related to a display panel and display device. BACKGROUND

[0002] OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) display device has light, wide viewing angle, low power consumption, fast response speed, low temperature resistance, high luminous efficiency, and can be widely used in various fields. And in order to reduce the driving chip, reduce the frame, reduce the cost, will adopt the gate drive circuit to replace the gate drive chip to drive the pixel circuit. But in the actual use process, it is found that the frame of display device is still larger, this is because the different types of gate drive circuit need to be set to output different signals to the pixel circuit, resulting in that the occupation space of gate drive circuit is larger, and the number of transistors set for realizing the function of each gate drive circuit is more, which further increases the occupation space of gate drive circuit, resulting in that the frame of display device is larger.

[0003] Therefore, the existing display device has the technical problem that the space occupied by the gate drive circuit is larger, resulting in a larger frame. SUMMARY

[0004] The utility model embodiment provides a kind of display panel and display device, to solve the technical problem that the frame of the existing display device is larger due to the space occupied by the gate drive circuit being larger.

[0005] In order to achieve the above purpose, according to the first aspect of the utility model, a display panel is provided, which comprises:

[0006] a pixel drive circuit;

[0007] a gate drive circuit connected to the pixel drive circuit, the gate drive circuit comprising a first type of gate circuit, a second type of gate circuit and a third type of gate circuit, the first type of gate circuit comprising a first inverter, the second type of gate circuit comprising a second inverter, and the third type of gate circuit comprising a third inverter;

[0008] The first inverter comprises a first inverter transistor and a second inverter transistor, and the first inverter transistor and the second inverter transistor are connected in series between a first high potential end and a first low potential end, the gate of the first inverter transistor is connected to the first high potential end, and the first inverter transistor and the second inverter transistor are connected to a first pull-down node;

[0009] And / or, the second inverter comprises a third inverting transistor and a fourth inverting transistor, the third inverting transistor and the fourth inverting transistor are connected in series between the first high potential end and the first low potential end, the gate of the third inverting transistor is connected to the first high potential end, and the third inverting transistor and the fourth inverting transistor are connected to the second pull-down node;

[0010] And / or, the third inverter comprises a fifth inverting transistor, a sixth inverting transistor and a seventh inverting transistor, the seventh inverting transistor is connected in series between the first high potential end and the third pull-down node, and at least one of the fifth inverting transistor and the sixth inverting transistor is directly connected to the seventh inverting transistor.

[0011] According to the second aspect of the present application, a display device is provided, which comprises the display panel according to any one of the above embodiments.

[0012] The display panel and the display device are provided in the embodiments of the present application, the first inverting transistor and the second inverting transistor are connected in series between the first high potential end and the first low potential end, the gate of the first inverting transistor is connected to the first high potential end, and the first inverting transistor and the second inverting transistor are connected to the first pull-down node, and / or, the third inverting transistor and the fourth inverting transistor are connected in series between the first high potential end and the first low potential end, the gate of the third inverting transistor is connected to the first high potential end, and the third inverting transistor and the fourth inverting transistor are connected to the second pull-down node, and / or, the seventh inverting transistor is connected in series between the first high potential end and the third pull-down node, and at least one of the fifth inverting transistor and the sixth inverting transistor is directly connected to the seventh inverting transistor, so that some transistors in the gate drive circuit can be reduced, thereby reducing the occupied space of the gate drive circuit and reducing the frame.

[0013] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained according to these drawings without creative labor for those skilled in the art.

[0015] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0016] Figure 1A plane schematic view of the display panel is provided for the embodiment of the utility model.

[0017] Figure 2 A circuit diagram of a pixel driving circuit of the display panel is provided for the embodiment of the utility model.

[0018] Figure 3 A circuit diagram of a first type of gate circuit of the display panel is provided for the embodiment of the utility model.

[0019] Figure 4 A circuit diagram of a second type of gate circuit of the display panel is provided for the embodiment of the utility model.

[0020] Figure 5 A circuit diagram of a third type of gate circuit of the display panel is provided for the embodiment of the utility model.

[0021] Figure 6 A timing diagram of each signal line in a gate driving circuit of the display panel is provided for the embodiment of the utility model.

[0022] Figure 7 A timing diagram of each signal line in a pixel driving circuit of the display panel is provided for the embodiment of the utility model. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the utility model will be described clearly and completely below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.

[0024] The embodiments of the utility model provide a display panel and a display device, to solve the technical problem that the space occupied by the gate driving circuit of the existing display device is large, resulting in a large frame.

[0025] Figure 1 A plane schematic view of the display panel is provided for the embodiment of the utility model. Figure 2 A circuit diagram of a pixel driving circuit of the display panel is provided for the embodiment of the utility model. Figure 3 A circuit diagram of a first type of gate circuit of the display panel is provided for the embodiment of the utility model. Figure 4 A circuit diagram of a second type of gate circuit of the display panel is provided for the embodiment of the utility model. Figure 5 A circuit diagram of a third type of gate circuit of the display panel is provided for the embodiment of the utility model. Figure 6 A timing diagram of each signal line in a gate driving circuit of the display panel is provided for the embodiment of the utility model. Figure 7The timing diagram of each signal line in the pixel driving circuit of the display panel is provided for the embodiments of the utility model.

[0026] As Figures 1 to 7 shown, the utility model discloses a display panel, this display panel 1 includes pixel drive circuit 11 and gate drive circuit 12, and gate drive circuit 12 is connected with pixel drive circuit 11, and gate drive circuit 12 includes first type gate circuit 21, second type gate circuit 22 and third type gate circuit 23.

[0027] As Figures 1 to 7 shown, the utility model discloses a display panel, this display panel 1 includes pixel drive circuit 11 and gate drive circuit 12, and gate drive circuit 12 is connected with pixel drive circuit 11, and gate drive circuit 12 includes first type gate circuit 21, second type gate circuit 22 and third type gate circuit 23, and first type gate circuit 21 includes first inverter 216, and second type gate circuit 22 includes second inverter 226, and third type gate circuit 23 includes third inverter 235.

[0028] Among them, first inverter 216 includes first inverter transistor T51A and second inverter transistor T52A, and first inverter transistor T51A and second inverter transistor T52A are connected in series between first high potential end VGH1 and first low potential end VGL1, and the gate of first inverter transistor T51A is connected with first high potential end VGH1, and first inverter transistor T51A and second inverter transistor T52A are connected with first pull-down node QB1.

[0029] And / or, second inverter 226 includes third inverter transistor T51B and fourth inverter transistor T52B, and third inverter transistor T51B and fourth inverter transistor T52B are connected in series between first high potential end VGH1 and first low potential end VGL1, and the gate of third inverter transistor T51B is connected with first high potential end VGH1, and third inverter transistor T51B and fourth inverter transistor T52B are connected with second pull-down node QB2.

[0030] And / or, third inverter 235 includes fifth inverter transistor T52C, sixth inverter transistor T52D and seventh inverter transistor T54, and seventh inverter transistor T54 is connected in series between first high potential end VGH1 and third pull-down node QB, and at least one of fifth inverter transistor T52C and sixth inverter transistor T52D is directly connected with seventh inverter transistor T54.

[0031] The utility model embodiment provides a kind of display panel, which is connected in series between the first high potential terminal VGH1 and the first low potential terminal VGL1 by the first inverter transistor T51A and the second inverter transistor T52A, the gate of the first inverter transistor T51A is connected to the first high potential terminal VGH1, and the first inverter transistor T51A and the second inverter transistor T52A are connected to the first pull-down node QB1, and / or, the third inverter transistor T51B and the fourth inverter transistor T52B are connected in series between the first high potential terminal VGH1 and the first low potential terminal VGL1, the gate of the third inverter transistor T51B is connected to the first high potential terminal VGH1, and the third inverter transistor T51B and the fourth inverter transistor T52B are connected to the second pull-down node QB2, and / or, the seventh inverter transistor T54 is connected in series between the first high potential terminal VGH1 and the third pull-down node QB3, at least one of the fifth inverter transistor T52C and the sixth inverter transistor T52D is directly connected to the seventh inverter transistor T54, so that some transistors in the gate drive circuit 12 can be reduced, thereby reducing the occupied space of the gate drive circuit 12 and reducing the frame.

[0032] Specifically, as shown in Figure 1 The display panel 1 includes a display area 101 and a non-display area 102, and the non-display area 102 can be arranged around the display area 101, but the embodiments of the utility model are not limited thereto. The non-display area 102 can be arranged on one side, two sides, or three sides of the display area 101, and the non-display area 102 can be bent to the back of the display area 101. The pixel driving circuit 11 is arranged in the display area 101, and the non-display area 102 can include an upper frame area, a lower frame area, a left frame area, and a right frame area. The gate drive circuit 12 can be arranged in the left frame area and / or the right frame area, and the gate drive circuit 12 can be arranged on one side of the display area 101 or on both sides of the display area 101.

[0033] In some embodiments, the mobility of at least one transistor in the gate drive circuit 12 is greater than the mobility of the transistors in the pixel driving circuit 11, thereby reducing the number of transistors in the gate drive circuit and / or reducing the size of the transistors in the gate drive circuit, thereby reducing the occupied space of the gate drive circuit 12 and reducing the frame.

[0034] Specifically, the mobility of at least one transistor in the gate drive circuit 12 can be greater than the mobility of the transistor in the pixel drive circuit 11, for example, the mobility of the first inverter transistor T51A in the gate drive circuit 12 is greater than the mobility of the initialization transistor T4 in the pixel drive circuit 11, but the embodiment of the present application is not limited to this, the mobility of other transistors in the gate drive circuit can be greater than the mobility of the transistor in the pixel drive circuit, or the mobility of multiple transistors in the gate drive circuit is greater than the mobility of the transistor in the pixel drive circuit.

[0035] Specifically, the material of the active pattern of each transistor in the gate drive circuit can be the same, the material of the active pattern of each transistor in the pixel drive circuit is the same, and the mobility of the active pattern of the transistor in the gate drive circuit is greater than the mobility of the active pattern of the transistor in the pixel drive circuit.

[0036] Specifically, the mobility of the active pattern of the transistor in the gate drive circuit can be greater than 20, for example, the material of the active pattern of each transistor in the gate drive circuit is Ln-IZO (lanthanide doped indium zinc oxide), IGZTO (indium gallium zinc tin oxide), and the material of the active pattern of the transistor in the pixel drive circuit is indium gallium zinc oxide, so that the area of the transistor in the gate drive circuit can be relatively small.

[0037] Specifically, in order to improve the performance of the transistor, the area of the transistor is generally large, for example, when indium gallium zinc oxide is used as the material of the active pattern, the channel width of the transistor needs to be 1000 and the length needs to be 5 to meet the electrical requirements of the transistor. The embodiment of the present application can reduce the area of the transistor by making the mobility of the transistor in the gate drive circuit greater than the mobility of the transistor in the pixel drive circuit, still meeting the electrical requirements, and reducing the occupied area of the transistor.

[0038] Specifically, as shown in Figure 3 The first type of gate circuit 21 can not be provided with an anti-creeping module, so that the number of transistors in the first type of gate circuit 21 and the corresponding wiring can be reduced, the occupied space of the first type of gate circuit 21 can be reduced, and the frame can be reduced.

[0039] Specifically, as shown in Figure 3As shown, the first type of gate circuit 21 can include a first inverter 216, which includes a first inverting transistor T51A and a second inverting transistor T52A. The first inverting transistor T51A and the second inverting transistor T52A are connected in series between a first high potential terminal VGH1 and a first low potential terminal VGL1. The gate of the first inverting transistor T51A is connected to the first high potential terminal VGH1, and the first inverting transistor T51A and the second inverting transistor T52A are connected to a first pull-down node QB1. This can reduce the number of transistors in the first inverter and the corresponding wiring, thereby reducing the space occupied by the first type of gate circuit 21 and reducing the bezel size.

[0040] Specifically, such as Figure 3 As shown, the first type of gate circuit 21 can be made without a Darlington structure, thereby reducing the number of transistors and corresponding wiring in the first type of gate circuit 21, reducing the space occupied by the first type of gate circuit 21, and reducing the bezel.

[0041] Specifically, current display devices typically connect a first inverting transistor and a second inverting transistor, then add another inverting transistor. The gate of this second inverting transistor is connected to the connection node of the first and second inverting transistors, and the first electrode of the second inverting transistor is connected to the first electrode of the first inverting transistor. The second electrode of the second inverting transistor is connected to a first pull-down node, and a Darlington structure is incorporated. This Darlington structure contains two transistors: one transistor's gate is connected to a first pull-up node, and the other transistor's gate is connected to a stage terminal. The first electrodes of both transistors are connected to a first low-potential terminal, and the second electrodes of both transistors are connected to the first pull-down node. This results in a large number of transistors in the first inverter and the Darlington structure, occupying a significant amount of space. This embodiment of the invention reduces the number of transistors in the first inverter and removes the Darlington structure, thus reducing the space occupied by the first type of gate circuit. Furthermore, by connecting the first inverting transistor and the second inverting transistor to the first pull-down node, the functions of the first inverter and the Darlington structure can be realized, enabling the first type of gate circuit to operate normally.

[0042] Specifically, such as Figure 3 As shown, the first type of gate circuit 21 can be made to not have a transmission module, thereby reducing the transistors, traces and signal terminals provided for the output transmission module, reducing the number of transistors and corresponding traces in the first type of gate circuit 21, reducing the space occupied by the first type of gate circuit 21, and reducing the bezel.

[0043] Specifically, such as Figure 3As shown in the figure, the first type of gate circuit 21 can be provided with a first signal output end, thereby reducing the number of transistors in the first type of gate circuit 21 and the corresponding wiring, reducing the occupied space of the first type of gate circuit 21, and reducing the frame.

[0044] Specifically, as shown in the figure, Figure 3 As shown in the figure, the first type of gate circuit 21 includes a first pull-up node Q1, and at least one parallel branch between the first pull-up node Q1 and the first low potential end VGL1, a transistor is arranged between the first pull-up node Q1 and the first low potential end VGL1. By arranging a transistor between the first pull-up node Q1 and the first low potential end VGL1 on at least one parallel branch, the number of transistors on the parallel branch can be reduced, the number of transistors in the first type of gate circuit 21 and the corresponding wiring can be reduced, the occupied space of the first type of gate circuit 21 can be reduced, and the frame can be reduced.

[0045] Specifically, for example, as shown in the figure, Figure 3 As shown in the figure, it can be seen that a plurality of parallel branches are arranged between the first pull-up node Q1 and the first low potential end VGL1, for example, the first pull-down maintenance transistor T41A and the first reset transistor T45A are arranged on two branches between the first pull-up node Q1 and the first low potential end VGL1. It can be understood that the branch where the first pull-down maintenance transistor T41A is arranged and the branch where the first reset transistor T45A is arranged are two parallel branches between the first pull-up node Q1 and the first low potential end VGL1. Similarly, other parallel branches can be determined, which will not be described here.

[0046] Specifically, as shown in the figure, Figure 4 As shown in the figure, the second type of gate circuit 22 can not be provided with an anti-leakage module, thereby reducing the number of transistors in the second type of gate circuit 22 and the corresponding wiring, reducing the occupied space of the second type of gate circuit 22, and reducing the frame.

[0047] Specifically, as shown in the figure, Figure 4 As shown in the figure, the second type of gate circuit 22 can include a second inverter 226, the second inverter 226 includes a third inverting transistor T51B and a fourth inverting transistor T52B, the third inverting transistor T51B and the fourth inverting transistor T52B are connected in series between the first high potential end VGH1 and the first low potential end VGL1, the gate of the third inverting transistor T51B is connected to the first high potential end VGH1, and the third inverting transistor T51B and the fourth inverting transistor T52B are connected to the second pull-down node QB2. Then the number of transistors in the second inverter and the corresponding wiring can be reduced, thereby reducing the occupied space of the second type of gate circuit 22, and reducing the frame.

[0048] Specifically, as shown in Figure 4 It can be seen that the Darlington structure is not provided in the second type of gate circuit 22, so that the number of transistors in the second type of gate circuit 22 and the corresponding wiring can be reduced, the occupied space of the second type of gate circuit 22 can be reduced, and the frame can be reduced.

[0049] Specifically, in the current display device, the third inverter transistor and the fourth inverter transistor are connected, another inverter transistor is provided, the gate of the other inverter transistor is connected to the connection node of the third inverter transistor and the fourth inverter transistor, the first electrode of the other inverter transistor is connected to the first electrode of the third inverter transistor, and the second electrode of the other inverter transistor is connected to the second pull-down node, and a Darlington structure is provided, the Darlington structure is provided with two transistors, the gate of one transistor is connected to the second pull-up node, the gate of one transistor is connected to the stage transmission end, the first electrodes of the two transistors are connected to the first low potential end, and the second electrodes of the two transistors are connected to the second pull-down node; the number of transistors in the second inverter and the Darlington structure is large, and the occupied space is large. The number of transistors in the second inverter is reduced, the Darlington structure is removed, the occupied space of the second type of gate circuit is reduced, the third inverter transistor and the fourth inverter transistor are connected to the second pull-down node, the functions of the second inverter and the Darlington structure can be realized, and the second type of gate circuit can work normally.

[0050] Specifically, as shown in Figure 4 The second type of gate circuit 22 includes a second pull-up node Q2, and at least one parallel branch between the second pull-up node Q2 and the first low potential end VGL1, and one transistor is provided between the second pull-up node Q2 and the first low potential end VGL1. By providing one transistor between the second pull-up node Q2 and the first low potential end VGL1 on at least one parallel branch, the number of transistors on the parallel branch can be reduced, the number of transistors in the second type of gate circuit 22 and the corresponding wiring can be reduced, the occupied space of the second type of gate circuit 22 can be reduced, and the frame can be reduced.

[0051] Specifically, for example, as shown in Figure 4 It can be seen that the second pull-up node Q2 and the first low potential end VGL1 are provided with a plurality of parallel branches, for example, the second pull-down maintaining transistor T41B and the second reset transistor T45B are located on two branches between the second pull-up node Q2 and the first low potential end VGL1. It can be understood that the branch where the second pull-down maintaining transistor T41B is located and the branch where the second reset transistor T45B is located are two parallel branches between the second pull-up node Q2 and the first low potential end VGL1. Similarly, other parallel branches can be determined, which will not be described here.

[0052] Specifically, as shown in Figure 5 , the third type of gate circuit 23 can be made without setting an anti-leakage module, so that the number of transistors in the third type of gate circuit 23 and the corresponding wiring can be reduced, the occupied space of the third type of gate circuit 23 can be reduced, and the frame can be reduced.

[0053] Specifically, as shown in Figure 5 , the third type of gate circuit 23 can include a third inverter 235, the third inverter 235 includes a fifth inverter transistor T52C, a sixth inverter transistor T52D and a seventh inverter transistor T54, the seventh inverter transistor T54 is connected in series between the first high potential end VGH1 and the third pull-down node QB, and at least one of the fifth inverter transistor T52C and the sixth inverter transistor T52D is directly connected with the seventh inverter transistor T54, so that the number of transistors in the third inverter and the corresponding wiring can be reduced, thereby reducing the occupied space of the third type of gate circuit 23 and reducing the frame.

[0054] Specifically, as shown in Figure 5 , a transistor is arranged between the fifth inverter transistor T52C and the seventh inverter transistor T54, a transistor is arranged between the sixth inverter transistor T52D and the seventh inverter transistor T54, and a transistor is arranged between the second electrode of the fifth inverter transistor T52C and the second electrode of the sixth inverter transistor T52D and the first high potential end VGH1. The embodiment of the utility model can remove at least one of the above three transistors, thereby reducing the number of transistors in the third inverter and the corresponding wiring, thereby reducing the occupied space of the third type of gate circuit 23 and reducing the frame.

[0055] Specifically, as shown in Figure 5 , a transistor is arranged between the third pull-up node Q3 and the first low potential end VGL1, so that the number of transistors in the third inverter and the corresponding wiring can be reduced, thereby reducing the occupied space of the third type of gate circuit 23 and reducing the frame.

[0056] In some embodiments, as Figure 3As shown, the first type of gate circuit 21 includes a first pull-up node Q1. A transistor is disposed between the first pull-up node Q1 and the first low-potential terminal VGL1 in at least one parallel branch. By distributing a transistor between the first pull-up node Q1 and the first low-potential terminal VGL1 in at least one parallel branch, the number of transistors in the parallel branch between the first pull-up node Q1 and the first low-potential terminal VGL1 can be reduced, thus reducing the number of transistors and corresponding wiring in the first type of gate circuit 21. This reduces the space occupied by the first type of gate circuit 21 and the bezel of the display panel.

[0057] Specifically, compared to current display devices where multiple transistors are placed on the parallel branch between the first pull-up node and the first low-potential terminal, resulting in a large number of transistors and a large space occupied by transistors and wiring, this embodiment of the invention reduces the number of transistors and corresponding wiring in the first type of gate circuit 21 by placing a transistor between the first pull-up node Q1 and the first low-potential terminal VGL1 on at least one parallel branch between the first pull-up node Q1 and the first low-potential terminal VGL1. This reduces the space occupied by the first type of gate circuit 21 and the bezel of the display panel.

[0058] In some embodiments, such as Figure 3 As shown, the first type of gate circuit 21 includes a first pull-up control module 211, a first pull-up module 212, a first pull-down module 213, a first pull-down sustaining module 214, a first reset module 215, and a first inverter 216; the first pull-up module 212 and the first pull-up control module 211 are connected to the first pull-up node Q1; the first pull-down module 213 is connected to the first pull-up node Q1, the first pull-down node QB1, and the first signal output terminal Gn[n]; the first pull-down sustaining module 214 is connected between the first pull-up node Q1 and the first low potential terminal VGL1; the first reset module 215 is connected between the first pull-up node Q1 and the first low potential terminal VGL1; the first inverter 216 is connected to the first pull-up node Q1, the first low potential terminal VGL1, and the first high potential terminal VGH1.

[0059] At least one of the first pull-down module 213, the first pull-down sustaining module 214, and the first reset module 215 includes the parallel branch. By including the parallel branch in at least one of the first pull-down module, the first pull-down sustaining module, and the first reset module, the number of transistors in at least one of the first pull-down module, the first pull-down sustaining module, and the first reset module can be reduced, thereby reducing the number of transistors and the corresponding wiring in the first type of gate circuit 21, reducing the space occupied by the first type of gate circuit 21, and reducing the bezel of the display panel.

[0060] Specifically, such as Figure 3 As shown, a portion of the first pull-down module 213, the first pull-down sustaining module 214, and the first reset module 215 are connected in parallel between the first pull-up node Q1 and the first low-potential terminal VGL1.

[0061] In some embodiments, such as Figure 3 As shown, the first pull-up control module 211 includes a first pull-up control transistor T11A. The gate of the first pull-up control transistor T11A is connected to the first signal output terminal Gn[n-2] of the first two-stage first type gate circuit 21. The first electrode of the first pull-up control transistor T11A is connected to the first high potential terminal VGH1. The second electrode of the first pull-up control transistor T11A is connected to the first pull-up node Q1.

[0062] Specifically, such as Figure 3 As shown, the gate drive circuit 12 includes multiple stages of first-type gate circuits 21. In the first stage of the first-type gate circuit 21, the gate of the first pull-up control transistor T11A is connected to the start signal line STV, and the first electrode of the first pull-up control transistor T11A is connected to the start signal line STV. In the other stages of the first-type gate circuit 21, the gate of the first pull-up control transistor T11A is connected to the first signal output terminal Gn[n-2] of the previous two stages of the first-type gate circuit 21, and the first electrode of the first pull-up control transistor T11A is connected to the first high potential terminal VGH1.

[0063] In some embodiments, such as Figure 3 As shown, the first pull-up module 212 includes a first pull-up transistor T21A. The gate of the first pull-up transistor T21A is connected to the first pull-up node Q1. The first electrode of the first pull-up transistor T21A is connected to the first type of clock signal line CKC. The second electrode of the first pull-up transistor T21A is connected to the first signal output terminal Gn[n] of the first type of gate circuit 21 of this stage.

[0064] Specifically, the first type of clock signal line CKC may include a first clock line CKC1, a second clock line CKC2, a third clock line CKC3, and a fourth clock line CKC4. The first electrodes of the four first pull-up transistors T21A of each of the four stages of the first type of gate circuit 21 are respectively connected to the first clock line CKC1, the second clock line CKC2, the third clock line CKC3, and the fourth clock line CKC4. However, the embodiments of this utility model are not limited to this. The first type of clock signal line CKC may be provided with different numbers of clock signal lines depending on the design. For example, the first type of clock signal line CKC may include eight clock lines.

[0065] In some embodiments, such as Figure 3 As shown, the first pull-down module 213 includes a first pull-down transistor T31A, a second pull-down transistor T43A, and a third pull-down transistor T53A. The gate of the first pull-down transistor T31A is connected to the first pull-down node QB1, the first electrode of the first pull-down transistor T31A is connected to the first low-potential terminal VGL1, and the second electrode of the first pull-down transistor T31A is connected to the first signal output terminal Gn[n] of the first-stage gate circuit 21. The gate of the second pull-down transistor T43A is connected to the first pull-down node QB1, the first electrode of the second pull-down transistor T43A is connected to the first low-potential terminal VGL1, and the second electrode of the second pull-down transistor T43A is connected to the first pull-up node Q1. The gate of the third pull-down transistor T53A is connected to the first signal output terminal Gn[n-2] of the two-stage first-stage gate circuit 21, the first electrode of the third pull-down transistor T53A is connected to the first low-potential terminal VGL1, and the second electrode of the third pull-down transistor T53A is connected to the first pull-down node QB1. By connecting the first electrode of the second pull-down transistor T43A to the first low-potential terminal VGL1, the number of transistors in the first pull-down module can be reduced, thereby reducing the number of transistors and corresponding wiring in the first type of gate circuit 21, reducing the space occupied by the first type of gate circuit 21, and reducing the bezel of the display panel.

[0066] Specifically, the third pull-down transistor can be omitted to further reduce the number of transistors and corresponding wiring in the first type of gate circuit 21, reduce the space occupied by the first type of gate circuit 21, and reduce the bezel of the display panel.

[0067] In some embodiments, such as Figure 3As shown, the first pull-down maintaining module 214 includes a first pull-down maintaining transistor T41A, a gate of the first pull-down maintaining transistor T41A is connected with a first signal output end Gn[n+2] of the first gate electrode circuit 21 of the second stage, a first electrode of the first pull-down maintaining transistor T41A is connected with the first low potential end VGL1, and a second electrode of the first pull-down maintaining transistor T41A is connected with the first pull-up node Q1. By connecting the first electrode of the first pull-down maintaining transistor with the first low potential end VGL1 and connecting the second electrode of the first pull-down maintaining transistor T41A with the first pull-up node Q1, the number of transistors in the first pull-down maintaining module can be reduced, thereby reducing the number of transistors and the corresponding wirings in the first gate electrode circuit 21, reducing the occupied space of the first gate electrode circuit 21, and reducing the frame of the display panel.

[0068] In some embodiments, as shown in FIG. 4, the first pull-up module 213 includes a first pull-up transistor T43A, a gate of the first pull-up transistor T43A is connected with the first pull-up node Q1, a first electrode of the first pull-up transistor T43A is connected with the first high potential end VGH1, and a second electrode of the first pull-up transistor T43A is connected with the first low potential end VGL1. By connecting the first electrode of the first pull-up transistor T43A with the first high potential end VGH1 and connecting the second electrode of the first pull-up transistor T43A with the first low potential end VGL1, the number of transistors in the first pull-up module can be reduced, thereby reducing the number of transistors and the corresponding wirings in the first gate electrode circuit 21, reducing the occupied space of the first gate electrode circuit 21, and reducing the frame of the display panel. Figure 3 In some embodiments, as shown in FIG. 4, the first reset module 215 includes a first reset transistor T45A, a gate of the first reset transistor T45A is connected with a reset signal line VST, a first electrode of the first reset transistor T45A is connected with the first low potential end VGL1, and a second electrode of the first reset transistor T45A is connected with the first pull-up node Q1. By connecting the first electrode of the first reset transistor T45A with the first low potential end VGL1 and connecting the second electrode of the first reset transistor T45A with the first pull-up node Q1, the number of transistors in the first reset module can be reduced, thereby reducing the number of transistors and the corresponding wirings in the first gate electrode circuit 21, reducing the occupied space of the first gate electrode circuit 21, and reducing the frame of the display panel.

[0069] Figure 3 In some embodiments, as shown in FIG. 4, a gate of the first inverting transistor T51A and a first electrode of the first inverting transistor T51A are connected with the first high potential end VGH1, a second electrode of the first inverting transistor T51A is connected with the first pull-down node QB1; a gate of the second inverting transistor T52A is connected with the first pull-up node Q1, a first electrode of the second inverting transistor T52A is connected with the first low potential end VGL, and a second electrode of the second inverting transistor T52A is connected with the first pull-down node QB1, so that the inverting function can be realized by the first inverting transistor and the second inverting transistor, and the potentials of the first pull-up node Q1 and the first pull-down node QB1 are inverted.

[0070] Specifically, as shown in FIG. 4, the first inverting transistor T51A includes a first inverting transistor T51A1 and a second inverting transistor T51A2, a gate of the first inverting transistor T51A1 is connected with the first high potential end VGH1, a first electrode of the first inverting transistor T51A1 is connected with the first pull-down node QB1, and a second electrode of the first inverting transistor T51A1 is connected with the second electrode of the second inverting transistor T51A2; a gate of the second inverting transistor T51A2 is connected with the first pull-up node Q1, a first electrode of the second inverting transistor T51A2 is connected with the first low potential end VGL, and a second electrode of the second inverting transistor T51A2 is connected with the first pull-down node QB1. Figure 3 ​As shown, it can be seen that one inverting transistor is removed in the first inverter, thereby reducing the number of transistors in the first inverter, reducing the number of transistors in the first gate circuit 21 and the corresponding wiring, reducing the occupied space of the first gate circuit 21, and reducing the frame of the display panel.

[0071] In some embodiments, as shown in FIG. 1, the first gate circuit 21 further includes a first capacitor C1, one plate of the first capacitor C1 being connected to the first pull-up node Q1, and the other plate being connected to the first signal output end Gn[n] of the first gate circuit 21 at the current stage. Figure 3 As shown in FIG. 1, the first gate circuit 21 further includes a first capacitor C1, one plate of the first capacitor C1 being connected to the first pull-up node Q1, and the other plate being connected to the first signal output end Gn[n] of the first gate circuit 21 at the current stage.

[0072] In some embodiments, as shown in FIG. 1, the first gate circuit 21 further includes a first capacitor C1, one plate of the first capacitor C1 being connected to the first pull-up node Q1, and the other plate being connected to the first signal output end Gn[n] of the first gate circuit 21 at the current stage. Figure 3 As shown in FIG. 1, the first inverting transistor T51 includes a first sub-transistor T51A1 and a second sub-transistor T51A2, the gate of the first sub-transistor T51A1 and the gate of the second sub-transistor T51A2 being connected to the first high potential end VGH1, the first electrode of the first sub-transistor T51A1 being connected to the first high potential end VGH1, the second electrode of the first sub-transistor T51A1 being connected to the first electrode of the second sub-transistor T51A2, and the second electrode of the second sub-transistor T51A2 being connected to the first pull-down node QB1. By making the first inverting transistor include the first sub-transistor and the second sub-transistor, the electrical property of the first inverting transistor can be improved.

[0073] Specifically, it can be understood that the first sub-transistor and the second sub-transistor can be two sub-transistors formed by two parts of one transistor, for example, the first sub-transistor and the second sub-transistor can be provided with only one first electrode, one second electrode, one active pattern and two gates in the actual structure.

[0074] Specifically, the above embodiments are described by taking the first inverting transistor including the first sub-transistor and the second sub-transistor as an example, but the embodiments of the present application are not limited thereto, and the first inverting transistor can include only one sub-transistor.

[0075] In some embodiments, as shown in FIG. 1, the first gate circuit 21 further includes a first capacitor C1, one plate of the first capacitor C1 being connected to the first pull-up node Q1, and the other plate being connected to the first signal output end Gn[n] of the first gate circuit 21 at the current stage. Figure 4As shown, the second type of gate circuit 22 includes a second pull-up node Q2, and a transistor is arranged between the second pull-up node Q2 and the first low potential end VGL1 on at least one parallel branch between the second pull-up node Q2 and the first low potential end VGL1. By arranging the transistor between the second pull-up node Q2 and the first low potential end VGL1 on at least one parallel branch between the second pull-up node Q2 and the first low potential end VGL1, the number of transistors on the parallel branch between the second pull-up node Q2 and the first low potential end VGL1 can be reduced, the number of transistors in the second type of gate circuit 22 and the corresponding wiring can be reduced, the occupied space of the second type of gate circuit 22 can be reduced, and the frame of the display panel can be reduced.

[0076] Specifically, compared with the current display device, a plurality of transistors are arranged on the parallel branch between the second pull-up node and the first low potential end, resulting in a large number of transistors and a large occupied space of the transistors and the wiring. The embodiment of the utility model reduces the number of transistors in the second type of gate circuit 22 and the corresponding wiring by arranging the transistor between the second pull-up node Q2 and the first low potential end VGL1 on at least one parallel branch between the second pull-up node Q2 and the first low potential end VGL1, thereby reducing the occupied space of the second type of gate circuit 22 and reducing the frame of the display panel.

[0077] In some embodiments, as Figure 4 As shown, the second type of gate circuit 22 includes a second pull-up control module 221, a second pull-up module 222, a second pull-down module 223, a second pull-down maintenance module 224, a second reset module 225, and a second inverter 226. The second pull-up module 222 and the second pull-up control module 221 are connected to the second pull-up node Q2. The second pull-down module 223 is connected to the second pull-up node Q2, the second pull-down node QB2, and the second signal output end INI[n]. The second pull-down maintenance module 224 is connected between the second pull-up node Q2 and the first low potential end VGL1. The second reset module 225 is connected between the second pull-up node Q2 and the first low potential end VGL1. The second inverter 226 is connected to the second pull-up node Q2, the first low potential end VGL1, and the first high potential end VGH1.

[0078] At least one of the second pull-down module 223, the second pull-down sustaining module 224, and the second reset module 225 includes the parallel branch. By including a parallel branch in at least one of the second pull-down module, the second pull-down sustaining module, and the second reset module, the number of transistors in at least one of the second pull-down module, the second pull-down sustaining module, and the second reset module can be reduced, thereby reducing the number of transistors and the corresponding wiring in the second type of gate circuit 22, reducing the space occupied by the second type of gate circuit 22, and reducing the bezel of the display panel.

[0079] Specifically, such as Figure 4 As shown, a portion of the second pull-down module 223, the second pull-down sustaining module 224, and the second reset module 225 are connected in parallel between the second pull-up node Q2 and the first low-potential terminal VGL1.

[0080] In some embodiments, such as Figure 4 As shown, the second pull-up control module 221 includes a second pull-up control transistor T11B. The gate of the second pull-up control transistor T11B is connected to the second signal output terminal INI[n-2] of the two-stage second type gate circuit 22 above. The first electrode of the second pull-up control transistor T11B is connected to the first high potential terminal VGH1. The second electrode of the second pull-up control transistor T11B is connected to the second pull-up node Q2.

[0081] Specifically, such as Figure 4 As shown, the gate drive circuit 12 includes multiple stages of second-type gate circuits 22. In the first stage of the second-type gate circuit 22, the gate of the second pull-up control transistor T11B is connected to the start signal line STV, and the first electrode of the second pull-up control transistor T11B is connected to the start signal line STV. In the other stages of the second-type gate circuit 22, the gate of the second pull-up control transistor T11B is connected to the first signal output terminal INI[n-2] of the two stages of the second-type gate circuit 22 above, and the first electrode of the second pull-up control transistor T11B is connected to the first high potential terminal VGH1.

[0082] In some embodiments, such as Figure 4 As shown, the second pull-up module 222 includes a second pull-up transistor T21B. The gate of the second pull-up transistor T21B is connected to the second pull-up node Q2. The first electrode of the second pull-up transistor T21B is connected to the second type clock signal line CKB. The second electrode of the second pull-up transistor T21B is connected to the second signal output terminal INI[n] of the second type gate circuit 22 of this stage.

[0083] Specifically, the second type of clock signal line CKB may include a fifth clock line CKB1, a sixth clock line CKB2, a seventh clock line CKB3, and an eighth clock line CKB4. The first electrodes of the four second pull-up transistors T21B of each of the four stages of the second type of gate circuit 22 are respectively connected to the fifth clock line CKB1, the sixth clock line CKB2, the seventh clock line CKB3, and the eighth clock line CKB4. However, the embodiments of this utility model are not limited to this. The second type of clock signal line CKB may be provided with different numbers of clock signal lines depending on the design. For example, the second type of clock signal line CKB may include eight clock lines.

[0084] In some embodiments, such as Figure 4 As shown, the second pull-down module 223 includes a fourth pull-down transistor T31B, a fifth pull-down transistor T43B, and a sixth pull-down transistor T53B. The gate of the fourth pull-down transistor T31B is connected to the second pull-down node QB2. The first electrode of the fourth pull-down transistor T31B is connected to the first low-potential terminal VGL1. The second electrode of the fourth pull-down transistor T31B is connected to the second signal output terminal INI[n] of the second type of gate circuit 22 in this stage. The gate of the fifth pull-down transistor T43B is connected to the second pull-down node QB2. Point QB2 is connected. The first electrode of the fifth pull-down transistor T43B is connected to the first low-potential terminal VGL1, and the second electrode of the fifth pull-down transistor T43B is connected to the second pull-up node Q2. The gate of the sixth pull-down transistor T53B is connected to the second signal output terminal INI[n-2] of the two-stage second type gate circuit 22. The first electrode of the sixth pull-down transistor T53B is connected to the first low-potential terminal VGL1, and the second electrode of the sixth pull-down transistor T53B is connected to the second pull-up node QB2. By connecting the first electrode of the fifth pull-down transistor T43B to the first low-potential terminal VGL1 and the second electrode of the fifth pull-down transistor T43B to the second pull-up node Q2, the number of transistors in the second pull-down module can be reduced, thereby reducing the number of transistors and corresponding wiring in the second type gate circuit 22, reducing the space occupied by the second type gate circuit 22, and reducing the bezel of the display panel.

[0085] Specifically, the sixth pull-down transistor can be omitted to further reduce the number of transistors and corresponding wiring in the second type of gate circuit 22, reduce the space occupied by the second type of gate circuit 22, and reduce the bezel of the display panel.

[0086] In some embodiments, such as Figure 4As shown, the second pull-down maintaining module 224 includes a second pull-down maintaining transistor T41B, a gate of the second pull-down maintaining transistor T41B is connected with a second signal output end INI[n+2] of the second gate electrode circuit 22, a first electrode of the second pull-down maintaining transistor T41B is connected with the first low potential end VGL1, and a second electrode of the second pull-down maintaining transistor T41B is connected with the second pull-up node Q2. By connecting the first electrode of the second pull-down maintaining transistor with the first low potential end VGL1 and connecting the second electrode of the second pull-down maintaining transistor T41B with the second pull-up node Q2, the number of transistors in the second pull-down maintaining module can be reduced, thereby reducing the number of transistors in the second gate electrode circuit 22 and the corresponding wirings, reducing the occupied space of the second gate electrode circuit 22, and reducing the frame of the display panel.

[0087] In some embodiments, as shown in FIG. 4, the second pull-down maintaining module 224 includes a second pull-down maintaining transistor T41B, a gate of the second pull-down maintaining transistor T41B is connected with a second signal output end INI[n+2] of the second gate electrode circuit 22, a first electrode of the second pull-down maintaining transistor T41B is connected with the first low potential end VGL1, and a second electrode of the second pull-down maintaining transistor T41B is connected with the second pull-up node Q2. By connecting the first electrode of the second pull-down maintaining transistor with the first low potential end VGL1 and connecting the second electrode of the second pull-down maintaining transistor T41B with the second pull-up node Q2, the number of transistors in the second pull-down maintaining module can be reduced, thereby reducing the number of transistors in the second gate electrode circuit 22 and the corresponding wirings, reducing the occupied space of the second gate electrode circuit 22, and reducing the frame of the display panel. Figure 4 In some embodiments, as shown in FIG. 4, the second pull-down maintaining module 224 includes a second pull-down maintaining transistor T41B, a gate of the second pull-down maintaining transistor T41B is connected with a second signal output end INI[n+2] of the second gate electrode circuit 22, a first electrode of the second pull-down maintaining transistor T41B is connected with the first low potential end VGL1, and a second electrode of the second pull-down maintaining transistor T41B is connected with the second pull-up node Q2. By connecting the first electrode of the second pull-down maintaining transistor with the first low potential end VGL1 and connecting the second electrode of the second pull-down maintaining transistor T41B with the second pull-up node Q2, the number of transistors in the second pull-down maintaining module can be reduced, thereby reducing the number of transistors in the second gate electrode circuit 22 and the corresponding wirings, reducing the occupied space of the second gate electrode circuit 22, and reducing the frame of the display panel.

[0088] Figure 4 In some embodiments, as shown in FIG. 4, the second pull-down maintaining module 224 includes a second pull-down maintaining transistor T41B, a gate of the second pull-down maintaining transistor T41B is connected with a second signal output end INI[n+2] of the second gate electrode circuit 22, a first electrode of the second pull-down maintaining transistor T41B is connected with the first low potential end VGL1, and a second electrode of the second pull-down maintaining transistor T41B is connected with the second pull-up node Q2. By connecting the first electrode of the second pull-down maintaining transistor with the first low potential end VGL1 and connecting the second electrode of the second pull-down maintaining transistor T41B with the second pull-up node Q2, the number of transistors in the second pull-down maintaining module can be reduced, thereby reducing the number of transistors in the second gate electrode circuit 22 and the corresponding wirings, reducing the occupied space of the second gate electrode circuit 22, and reducing the frame of the display panel.

[0089] In some embodiments, as shown in FIG. 4, the second pull-down maintaining module 224 includes a second pull-down maintaining transistor T41B, a gate of the second pull-down maintaining transistor T41B is connected with a second signal output end INI[n+2] of the second gate electrode circuit 22, a first electrode of the second pull-down maintaining transistor T41B is connected with the first low potential end VGL1, and a second electrode of the second pull-down maintaining transistor T41B is connected with the second pull-up node Q2. By connecting the first electrode of the second pull-down maintaining transistor with the first low potential end VGL1 and connecting the second electrode of the second pull-down maintaining transistor T41B with the second pull-up node Q2, the number of transistors in the second pull-down maintaining module can be reduced, thereby reducing the number of transistors in the second gate electrode circuit 22 and the corresponding wirings, reducing the occupied space of the second gate electrode circuit 22, and reducing the frame of the display panel. Figure 4 ​As shown, it can be seen that one inverting transistor is removed in the second inverter, thereby reducing the number of transistors in the second inverter, reducing the number of transistors in the second gate circuit 22 and the corresponding wiring, reducing the occupied space of the second gate circuit 22, and reducing the frame of the display panel.

[0090] In some embodiments, as shown in FIG. 2, the second gate circuit 22 further includes a second capacitor C2, one plate of the second capacitor C2 is connected to the second pull-up node Q2, and the other plate is connected to the second signal output end INI[n] of the second gate circuit 22 at the current stage. Figure 4

[0091] In some embodiments, as shown in FIG. 2, the second gate circuit 22 further includes a second capacitor C2, one plate of the second capacitor C2 is connected to the second pull-up node Q2, and the other plate is connected to the second signal output end INI[n] of the second gate circuit 22 at the current stage. Figure 5

[0092] Specifically, it can be understood that the third transistor and the fourth transistor can be two sub-transistors formed by two parts of one transistor, for example, the third transistor and the fourth transistor can be provided with only one first electrode, one second electrode, one active pattern and two gates in the actual structure.

[0093] Specifically, the above embodiment takes the second inverting transistor including the third sub-transistor and the fourth sub-transistor as an example for description, but the embodiment of the present application is not limited thereto, and the second inverting transistor can include only one sub-transistor.

[0094] In some embodiments, as shown in FIG. 2, the display panel 1 further includes a first low potential end VGL1, and the third gate circuit 23 includes a third pull-up node Q3. Figure 5

[0095] ​​​At least one parallel branch between the third pull-up node Q3 and the first low potential end VGL1 is provided with a transistor. By providing at least one parallel branch between the third pull-up node Q3 and the first low potential end VGL1 with a transistor, the number of transistors in the parallel branch between the third pull-up node Q3 and the first low potential VGL1 is reduced, the number of transistors in the third gate circuit 23 is reduced, and the corresponding wiring is reduced, thereby reducing the occupied space of the third gate circuit 23 and reducing the frame of the display panel.

[0096] Specifically, compared with the current display device, a plurality of transistors are provided in the parallel branch between the third pull-up node and the first low potential end, resulting in a large number of transistors and a large occupied space of the transistors and the wiring. The embodiment of the utility model reduces the number of transistors in the third gate circuit 23 and the corresponding wiring by providing at least one parallel branch between the third pull-up node Q3 and the first low potential end VGL1 with a transistor, thereby reducing the occupied space of the third gate circuit 23 and reducing the frame of the display panel.

[0097] In some embodiments, as shown in Figure 5 The third gate circuit 23 includes a third pull-up control module 231, a third pull-up module 232, a pull-down control module 233, a third pull-down module 234, and a third inverter 235. The third pull-up module 232 and the third pull-up control module 231 are connected to the third pull-up node Q3. The pull-down control module 233 and the third pull-up module 232 are connected to the third pull-up node Q3. The third pull-down module 234 is connected to the third pull-up node Q3 and the third signal output end. The third inverter 235 is connected to the third pull-up node Q3, the first low potential end VGL1, and the first high potential end VGH1.

[0098] At least one of the third pull-down module 234 and the pull-down control module 233 includes the parallel branch. By providing at least one of the third pull-down module and the pull-down control module with the parallel branch, the number of transistors in at least one of the third pull-down module and the pull-down control module is reduced, thereby reducing the number of transistors in the third gate circuit 23 and the corresponding wiring, reducing the occupied space of the third gate circuit 23, and reducing the frame of the display panel.

[0099] Specifically, as shown in Figure 5As shown, a portion of the third pull-down module 234 and the pull-down control module 233 are connected in parallel between the third pull-up node Q3 and the first low-potential terminal VGL1.

[0100] In some embodiments, such as Figure 5 As shown, the third pull-up control module 231 includes a third pull-up control transistor T11C. The gate of the third pull-up control transistor T11C is connected to the second signal output terminal INI[n+1] of the next stage second type gate circuit 22. The first electrode of the third pull-up control transistor T11C is connected to the first high potential terminal VGH1. The second electrode of the third pull-up control transistor T11C is connected to the third pull-up node Q3.

[0101] In some embodiments, such as Figure 5 As shown, the third pull-up module 232 includes a third pull-up transistor T21C. The gate of the third pull-up transistor T21C is connected to the third pull-up node Q3. The first electrode of the third pull-up transistor T21C is connected to the second high-potential terminal VGH2. The second electrode of the third pull-up transistor T21C is connected to the third signal output terminal REF[n] of the third type gate circuit 23 of this stage.

[0102] In some embodiments, such as Figure 5 As shown, the pull-down control module 233 includes a pull-down control transistor T42. The gate of the pull-down control transistor T42 is connected to the first signal output terminal Gn[n-1] of the previous stage first type gate circuit 21. The first electrode of the pull-down control transistor T42 is connected to the first low potential terminal VGL1, and the second electrode of the pull-down control transistor T42 is connected to the third pull-up node Q3. By connecting the first electrode of the pull-down control transistor T42 to the first low potential terminal VGL1 and the second electrode of the pull-down control transistor T42 to the third pull-up node, the number of transistors in the pull-down control module can be reduced, thereby reducing the number of transistors and corresponding wiring in the third type gate circuit 23, reducing the space occupied by the third type gate circuit 23, and reducing the bezel of the display panel.

[0103] In some embodiments, such as Figure 5As shown, the third pull-down module 234 includes a seventh pull-down transistor T31C and an eighth pull-down transistor T43C. A gate of the seventh pull-down transistor T31C is connected with the third pull-down node QB3, a first electrode of the seventh pull-down transistor T31C is connected with the second low potential end VGL2, and a second electrode of the seventh pull-down transistor T31C is connected with the third signal output end REF[n] of the third gate electrode circuit 23 of the current stage. A gate of the eighth pull-down transistor T43C is connected with the third pull-down node QB3, a first electrode of the eighth pull-down transistor T43C is connected with the first low potential end VGL1, and a second electrode of the eighth pull-down transistor T43C is connected with the third pull-up node Q3. By connecting the first electrode of the eighth pull-down transistor T43C with the first low potential end VGL1 and connecting the second electrode of the eighth pull-down transistor T43C with the third pull-up node Q3, the number of transistors in the third pull-down module can be reduced, thereby reducing the number of transistors in the third gate electrode circuit 23 and the corresponding wirings, reducing the occupied space of the third gate electrode circuit 23, and reducing the frame of the display panel.

[0104] In some embodiments, as Figure 5As shown, the third inverter 235 further includes an eighth inverting transistor T55 and a ninth inverting transistor T56, the gate of the fifth inverting transistor T52C and the first electrode of the fifth inverting transistor T52C are connected with the first signal output end Gn[n-1] of the first type of gate circuit 21 of the previous stage, the second electrode of the fifth inverting transistor T52C is connected with the gate of the seventh inverting transistor T54 at the inverting node P, the gate of the sixth inverting transistor T52D is connected with the second signal output end INI[n] of the second type of gate circuit 22 of the current stage, the first electrode of the sixth inverting transistor T52D is connected with the first low potential end VGL1, the second electrode of the sixth inverting transistor T52D is connected with the gate of the seventh inverting transistor T54 at the inverting node P, the first electrode of the seventh inverting transistor T54 is connected with the first high potential end VGH1, the second electrode of the seventh inverting transistor T54 is connected with the second electrode of the eighth inverting transistor T55 at the third pull-down node QB3, the gate of the eighth inverting transistor T55 is connected with the third pull-up node Q3, the first electrode of the eighth inverting transistor T55 is connected with the first low potential end VGL1, the gate of the ninth inverting transistor T56 is connected with the second signal output end INI[n+1] of the second type of gate circuit 22 of the next stage, the first electrode of the ninth inverting transistor T56 is connected with the first low potential end VGL1, and the second electrode of the ninth inverting transistor T56 is connected with the second electrode of the seventh inverting transistor T54 at the third pull-down node QB3; thereby the inverting function can be realized by the fifth inverting transistor, the sixth inverting transistor, the seventh inverting transistor, the eighth inverting transistor and the ninth inverting transistor, and the potentials of the third pull-up node Q3 and the third pull-down node QB3 are inverted.

[0105] Specifically, as shown in FIG. 6, it can be seen that one inverting transistor is removed in the third inverter, thereby reducing the number of transistors in the third inverter, reducing the number of transistors in the third type of gate circuit 23 and the corresponding wiring, reducing the occupied space of the third type of gate circuit 23, and reducing the frame of the display panel. Figure 5 In some embodiments, as shown in FIG. 7, the third type of gate circuit 23 further includes a third capacitor C3 and a fourth capacitor C4, one plate of the third capacitor C3 is connected with the third pull-up node Q3, and the other plate is connected with the third signal output end REF[n] of the third type of gate circuit 23 of the current stage, one plate of the fourth capacitor C4 is connected with the inverting node P, and the other plate is connected with the first high potential end VGH1.

[0106] Figure 2

[0107] ​​Specifically, the signal of the first high potential end VGH1 and the signal of the second high potential end VGH2 can be the same or different.

[0108] Specifically, the signal of the first low potential end VGL1 and the signal of the second low potential end VGL2 can be the same or different.

[0109] In some embodiments, the area of at least one transistor in the gate driving circuit 12 is smaller than the area of the transistor in the pixel driving circuit 11, so that the occupied space of the gate driving circuit can be reduced, and the frame of the display panel can be reduced.

[0110] In some embodiments, as shown in Figure 2 The pixel driving circuit 11 includes a driving transistor T1, a switching transistor T2, a reset transistor T3 and an initialization transistor T4, the driving transistor T1, the switching transistor T2 and the reset transistor T3 are connected to the first node g, and the driving transistor T1 and the initialization transistor T4 are connected to the second node s.

[0111] The gate of the switching transistor T2 is connected to the first signal output end Gn[n] of the first type of gate circuit 21 of the current stage, the gate of the initialization transistor T4 is connected to the second signal output end INI[n] of the second type of gate circuit 22 of the current stage, and the gate of the reset transistor T3 is connected to the third signal output end REF[n] of the third type of gate circuit 23 of the current stage. By connecting the gate of the switching transistor, the gate of the initialization transistor and the gate of the reset transistor to the first signal output end Gn[n] of the first type of gate circuit 21 of the current stage, the second signal output end INI[n] of the second type of gate circuit 22 of the current stage and the third signal output end REF[n] of the third type of gate circuit 23 of the current stage respectively, the gate driving circuit can input signals to the pixel driving circuit, so that the pixel driving circuit can work normally.

[0112] Specifically, as shown in Figure 6 The display panel 1 further includes a light emitting device LED, the gate of the driving transistor T1 is connected to the first node g, the first electrode of the driving transistor T1 is connected to the high potential power line VDD, the second electrode of the driving transistor T1 is connected to the second node s, the first electrode of the switching transistor T2 is connected to the data line Vdata, the second electrode of the switching transistor T2 is connected to the first node g, the first electrode of the reset transistor T3 is connected to the reference line Vref, the second electrode of the reset transistor T3 is connected to the first node g, the first electrode of the initialization transistor T4 is connected to the initialization signal line Vini, the second electrode of the initialization transistor T4 is connected to the positive electrode of the light emitting device LED, and the negative electrode of the light emitting device LED is connected to the low potential power line VSS.

[0113] Specifically, it can be understood that the display panel includes multiple rows of sub-pixel units, and correspondingly, multiple-stage pixel driving circuits are arranged to drive each sub-pixel unit, and correspondingly, multiple-stage gate driving circuits are arranged, and each stage of the gate driving circuit can be connected with the corresponding pixel driving circuit.

[0114] Specifically, as shown in Figure 6 , a timing of the gate driving circuit 12 is provided to illustrate the working process of the gate driving circuit 12, from Figure 6 , it can be seen that in a frame time t0, it is divided into an output time period t1 and a blank time period t2, in the output time period t1, the reset signal line VST is first input to an effective level, which can reset the first pull-up node Q1 of the first type of gate circuit 21 and the second pull-up node Q2 of the second type of gate circuit 22, and then the start signal line STV and the first high potential end VGH1 are input to an effective level, so that the first stage of the first type of gate circuit 21 and the first stage of the second type of gate circuit 22 start to work, and then the first clock line CKC1, the second clock line CKC2, the third clock line CKC3 and the fourth clock line CKC4 are sequentially input to an effective level, and the effective level input time of each other has an intersection, and the fifth clock line CKB1, the sixth clock line CKB2, the seventh clock line CKB3 and the eighth clock line CKB4 are sequentially input to an effective level, so that each stage of the first type of gate circuit 21 and each stage of the second type of gate circuit 22 start to work, and at the same time, the third type of gate circuit 23 also starts to work, and outputs signals to the gate of the switching transistor, the gate of the initialization transistor and the gate of the reset transistor respectively.

[0115] Specifically, it can be understood that, for example, the timing of Figure 7 , the clock line connected with the second pull-up transistor T21B in the second type of gate circuit 22 and the clock line connected with the first pull-up transistor T21A in the first type of gate circuit 21 are staggered, for example, the second pull-up transistor T21B in each stage of the second type of gate circuit 22 is sequentially connected with the fifth clock line CKB1, the sixth clock line CKB2, the seventh clock line CKB3 and the eighth clock line CKB4, and the first pull-up transistor T21A in each stage of the first type of gate circuit 21 corresponding to each stage of the second type of gate circuit 22 is sequentially connected with the second clock line CKC2, the third clock line CKC3, the fourth clock line CKC4 and the first clock line CKC1.

[0116] Specifically, as shown in ​As shown, the output timing of the gate drive circuit 12, i.e. the input timing of the pixel drive circuit 11, is provided to illustrate the working process of the pixel drive circuit 11, it can be seen that the second signal output end INI[n] of the second type of gate circuit 22 of the current stage will first input a valid level to initialize the anode of the light emitting device LED, then the third signal output end REF[n] of the third type of gate circuit 23 of the current stage will input a valid level to output a reference level to the gate of the drive transistor, then the data line Vdata inputs a valid level and makes the first signal output end Gn[n] of the first type of gate circuit 21 of the current stage input a valid level to charge the light emitting device LED.

[0117] Specifically, the type of each transistor in the embodiments of the present application can be an N-type transistor.

[0118] Specifically, the valid level refers to an electrical signal capable of turning on a transistor, and the invalid level refers to an electrical signal capable of turning off a transistor. When a high potential signal is input to the gate of a transistor, the transistor is turned on, and thus the valid level refers to the high potential signal. When a low potential signal is input to the gate of a transistor, the transistor is turned on, and thus the valid level refers to the low potential signal. The embodiments of the present application are described by taking the case that the transistor is turned on when a high potential signal is input to the gate of the transistor as an example. It can be understood that the type of the transistor can be changed so that the transistor is turned on when a low potential signal is input to the gate of the transistor.

[0119] Specifically, the display panel is described in detail from the aspects of the circuit, timing, and transistor design of the display panel in the above embodiments. It can be understood that the embodiments can be combined when there is no conflict among the embodiments. For example, the display panel 1 includes the pixel drive circuit 11 and the gate drive circuit 12, the gate drive circuit 12 is connected with the pixel drive circuit 11, the gate drive circuit 12 includes the first type of gate circuit 21, the second type of gate circuit 22, and the third type of gate circuit 23, and the first type of gate circuit 21 does not include the anti-leakage module. Alternatively, the display panel 1 includes the pixel drive circuit 11 and the gate drive circuit 12, the gate drive circuit 12 is connected with the pixel drive circuit 11, the gate drive circuit 12 includes the first type of gate circuit 21, the second type of gate circuit 22, and the third type of gate circuit 23, and the mobility of at least one transistor in the gate drive circuit 12 is greater than the mobility of the transistor in the pixel drive circuit 11.

[0120] Meanwhile, the embodiments of the present application provide a display device, which includes the display panel according to any one of the above embodiments.

[0121] In the description of the utility model, the terms "first", "second" are only used for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more features. In the description of the utility model, the meaning of "multiple" is two or more than two, unless otherwise specifically limited.

[0122] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0123] The embodiments, implementation manners and related technical features of the utility model can be combined, replaced without conflict.

[0124] The above is only the preferred embodiment of the utility model, and does not limit the utility model in any form, but any simple modification, equivalent change and modification of the above embodiment according to the technical essence of the utility model still belongs to the scope of the technical scheme of the utility model.

Claims

1. A display panel, characterized by, The pixel driving circuit comprises: a pixel driving circuit; a gate driving circuit connected with the pixel driving circuit, the gate driving circuit comprising a first type of gate circuit, a second type of gate circuit and a third type of gate circuit, the first type of gate circuit comprising a first inverter, the second type of gate circuit comprising a second inverter, and the third type of gate circuit comprising a third inverter; wherein the first inverter comprises a first inverting transistor and a second inverting transistor, the first inverting transistor and the second inverting transistor being connected in series between a first high potential end and a first low potential end, the gate of the first inverting transistor being connected to the first high potential end, and the first inverting transistor and the second inverting transistor being connected to a first pull-down node; and / or the second inverter comprises a third inverting transistor and a fourth inverting transistor, the third inverting transistor and the fourth inverting transistor being connected in series between the first high potential end and the first low potential end, the gate of the third inverting transistor being connected to the first high potential end, and the third inverting transistor and the fourth inverting transistor being connected to a second pull-down node; and / or the third inverter comprises a fifth inverting transistor, a sixth inverting transistor and a seventh inverting transistor, the seventh inverting transistor being connected in series between the first high potential end and a third pull-down node, at least one of the fifth inverting transistor and the sixth inverting transistor being directly connected to the seventh inverting transistor.

2. The display panel of claim 1, wherein, The first type of gate circuit comprises a first pull-up node, and a transistor is arranged between the first pull-up node and the first low potential end in at least one parallel branch between the first pull-up node and the first low potential end.

3. The display panel of claim 2, wherein, The first type of gate circuit comprises: a first pull-up control module; a first pull-up module connected with the first pull-up control module at the first pull-up node; a first pull-down module connected with the first pull-up node, the first pull-down node and a first signal output end; a first pull-down maintaining module connected between the first pull-up node and the first low potential end; a first reset module connected between the first pull-up node and the first low potential end; a first inverter connected with the first pull-up node, the first low potential end and a first high potential end; wherein at least one of the first pull-down module, the first pull-down maintaining module and the first reset module comprises the parallel branch.

4. The display panel of claim 3, wherein, The first pull-up control module comprises a first pull-up control transistor, the gate of the first pull-up control transistor being connected to the first signal output end of the first type of gate circuit in the upper two stages, the first electrode of the first pull-up control transistor being connected to the first high potential end, and the second electrode of the first pull-up control transistor being connected to the first pull-up node; the first pull-up module comprises a first pull-up transistor, the gate of the first pull-up transistor being connected to the first pull-up node, the first electrode of the first pull-up transistor being connected to a first type of clock signal line, and the second electrode of the first pull-up transistor being connected to the first signal output end of the first type of gate circuit in the current stage; The first pull-down module comprises a first pull-down transistor, a second pull-down transistor and a third pull-down transistor, a gate of the first pull-down transistor is connected with a first pull-down node, a first electrode of the first pull-down transistor is connected with the first low potential end, a second electrode of the first pull-down transistor is connected with a first signal output end of the first gate circuit of the current stage, a gate of the second pull-down transistor is connected with the first pull-down node, a first electrode of the second pull-down transistor is connected with the first low potential end, a second electrode of the second pull-down transistor is connected with the first pull-up node, a gate of the third pull-down transistor is connected with a first signal output end of the first gate circuit of the previous two stages, a first electrode of the third pull-down transistor is connected with the first low potential end, and a second electrode of the third pull-down transistor is connected with the first pull-down node. The first pull-down maintaining module comprises a first pull-down maintaining transistor, a gate of the first pull-down maintaining transistor is connected with a first signal output end of the first gate circuit of the previous stage, a first electrode of the first pull-down maintaining transistor is connected with the first low potential end, and a second electrode of the first pull-down maintaining transistor is connected with the first pull-up node. The first reset module comprises a first reset transistor, a gate of the first reset transistor is connected with a reset signal line, a first electrode of the first reset transistor is connected with the first low potential end, and a second electrode of the first reset transistor is connected with the first pull-up node. A gate of the first inverting transistor and a first electrode of the first inverting transistor are connected with the first high potential end, and a second electrode of the first inverting transistor is connected with the first pull-down node; a gate of the second inverting transistor is connected with the first pull-up node, a first electrode of the second inverting transistor is connected with the first low potential end, and a second electrode of the second inverting transistor is connected with the first pull-down node.

5. The display panel of claim 4, wherein, The first inverting transistor comprises a first sub-transistor and a second sub-transistor, a gate of the first sub-transistor and a gate of the second sub-transistor are connected with the first high potential end, a first electrode of the first sub-transistor is connected with the first high potential end, a second electrode of the first sub-transistor is connected with a first electrode of the second sub-transistor, and a second electrode of the second sub-transistor is connected with the first pull-down node.

6. The display panel of claim 1, wherein, The second gate circuit of the second type comprises a second pull-up node, and at least one parallel branch between the second pull-up node and the first low potential end is provided with a transistor between the second pull-up node and the first low potential end.

7. The display panel of claim 6, wherein, The second gate circuit of the second type comprises: a second pull-up control module; a second pull-up module connected with the second pull-up control module at the second pull-up node; a second pull-down module connected with the second pull-up node, the second pull-down node and a second signal output end; a second pull-down maintaining module connected between the second pull-up node and the first low potential end; a second reset module connected between the second pull-up node and the first low potential end; A second inverter is connected with the second pull-up node, the first low potential end and the first high potential end; At least one of the second pull-down module, the second pull-down maintaining module and the second reset module comprises the parallel branch.

8. The display panel of claim 7, wherein, The second pull-up control module comprises a second pull-up control transistor, a gate of the second pull-up control transistor is connected with a second signal output end of the second gate circuit of the upper two stages, a first electrode of the second pull-up control transistor is connected with the first high potential end, and a second electrode of the second pull-up control transistor is connected with the second pull-up node; The second pull-up module comprises a second pull-up transistor, a gate of the second pull-up transistor is connected with the second pull-up node, a first electrode of the second pull-up transistor is connected with a second clock signal line, and a second electrode of the second pull-up transistor is connected with the second signal output end of the second gate circuit of the current stage; The second pull-down module comprises a fourth pull-down transistor, a fifth pull-down transistor and a sixth pull-down transistor, a gate of the fourth pull-down transistor is connected with a second pull-down node, a first electrode of the fourth pull-down transistor is connected with the first low potential end, and a second electrode of the fourth pull-down transistor is connected with the second signal output end of the second gate circuit of the current stage, a gate of the fifth pull-down transistor is connected with the second pull-down node, a first electrode of the fifth pull-down transistor is connected with the first low potential end, and a second electrode of the fifth pull-down transistor is connected with the second pull-up node, a gate of the sixth pull-down transistor is connected with the second signal output end of the second gate circuit of the upper two stages, a first electrode of the sixth pull-down transistor is connected with the first low potential end, and a second electrode of the sixth pull-down transistor is connected with the second pull-down node; The second pull-down maintaining module comprises a second pull-down maintaining transistor, a gate of the second pull-down maintaining transistor is connected with the second signal output end of the second gate circuit of the lower two stages, a first electrode of the second pull-down maintaining transistor is connected with the first low potential end, and a second electrode of the second pull-down maintaining transistor is connected with the second pull-up node; The second reset module comprises a second reset transistor, a gate of the second reset transistor is connected with a reset signal line, a first electrode of the second reset transistor is connected with the first low potential end, and a second electrode of the second reset transistor is connected with the second pull-up node; The gate of the third inverter transistor and the first electrode of the third inverter transistor are connected with the first high potential end, the second electrode of the third inverter transistor is connected with the second pull-down node, the gate of the fourth inverter transistor is connected with the second pull-up node, the first electrode of the fourth inverter transistor is connected with the first low potential end, and the second electrode of the fourth inverter transistor is connected with the second pull-down node.

9. The display panel of claim 8, wherein, The second inverter transistor comprises a third sub-transistor and a fourth sub-transistor, a gate of the third sub-transistor and a gate of the fourth sub-transistor are connected with the first high potential end, a first electrode of the third sub-transistor is connected with the first high potential end, a second electrode of the third sub-transistor is connected with a first electrode of the fourth sub-transistor, and a second electrode of the fourth sub-transistor is connected with the second pull-down node.

10. The display panel of claim 1, wherein, The display panel further comprises a first low potential end, and the third gate circuit comprises a third pull-up node. A transistor is arranged between the third pull-up node and the first low potential end in at least one parallel branch between the third pull-up node and the first low potential end.

11. The display panel of claim 10, wherein, The third gate circuit comprises: a third pull-up control module; a third pull-up module connected with the third pull-up control module at the third pull-up node; a pull-down control module connected with the third pull-up module at the third pull-up node; a third pull-down module connected with the third pull-up node and a third signal output end; a third inverter connected with the third pull-up node, the first low potential end and the first high potential end; At least one of the third pull-down module and the pull-down control module comprises the parallel branch.

12. The display panel of claim 11, wherein, The third pull-up control module comprises a third pull-up control transistor, a gate of the third pull-up control transistor is connected with a second signal output end of a next-stage second gate circuit, a first electrode of the third pull-up control transistor is connected with the first high potential end, and a second electrode of the third pull-up control transistor is connected with the third pull-up node; The third pull-up module comprises a third pull-up transistor, a gate of the third pull-up transistor is connected with the third pull-up node, a first electrode of the third pull-up transistor is connected with a second high potential end, and a second electrode of the third pull-up transistor is connected with a third signal output end of the third gate circuit of the current stage; The pull-down control module comprises a pull-down control transistor, a gate of the pull-down control transistor is connected with a first signal output end of a previous-stage first gate circuit, a first electrode of the pull-down control transistor is connected with the first low potential end, and a second electrode of the pull-down control transistor is connected with the third pull-up node; The third pull-down module comprises a seventh pull-down transistor and an eighth pull-down transistor, a gate of the seventh pull-down transistor is connected with a third pull-down node, a first electrode of the seventh pull-down transistor is connected with a second low potential end, a second electrode of the seventh pull-down transistor is connected with the third signal output end of the third gate circuit of the current stage, a gate of the eighth pull-down transistor is connected with the third pull-down node, a first electrode of the eighth pull-down transistor is connected with the first low potential end, and a second electrode of the eighth pull-down transistor is connected with the third pull-up node; The third inverter further comprises an eighth inverting transistor and a ninth inverting transistor, a gate of the fifth inverting transistor and a first electrode of the fifth inverting transistor are connected with a first signal output end of the first type of gate circuit of the previous stage, a second electrode of the fifth inverting transistor is connected with a gate of the seventh inverting transistor at an inverting node, a gate of the sixth inverting transistor is connected with a second signal output end of the second type of gate circuit of the current stage, a first electrode of the sixth inverting transistor is connected with the first low potential end, a second electrode of the sixth inverting transistor is connected with the gate of the seventh inverting transistor at the inverting node, a first electrode of the seventh inverting transistor is connected with the first high potential end, a second electrode of the seventh inverting transistor is connected with a second electrode of the eighth inverting transistor at the third pull-down node, a gate of the eighth inverting transistor is connected with the third pull-up node, a first electrode of the eighth inverting transistor is connected with the first low potential end, a gate of the ninth inverting transistor is connected with a second signal output end of the second type of gate circuit of the next stage, a first electrode of the ninth inverting transistor is connected with the first low potential end, and a second electrode of the ninth inverting transistor is connected with the second electrode of the seventh inverting transistor at the third pull-down node.

13. The display panel of any of claims 1-12, wherein, The mobility of at least one transistor in the gate driving circuit is greater than the mobility of a transistor in the pixel driving circuit.

14. The display panel of claim 13, wherein, The area of at least one transistor in the gate driving circuit is smaller than the area of a transistor in the pixel driving circuit.

15. The display panel of any one of claims 1-12, wherein, The pixel driving circuit comprises a driving transistor, a switching transistor, a reset transistor and an initialization transistor, the driving transistor, the switching transistor and the reset transistor are connected to a first node, and the driving transistor and the initialization transistor are connected to a second node. The gate of the switching transistor is connected with a first signal output end of the first type of gate circuit of the current stage, the gate of the initialization transistor is connected with a second signal output end of the second type of gate circuit of the current stage, and the gate of the reset transistor is connected with a third signal output end of the third type of gate circuit of the current stage.

16. A display device comprising: The display panel comprises the display panel as claimed in any one of claims 1 to 15.

Images