Switch wake-up circuit

Abstract

The utility model discloses a switch wake-up circuit, which is characterized in that a power supply protection module, a switch jitter elimination module, an energy taking module and a waveform shaping module are arranged in a matched manner, jitter caused by a switch can be eliminated through the switch jitter elimination module, stable waveforms can be effectively output by utilizing the waveform shaping module, power consumption is reduced, and circuit heating is reduced. The problems of misoperation and data errors caused by switch jitter are effectively solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of wake -up circuit, specifically is a switch wake -up circuit. BACKGROUND

[0002] The existing switch wake -up circuit is generally applied to the field of smart home, security monitoring, medical instruments etc., mainly through detecting external signal transmission, for example, button switch presses, sound, light etc., realizes the wake -up of equipment. Press the button switch as an input signal, when the equipment enters the sleep state, the circuit change when the button switch is operated gives the circuit a specific "wake -up" signal, when this signal is triggered, it will be transmitted to the controller of the equipment, thereby realizing the circuit wake -up function, makes the equipment quickly restore to normal state.

[0003] However, the current switch wake -up circuit needs to control the power consumption and response time accurately, so the design is complex, usually including power management unit, microcontroller (MCU), signal sensor, filter, signal amplifier, flip -flop etc. component, wherein the microcontroller needs to rely on software to identify the wake -up signal, leading to the cost of the whole circuit is very high. And because of the mechanical elasticity of the button switch, when the mechanical contact is disconnected or closed, due to the elastic effect of the mechanical contact, a button switch will not be stable when closing, and will not be disconnected at once. Thus the button switch is accompanied by a series of dithering in the moment of closing or opening, the button switch input signal has the problem of burr and dithering, which may cause the backend chip to produce false judgment. UTILITY MODEL CONTENTS

[0004] Therefore, it is necessary to provide a switch wake -up circuit. The application provides a switch wake -up circuit, which can effectively solve the problem of switch dithering through the cooperation of switch dithering elimination module, energy taking module and waveform shaping module, effectively avoid the misoperation and data error caused by dithering.

[0005] A switch wake -up circuit, comprising a power protection module, a switch dithering elimination module, an energy taking module and a waveform shaping module, the signal output end of the power protection module is connected with the signal input end of the switch dithering elimination module, the signal output end of the switch dithering elimination module is connected with the signal input end of the energy taking module, and the signal output end of the energy taking module is connected with the signal input end of the waveform shaping module.

[0006] In one embodiment, the power protection module comprises a power supply, a first switch and a first diode, the positive pole of the power supply is connected with one end of the first switch, the negative pole of the power supply is connected with the ground pole, the other end of the first switch is connected with the positive pole of the first diode, and the negative pole of the first diode is connected with the signal input end of the switch dithering elimination module.

[0007] In one of the embodiments, the switch de-bounce module comprises a first charge-discharge unit and a second charge-discharge unit, a signal input end of the first charge-discharge unit is connected with a negative pole of the first diode, a signal output end of the first charge-discharge unit is connected with a signal input end of the second charge-discharge unit, and a signal output end of the second charge-discharge unit is connected with the energy harvesting module.

[0008] In one of the embodiments, the first charge-discharge unit comprises a first capacitor and a first resistor, one end of the first capacitor is connected with the negative pole of the first diode, the other end is connected with one end of the first resistor, and the other end of the first resistor is connected with the second charge-discharge unit.

[0009] In one of the embodiments, the second charge-discharge unit comprises a second capacitor and a second resistor, one end of the second capacitor is connected with the first capacitor, the other end is connected with one end of the second resistor, the other end of the second resistor is connected with the energy harvesting module, and the first resistor and the second resistor are connected in series.

[0010] In one of the embodiments, the energy harvesting module comprises a third capacitor and a second voltage stabilizing diode, one end of the third capacitor is connected with the other end of the second capacitor, the other end is connected with a ground pole, the third capacitor and the second voltage stabilizing diode are connected in parallel, and a positive pole of the second voltage stabilizing diode is connected with the ground pole.

[0011] In one of the embodiments, the waveform shaping module comprises a shaping unit and a voltage stabilizing unit, a signal input end of the shaping unit is respectively connected with one end of the third capacitor and a negative pole of the second voltage stabilizing diode, and a signal output end of the shaping unit is connected with a signal input end of the voltage stabilizing unit.

[0012] In one of the embodiments, the shaping unit comprises a pull-up resistor, a pull-down resistor, a first current-limiting resistor, a second current-limiting resistor, a third current-limiting resistor, a fourth capacitor, a third voltage stabilizing diode, a first control unit and a second control unit, a first end of the second control unit is connected with one end of the third capacitor, a second end of the second control unit is connected with one end of the pull-down resistor, a third end of the second control unit is connected with the ground pole, the other end of the pull-down resistor is respectively connected with a first end of the first control unit and a positive pole of the third voltage stabilizing diode, the third voltage stabilizing diode is connected with the pull-up resistor in parallel, a second end of the first control unit is connected with one end of the first current-limiting resistor, the other end of the first current-limiting resistor is connected with a negative pole of the third voltage stabilizing diode, a third end of the first control unit is connected with one end of the second current-limiting resistor, the other end of the second current-limiting resistor is connected with the ground pole, the third current-limiting resistor and the fourth capacitor are connected with the second current-limiting resistor in parallel in sequence.

[0013] In one of the embodiments, the voltage stabilizing unit comprises a fourth voltage stabilizing diode connected in parallel with the fourth capacitor, and the positive pole of the fourth voltage stabilizing diode is connected with the ground pole.

[0014] In one of the embodiments, the first control unit is a P-MOS tube, and the second control unit is an N-MOS tube.

[0015] The switch wake-up circuit has the advantages that: through the cooperation of the power protection module, the switch dithering elimination module, the energy extraction module and the waveform shaping module, the switch dithering can be eliminated by the switch dithering elimination module, and the stable waveform can be effectively output by the waveform shaping module, so that the power consumption is reduced, the circuit heating is reduced, and the problems of misoperation and data error caused by switch dithering are effectively solved. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of the switch wake-up circuit of the utility model.

[0017] Figure 2 It is Figure 1 It is a circuit principle diagram of the switch wake-up circuit of the utility model. DETAILED DESCRIPTION

[0018] In order to make the above-mentioned purpose, features and advantages of the utility model more apparent, obvious and easy to understand, the specific embodiments of the utility model are described in detail below in combination with the drawings. In the following description, a lot of specific details are set forth in order to fully understand the utility model. However, the utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the utility model, so the utility model is not limited by the following disclosed specific embodiments.

[0019] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or a middle element can exist simultaneously. In contrast, when an element is referred to as being "directly" connected to another element, no middle element exists.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the utility model belongs. The terms used in the specification of the utility model herein are only for the purpose of describing the specific embodiments and are not intended to limit the utility model. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0021] As Figure 1 And Figure 2As shown, a switch wake-up circuit includes a power protection module 1, a switch dithering elimination module 2, a power extraction module 3, and a waveform shaping module 4. The signal output end of the power protection module 1 is connected to the signal input end of the switch dithering elimination module 2. The signal output end of the switch dithering elimination module 2 is connected to the signal input end of the power extraction module 3. The signal output end of the power extraction module 3 is connected to the signal input end of the waveform shaping module 4.

[0022] After the first switch SW1 of the power protection module 1 is closed, the signal is eliminated of switch dithering by the switch dithering elimination module 2. The waveform shaping module 4 is turned on by using the stable voltage output by the power extraction module 3. After the voltage is stabilized and filtered by the waveform shaping module 4, the stable waveform is output from OUT3 to wake up the rear-end circuit.

[0023] In this way, the switch wake-up circuit is set by the power protection module 1, the switch dithering elimination module 2, the power extraction module 3, and the waveform shaping module 4. The switch dithering caused by the switch can be eliminated by the switch dithering elimination module 2. The stable waveform can be effectively output by the waveform shaping module 4. The power consumption is reduced. The circuit heating is reduced. The problems of misoperation and data error caused by switch dithering are effectively solved.

[0024] In one embodiment, the power protection module 1 includes a power supply, a first switch SW1, and a first diode D1. The positive pole of the power supply is connected to one end of the first switch SW1. The negative pole of the power supply is connected to the ground. The other end of the first switch SW1 is connected to the positive pole of the first diode D1. The negative pole of the first diode D1 is connected to the signal input end of the switch dithering elimination module 2.

[0025] When the first switch SW1 is pressed, the current passes through the first switch SW1 to the first diode D1. Due to the unidirectional conduction characteristic of the first diode D1, when the first diode D1 is turned on, the voltage across the two terminals does not change, which can protect the power supply from being damaged. In addition, since the power supply and the rear-end electrical appliances are controlled by the closure of the first switch SW1, when the first switch SW1 is not closed, the circuit is not woken up, and the entire circuit does not consume power, which can save power energy.

[0026] In one embodiment, the switch dithering elimination module 2 includes a first charge-discharge unit 21 and a second charge-discharge unit 22. The signal input end of the first charge-discharge unit 21 is connected to the negative pole of the first diode D1. The signal output end of the first charge-discharge unit 21 is connected to the signal input end of the second charge-discharge unit 22. The signal output end of the second charge-discharge unit 22 is connected to the power extraction module 3.

[0027] The first charge-discharge unit 21 includes a first capacitor C1 and a first resistor R1, one end of the first capacitor C1 is connected with the negative electrode of the first diode D1, the other end is connected with one end of the first resistor R1, the other end of the first resistor R1 is connected with the second charge-discharge unit 22.

[0028] The second charge-discharge unit 22 includes a second capacitor C2 and a second resistor R2, one end of the second capacitor C2 is connected with the first capacitor C1, the other end is connected with one end of the second resistor R2, the other end of the second resistor R2 is connected with the energy taking module 3, the first resistor R1 and the second resistor R2 are connected in series.

[0029] The first capacitor C1 discharges through the first resistor R1, and the second capacitor C2 discharges through the second resistor R2. When the circuit is powered on, the current passes through the charge-discharge of the first capacitor C1 and the second capacitor C2, which can effectively filter out part of the switch jitter of the first switch SW1. When the key is pressed, the first capacitor C1 and the second capacitor C2 start to charge. Since the capacitor charging needs time, and the mechanical jitter time of the first switch SW1 key is usually short, therefore, during the charging process of the first capacitor C1 and the second capacitor C2, the jitter of the first switch SW1 key will be smoothed out; when the first switch SW1 key is released, the first capacitor C1 and the second capacitor C2 start to discharge. Similarly, since the capacitor discharges need time, the release jitter of the first switch SW1 key will also be smoothed out, and a stable signal is output.

[0030] In one of the embodiments, the energy taking module 3 includes a third capacitor C3 and a second voltage stabilizing diode D2, one end of the third capacitor C3 is connected with the other end of the second capacitor C2, the other end is connected with the ground, the third capacitor C3 and the second voltage stabilizing diode D2 are connected in parallel, and the positive electrode of the second voltage stabilizing diode D2 is connected with the ground GND.

[0031] The third capacitor C3 and the switch anti-jitter module 2 charge through the voltage difference of the voltage after the switch anti-jitter, store energy, effectively control the voltage size, and pass through the overvoltage protection of the second voltage stabilizing diode D2. When the energy in the third capacitor C3 is released, if a spike is generated, the voltage can be clamped to a certain value, a stable voltage OUT1 is provided, and the waveform shaping module 4 is used.

[0032] In one of the embodiments, the waveform shaping module 4 includes a shaping unit 41 and a voltage stabilizing unit 42, the signal input ends of the shaping unit 41 are respectively connected with one end of the third capacitor C3 and the negative electrode of the second voltage stabilizing diode D2, and the signal output end of the shaping unit 41 is connected with the signal input end of the voltage stabilizing unit 42.

[0033] The shaping unit 41 comprises a pull-up resistor R3, a pull-down resistor R5, a first current-limiting resistor R4, a second current-limiting resistor R6, a third current-limiting resistor R7, a fourth capacitor C4, a third voltage stabilizing diode D3, a first control unit Q1 and a second control unit Q2. The first end of the second control unit Q2 is connected with one end of the third capacitor C3, the second end of the second control unit Q2 is connected with one end of the pull-down resistor R5, the third end of the second control unit Q2 is connected with the ground pole GND, the other end of the pull-down resistor R5 is connected with the first end of the first control unit Q1 and the anode of the third voltage stabilizing diode D3 respectively, the third voltage stabilizing diode D3 is connected with the pull-up resistor R3 in parallel, the second end of the first control unit Q1 is connected with one end of the first current-limiting resistor R4, the other end of the first current-limiting resistor R4 is connected with the cathode of the third voltage stabilizing diode D3, the third end of the first control unit Q1 is connected with one end of the second current-limiting resistor R6, the other end of the second current-limiting resistor R6 is connected with the ground pole GND, the third current-limiting resistor R7 and the fourth capacitor C4 are connected with the second current-limiting resistor R6 in parallel in turn.

[0034] The voltage stabilizing unit 42 comprises a fourth voltage stabilizing diode D4, which is connected with the fourth capacitor C4 in parallel, and the anode of the fourth voltage stabilizing diode D4 is connected with the ground pole GND.

[0035] The first control unit Q1 is a P-MOS tube, and the second control unit Q2 is an N-MOS tube. The G pole of the first control unit Q1 is connected with the common connection point between the pull-down resistor R5 and the third voltage stabilizing diode D3, the S pole is connected with one end of the first current-limiting resistor R4, and the D pole is connected with one end of the second current-limiting resistor R6. The G pole of the second control unit Q2 is connected with one end of the third capacitor C3 and the cathode of the second voltage stabilizing diode D2 respectively, the D pole is connected with one end of the pull-down resistor R5, and the S pole is connected with the ground pole GND. The first current-limiting resistor R4 is a current-limiting resistor, which can avoid the power supply from being burnt out. The pull-up resistor R3 and the pull-down resistor R5 also have a certain current-limiting effect.

[0036] Since the first control unit Q1 is pulled up by the pull-up resistor R3, the first control unit Q1 is not turned on. When the voltage output by OUT1 is applied to the G electrode of the second control unit Q2, the second control unit Q2 is turned on. When the second control unit Q2 is turned on, the voltage output by OUT2 is pulled down to the ground by the pull-down resistor R5, and at this time, the voltage at the G electrode of the first control unit Q1 is less than the voltage at the S electrode of the first control unit Q1, so the first control unit Q1 is turned on. At the moment when the first control unit Q1 is turned on, the surge is increased in the current-carrying capacity through the second current-limiting resistor R6 and the third current-limiting resistor R7 in parallel, and the fourth capacitor C4 and the fourth voltage stabilizing diode D4 clamp the voltage, thereby protecting the rear-end electrical appliance from being damaged. The two-stage MOS tube is turned on, the duty cycle of the circuit can be improved, the narrow waveform is changed into a stable wide waveform, the output stable waveform OUT3 is output, and the rear-end circuit is woken up, so that the rear-end circuit is prevented from being mistakenly started due to the sharp peak or the clutter of the waveform, and the safe and stable operation of the circuit is ensured.

[0037] The working principle of the present application is as follows: when the first switch SW1 is closed, the circuit flows through the first diode D1, and after the first capacitor C1, the first resistor R1, the second capacitor C2 and the second resistor R2 at the rear end are charged and discharged, a part of the jitter of the first switch SW1 is eliminated, the third capacitor C3 is used to take power, the second voltage stabilizing diode D2 clamps the voltage, the stable voltage is applied to OUT2, the second control unit Q2 is turned on, after the second control unit Q2 is turned on, the voltage at OUT2 is pulled down to the ground by the pull-down resistor R5, at this time, the first control unit Q1 is turned on, after the second current-limiting resistor R6, the third current-limiting resistor R7 and the fourth capacitor C4 at the rear end are filtered, the output stable waveform OUT3 is output, and the rear-end circuit is woken up. The entire circuit uses a plurality of discrete devices, so that the circuit is more simple, and the cost of the entire circuit is effectively reduced.

[0038] The technical features of the above-described embodiments can be combined in any manner, and to make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the description.

[0039] The above-described embodiments only express several implementation manners of the present application, the description is relatively specific and detailed, but it should not be understood as the limitation of the scope of the utility model patent. It should be pointed out that for ordinary skilled persons in the art, on the premise of not departing from the concept of the present application, a plurality of modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the utility model patent should be subject to the appended claims.

Claims

1. A switch wake-up circuit, characterized by: The power protection module, the switch dithering elimination module, the energy taking module and the waveform shaping module are connected in series.

2. The switch wake-up circuit of claim 1, wherein: The power protection module comprises a power supply, a first switch and a first diode.

3. A switch wake-up circuit according to claim 2, characterized in that: The switch dithering elimination module comprises a first charge-discharge unit and a second charge-discharge unit.

4. The switch-wake-up circuit of claim 3, wherein: The first charge-discharge unit comprises a first capacitor and a first resistor.

5. A switch wake-up circuit according to claim 4, characterized in that: The second charge-discharge unit comprises a second capacitor and a second resistor.

6. A switch-wake-up circuit according to claim 5, characterized in that: The energy taking module comprises a third capacitor and a second voltage stabilizing diode.

7. A switch-wake-up circuit according to claim 6, characterized in that: The waveform shaping module comprises a shaping unit and a voltage stabilizing unit. The shaping unit is connected to the third capacitor and the second voltage stabilizing diode. The voltage stabilizing unit is connected to the shaping unit.

8. A switch-wake-up circuit according to claim 7, characterized in that: The shaping unit comprises a pull-up resistor, a pull-down resistor, a first current-limiting resistor, a second current-limiting resistor, a third current-limiting resistor, a fourth capacitor, a third voltage stabilizing diode, a first control unit and a second control unit, a first end of the second control unit is connected with one end of the third capacitor, a second end of the second control unit is connected with one end of the pull-down resistor, a third end of the second control unit is connected with a ground, the other end of the pull-down resistor is connected with a first end and a positive electrode of the third voltage stabilizing diode of the first control unit respectively, the third voltage stabilizing diode is connected with the pull-up resistor in parallel, a second end of the first control unit is connected with one end of the first current-limiting resistor, the other end of the first current-limiting resistor is connected with a negative electrode of the third voltage stabilizing diode, a third end of the first control unit is connected with one end of the second current-limiting resistor, the other end of the second current-limiting resistor is connected with the ground, the third current-limiting resistor and the fourth capacitor are connected with the second current-limiting resistor in parallel in sequence.

9. A switch wake-up circuit according to claim 8, characterised in that: The voltage stabilizing unit comprises a fourth voltage stabilizing diode, the fourth voltage stabilizing diode is connected with the fourth capacitor in parallel, and a positive electrode of the fourth voltage stabilizing diode is connected with the ground.

10. The switch-wake-up circuit of claim 8, wherein: The first control unit is a P-MOS tube, and the second control unit is an N-MOS tube.

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