Battery assembly, power utilization device and power generation device

Abstract

The utility model discloses a battery assembly, a power utilization device and a power generation device, and the battery assembly comprises a first substrate, a second substrate located on the first substrate, and a battery packaged between the first substrate and the second substrate. The first sealing layer is positioned between the battery and the second substrate and covers at least part of the battery; wherein the first sealing layer comprises a first sub-layer and a second sub-layer located on the side, away from the battery, of the first sub-layer, the first sub-layer and the second sub-layer are made of different materials, and the mobility of the second sub-layer is larger than that of the first sub-layer at the preset temperature.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of batteries, and in particular to a battery assembly, a power consumption device and a power generation device. BACKGROUND

[0002] In the photovoltaic industry, solar cells are usually packaged between front plate glass and back plate glass, and a high-temperature lamination process is a necessary step in the packaging process of solar cells. This process can firmly bond the front plate glass, solar cells and back plate glass together, increasing the overall mechanical strength of the battery assembly.

[0003] During the lamination process, a high temperature is usually applied to the battery assembly over a long period of time, so that the battery assembly is continuously subjected to heat. However, some film layers in the solar cell assembly (such as the light-absorbing layer in thin-film solar cells) may be negatively affected by decomposition or phase change at high temperatures, resulting in reduced performance of the battery assembly. CONTENT OF THE UTILITY MODEL

[0004] To solve the above technical problems, the present application provides a battery assembly to reduce the lamination temperature and time of the battery assembly, thereby avoiding or alleviating the negative effects of the lamination process on the film layers in the battery assembly and reducing the performance loss of the battery assembly.

[0005] The present application is implemented by the following technical solutions.

[0006] The first aspect of the present application provides a battery assembly, comprising: a first substrate, a second substrate located on the first substrate, and a battery encapsulated between the first substrate and the second substrate; a first sealing layer located between the battery and the second substrate and covering at least part of the battery; wherein the first sealing layer comprises a first sub-layer and a second sub-layer located on the side of the first sub-layer away from the battery, the materials of the first sub-layer and the second sub-layer are different, and at a preset temperature, the flowability of the second sub-layer is greater than that of the first sub-layer.

[0007] In the present application, the battery is sealed by a first sealing layer, the first sealing layer includes a first sub-layer close to the battery and a second sub-layer away from the battery, and at a preset temperature, the flowability of the second sub-layer is greater than that of the first sub-layer. In this way, the setting of the second sub-layer with greater flowability can allow the lamination process to be performed on the battery assembly at a lower temperature and reduce the lamination time, and the second sub-layer makes up for the problem of insufficient flowability of the first sub-layer with smaller flowability when lamination at low temperature, and cooperates with the first sub-layer to flow and fill small gaps, thereby improving the water and oxygen barrier property of the first sealing layer and reducing the lamination time, and the reduction of lamination temperature and lamination time can avoid or alleviate the decomposition or phase change of the film layer (such as the light absorbing layer) in the battery, thereby reducing the performance loss of the battery; at the same time, the first sub-layer is arranged between the second sub-layer and the battery to avoid direct contact between the second sub-layer and the battery, thereby avoiding or reducing damage to the battery caused by the second sub-layer due to aging or corrosion. In addition, the second sub-layer has greater flowability and smaller hardness, which can effectively alleviate the lamination stress.

[0008] In any embodiment, the battery assembly further comprises:

[0009] At least one bus bar, one end of the bus bar is connected with the battery, and the other end is led out from the space formed by the first substrate and the second substrate; the bus bar at least includes a first sub-part, the first sub-part is located between the first substrate and the second substrate and extends in a direction substantially parallel to the plane of the first substrate; a buffer layer is located between the first substrate and the second substrate and covers at least part of the first sub-part in the extension direction of the first sub-part.

[0010] In this way, during the lamination process of the battery assembly, the buffer layer plays a role in buffering stress, thereby alleviating the lamination stress received by the first sub-part, and further reducing the lamination stress inside the battery assembly.

[0011] In any embodiment, the first sub-part includes a first sub-section and a second sub-section connected in series, and the buffer layer at least covers the first sub-section; the battery assembly further comprises: a conductive adhesive tape, the conductive adhesive tape is located on the side surface of the battery away from the first substrate, and the first sub-section is clamped between the conductive adhesive tape and at least part of the buffer layer. In this way, the bus bar realizes electrical connection with the battery through the conductive adhesive tape, and the conductive adhesive tape, the first sub-section and the buffer layer form a sandwich structure, which plays a role in protecting the first sub-section and buffering the lamination stress, and can further alleviate the lamination stress received by the first sub-section.

[0012] In any of the embodiments, the first sub-portion comprises a first sub-section and a second sub-section connected to each other, the buffer layer covers at least the second sub-section, and the second sub-section and the buffer layer covering the second sub-section are located between the first sub-layer and the battery; the battery assembly further comprises an insulation layer located on a side surface of the battery away from the first substrate, and the second sub-section is sandwiched between the insulation layer and at least part of the buffer layer. In this way, the insulation layer is used to separate the second sub-section and part of the battery to avoid the risk of short circuit, and the insulation layer, the second sub-section and the buffer layer also form a sandwich structure, which can further relieve the stress on the second sub-section.

[0013] In any of the embodiments, the first sub-portion comprises a first sub-section and a second sub-section connected to each other, the buffer layer covers at least the second sub-section, and the second sub-section and the buffer layer covering the second sub-section are located between the first sub-layer and the second sub-layer. In this way, the effect of relieving the stress on the second sub-section can be further increased.

[0014] In any of the embodiments, the hardness of the buffer layer is less than the hardness of the first sub-layer, so that the buffering effect of the buffer layer can be further increased; and / or,

[0015] At the preset temperature, the flowability of the buffer layer is less than the flowability of the second sub-layer, so that the buffer layer can play a role in shaping the second sub-section during the lamination process, further increasing its stress-relieving effect.

[0016] In any of the embodiments, the battery assembly satisfies one or more of the following conditions:

[0017] (1) The material of the first sub-layer comprises one or more of polyolefin elastomer, ethylene-vinyl acetate copolymer, polyvinyl butyral ester, thermoplastic polyurethane elastomer, thermoplastic polyolefin, and polyethylene foam;

[0018] (2) The material of the second sub-layer comprises one or more of solid silicone rubber, liquid silicone rubber, epoxy resin, and polydimethylsiloxane;

[0019] (3) The thickness of the first sub-layer is between 0.3 mm and 0.5 mm;

[0020] (4) The thickness of the second sub-layer is between 0.5 mm and 1 mm.

[0021] In this way, the first sub-layer is adapted to a lower lamination temperature to promote its flowability in a low-temperature lamination process; and / or, the synergistic flow effect of the second sub-layer is increased.

[0022] In any of the embodiments, the material of the buffer layer comprises one or more of butyl tape, ethylene-propylene-diene monomer tape, ethylene-vinyl acetate copolymer tape, and silicone rubber tape.

[0023] In any of the embodiments, the battery comprises a light-absorbing layer, which comprises one or more of a perovskite light-absorbing layer, an amorphous silicon light-absorbing layer, a copper-indium-gallium-selenium light-absorbing layer, a cadmium telluride light-absorbing layer, a gallium arsenide light-absorbing layer, and an organic dye light-absorbing layer, so as to expand the application scenarios of the solar cell.

[0024] In any of the embodiments, the light-absorbing layer comprises a perovskite light-absorbing layer; the battery further comprises a first electrode layer and a second electrode layer, and the perovskite light-absorbing layer is located between the first electrode layer and the second electrode layer. The technical solution of the present application can be applied to a perovskite solar cell, so as to reduce the lamination temperature and lamination time of the perovskite battery assembly, thereby avoiding or alleviating the decomposition or phase change of the perovskite light-absorbing layer due to the excessively high lamination temperature in the lamination process, and reducing the performance loss of the battery assembly.

[0025] In any of the embodiments, the battery further comprises a first transport layer and / or a second transport layer, wherein the first transport layer is located between the first electrode layer and the perovskite light-absorbing layer, the second transport layer is located between the perovskite light-absorbing layer and the second electrode layer, the first transport layer is one of an electron transport layer or a hole transport layer, and the second transport layer is the other of the electron transport layer or the hole transport layer. The first transport layer and / or the second transport layer are used to increase the transport of carriers in the perovskite solar cell.

[0026] The second aspect of the present application further provides a power consumption device comprising the battery assembly of the first aspect of the present application.

[0027] The third aspect of the present application further provides a power generation device comprising the battery assembly of the first aspect of the present application.

[0028] The details of one or more embodiments of the present disclosure are presented in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.

[0030] Figure 1a The schematic block diagram of the power consumption device provided by some embodiments of the present application is shown in FIG. 1. Figure 1bA schematic block diagram of a power generation device provided for some embodiments of the present application;

[0031] Figure 2a A top view schematic diagram of a battery assembly provided for some embodiments of the present application, Figure 2b A cross-sectional structure schematic diagram taken along the line AA' in Figure 2a A cross-sectional structure schematic diagram taken along the line BB' in Figure 2c A cross-sectional structure schematic diagram taken along the line AA' in Figure 2a A cross-sectional structure schematic diagram taken along the line BB' in Figure 2d A structure schematic diagram of a sub-cell in Figure 2a A structure schematic diagram of a sub-cell in

[0032] Figure 3a A cross-sectional structure schematic diagram taken along the line AA' in Figure 2a A cross-sectional structure schematic diagram taken along the line BB' in Figure 3b A cross-sectional structure schematic diagram taken along the line AA' in Figure 2a A cross-sectional structure schematic diagram taken along the line BB' in

[0033] Explanation of reference signs:

[0034] 1 power consuming device; 2 power generation device; 100 battery assembly; 101 first substrate; 102 second substrate; 12 battery; 13 sub-cell; 131 first electrode layer; 132 functional layer; 1321 first transport layer; 1322 light absorbing layer; 1323 second transport layer; 133 second electrode layer; 14 first sealing layer; 141 first sub-layer; 142 second sub-layer; 15 bus bar; 151 first sub-portion; 152 second sub-portion; 1511 first sub-segment; 1512 second sub-segment; 16 conductive tape; 17 buffer layer; 18 insulation layer; 19 via structure; 21 second sealing layer. DETAILED DESCRIPTION

[0035] Example embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While example embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0036] In the following description, numerous specific details are given to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features are not described in detail to avoid obscuring the present disclosure. In addition, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features are not described in detail to avoid obscuring the present disclosure.

[0037] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numbers in different drawings can indicate like elements.

[0038] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0039] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] During the lamination process of the battery assembly, a high temperature is usually applied to the battery assembly for a long time, for example, a temperature between 120 and 160 degrees Celsius is applied to the back plate glass and maintained for more than 15 minutes, so that the battery assembly is continuously subjected to heat. However, some film layers in the solar cell assembly, such as the light absorption layer in the thin film solar cell, may change, such as decomposition or phase change, at high temperatures, resulting in reduced performance of the battery assembly. For example, the perovskite layer in the perovskite solar cell may decompose or change phase at high temperatures, causing changes in its original photoelectric performance. For example, common methylammonium lead iodide (MAPbI3) may decompose into PbI2 and other substances at high temperatures, causing changes in the absorption spectrum of the perovskite layer, narrowing the absorption range and reducing the absorption coefficient, which in turn weakens the light absorption ability of the battery and reduces the photoelectric conversion efficiency.

[0042] In related technologies, the decomposition or phase change of the light absorption layer can be alleviated by reducing the lamination temperature. However, reducing the lamination temperature can result in insufficient flowability of the polymer encapsulation material such as the adhesive film during the lamination process, which cannot flow to every small gap, resulting in a decrease in the water and oxygen barrier properties of the encapsulation material. At the same time, the low flowability of the encapsulation material during low-temperature lamination can cause a large impact stress on the structure of the encapsulation substrate and metal bus bar, reducing the performance and stability of the battery assembly, and in severe cases, damaging the battery assembly.

[0043] In related technologies, the encapsulation material can also be improved, for example, TiO2 can be doped in the adhesive film to modify it to reduce the melting point of the adhesive film. In addition, the perovskite layer can also be doped to improve the lattice thermal stability of the perovskite layer. However, improving the encapsulation material cannot improve the thermal stability of the light absorption layer, and adjusting the heat resistance of the light absorption layer may increase the photoelectric loss and cost of the battery.

[0044] Based on this, the inventors propose a technical solution in which a first sealing layer is used to seal the battery, the first sealing layer includes a first sub-layer close to the battery and a second sub-layer away from the battery, and at a preset temperature, the flowability of the second sub-layer is greater than that of the first sub-layer. In this way, the provision of the second sub-layer with greater flowability allows the lamination process to be performed on the battery assembly at a lower temperature and reduces the lamination time. The second sub-layer makes up for the insufficient flowability of the first sub-layer with less flowability when lamination is performed at low temperature, cooperates with the first sub-layer to fill small gaps, thereby improving the water and oxygen barrier property of the first sealing layer and reducing the lamination time. The reduction of lamination temperature and lamination time can avoid or alleviate the decomposition or phase change of the film layer (such as the light-absorbing layer) in the battery, thereby reducing the performance loss of the battery. At the same time, the first sub-layer is arranged between the second sub-layer and the battery, avoiding direct contact between the second sub-layer and the battery, thereby avoiding or reducing damage to the battery caused by the second sub-layer dissolving to produce by-products or harmful gases due to aging or corrosion. In addition, the second sub-layer has greater flowability and smaller hardness, which can effectively alleviate the lamination stress.

[0045] The technical solutions described in the embodiments of the present application are applicable to battery assemblies, electric devices using battery assemblies, and power generation devices using battery assemblies. Figure 1a A schematic block diagram of an electric device 1 provided for some embodiments of the present application includes a battery assembly 100. The electric device 1 can be a vehicle, a mobile phone, a portable device, a notebook computer, a ship, a spacecraft, an electric toy, and an electric tool, etc. The vehicle can be a fuel automobile, a gas automobile, or a new energy automobile; the spacecraft includes an airplane, a rocket, a space shuttle, and a spacecraft, etc.; the electric toy includes a fixed or mobile electric toy, such as a game console, an electric car toy, an electric ship toy, and an electric airplane toy, etc.; the electric tool includes a metal cutting electric tool, a grinding electric tool, an assembly electric tool, and a railway electric tool, such as an electric drill, an electric grinder, an electric wrench, an electric screwdriver, an electric hammer, an impact drill, a concrete vibrator, and an electric planer, etc. The embodiments of the present application do not specially limit the above-mentioned electric device 1.

[0046] Figure 1b A schematic block diagram of a power generation device 2 provided for some embodiments of the present application includes a battery assembly 100. The power generation device 2 can also have a control system and a transmission system. The power generation device 2 provided by the present application adjusts the electric energy generated from the battery assembly 100 to electric energy that can match the electric equipment through the control system and the transmission system.

[0047] To make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure will be described in detail below with reference to the drawings. Among them, Figure 2aFig. 1 is a top view of a battery assembly without a buffer layer, a first sealing layer, a second sealing layer, and a second substrate; Figure 2a Fig. 2 is a top view of a battery assembly without a first sealing layer, a second sealing layer, and a second substrate.

[0048] In the detailed description of the embodiments of the present disclosure, the schematic views are partially enlarged without the general proportion for the convenience of illustration, and the schematic views are only examples, which should not limit the protection scope of the present disclosure herein.

[0049] As shown in the accompanying drawings, Figure 2a to Figure 3b The battery assembly provided by the embodiments of the present disclosure includes a first substrate 101, a second substrate 102 located on the first substrate 101, and a battery 12 encapsulated between the first substrate 101 and the second substrate 102; a first sealing layer 14 located between the battery 12 and the second substrate 102 and covering at least part of the battery 12; wherein the first sealing layer 14 includes a first sub-layer 141 and a second sub-layer 142 located on the side of the first sub-layer 141 away from the battery 12, the materials of the first sub-layer 141 and the second sub-layer 142 are different, and the fluidity of the second sub-layer 142 is greater than that of the first sub-layer 141 at a preset temperature.

[0050] In some embodiments, the materials of the first substrate 101 and the second substrate 102 can be the same or different. In some embodiments, the first substrate 101 and the second substrate 102 include inorganic substrates made of quartz, sapphire, glass, etc., and transparent plastic substrates made of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polystyrene, polyethylene, polypropylene, polyphenylene sulfide, polyvinylidene fluoride, cellulose tetraacetate, brominated phenoxy, aromatic polyamide, polyimide, polystyrene, polyarylate, polysulfone, polyolefin, etc. In a specific embodiment, the first substrate 101 and the second substrate 102 can both be glass substrates.

[0051] In some embodiments, the battery 12 includes a solar cell, and the number of the solar cell can be one or multiple. If the solar cell is multiple, the multiple solar cells can be connected in series, in parallel, or in a mixed connection. The mixed connection means that the multiple solar cells are connected in series and in parallel at the same time, which can provide higher voltage and capacity.

[0052] In some embodiments, the solar cell can include one or multiple sub-cells 13. If the number of the sub-cells 13 is multiple, the multiple sub-cells 13 can be connected in series, in parallel, or in a mixed connection. Figure 2a As shown in the accompanying drawings, in some embodiments, the battery 12 includes multiple sub-cells 13 arranged along a first direction on the first substrate 101 and extending along a direction intersecting with the first direction (including perpendicular or oblique). The multiple sub-cells 13 are connected in series along the first direction.

[0053] As shown in the drawings, in some embodiments, the sub-cell 13 comprises a first electrode layer 131, a functional layer 132 and a second electrode layer 133 stacked in order from bottom to top on the first substrate 101. Figure 2d

[0054] In some embodiments, the material of the first electrode layer 131 can be a transparent conductive material, including but not limited to one or more of indium tin oxide (ITO), aluminum zinc oxide (AZO), tungsten-doped indium oxide (IWO), cerium-doped indium oxide (ICO), fluorine-doped tin oxide (FTO), zinc-doped zinc oxide (IZO) and antimony-doped tin oxide (ATO), for example fluorine-doped tin oxide (FTO).

[0055] In some embodiments, the material of the second electrode layer 133 can include a metal electrode material, a carbon material, a transparent conductive material or a composite electrode material composed of a metal electrode material and a transparent conductive material; wherein the metal electrode material includes one or more of silver, aluminum, gold, copper, titanium, chromium, nickel, platinum and palladium, and the carbon material includes graphene and the like.

[0056] In some embodiments, the functional layer 132 includes a light-absorbing layer 1322 located between the first electrode layer 131 and the second electrode layer 133; the light-absorbing layer 1322 can be one or more of a perovskite layer, an amorphous silicon light-absorbing layer, a copper indium gallium selenide light-absorbing layer, a cadmium telluride light-absorbing layer, a gallium arsenide light-absorbing layer and an organic dye light-absorbing layer, which can be used to prepare a thin-film solar cell with a light-absorbing layer thickness of microns or nanometers, so as to expand the application scenarios of the solar cell. Further, the light-absorbing layer 1322 can be a perovskite light-absorbing layer, and the cell 12 includes a perovskite solar cell, so that the technical solutions provided by the present application can be used to reduce the lamination temperature and lamination time of the perovskite solar cell, thereby avoiding or alleviating decomposition or phase change of the perovskite layer.

[0057] In some embodiments, the functional layer 132 further includes a first transport layer 1321 located between the first electrode layer 131 and the light-absorbing layer 1322, and / or a second transport layer 1323 located between the light-absorbing layer 1322 and the second electrode layer 133, one of the first transport layer 1321 and the second transport layer 1323 being an electron transport layer and the other being a hole transport layer. The provision of the electron transport layer and / or the hole transport layer helps to extract and transport the electron-hole pairs generated by the light-absorbing layer 1322 to the corresponding electrode, thereby improving the carrier transport capability. The electron transport layer and the hole transport layer can be respectively provided on both sides of the light-absorbing layer 1322 according to actual conditions, or one of the two can be provided on one side of the light-absorbing layer 1322, such as only the hole transport layer, which is not limited herein.

[0058] ​In some embodiments, the first transport layer 1321 is located between the first electrode layer 131 and the perovskite light-absorbing layer, and / or the second transport layer 1323 is located between the perovskite light-absorbing layer and the second electrode layer 133. Thus, the first transport layer 1321 and the second transport layer 1323 can improve the carrier transport capability in the perovskite solar cell.

[0059] The electron transport layer material is an n-type semiconductor with electron transport capabilities. Specific materials include, but are not limited to, titanium oxide (TiO2), tin oxide (SnO2), zinc oxide (ZnO), vanadium oxide (V2O5), zinc tin oxide (Zn2SnO4), and fullerene C. 60 (C 60 ), fullerene C 70 (C 70 ) and fullerene derivatives (such as [6,6]-phenyl-C61-butyrate isomethyl ester, PC 61 One or more of BM, etc., without specific restrictions here.

[0060] The hole transport layer material is a p-type semiconductor with hole transport capability. Specific materials include, but are not limited to, one or more of the following: nickel oxide (NiOx), cuprous oxide (Cu2O), molybdenum oxide (MoO3), copper iodide (CuI), cuprous thiocyanate (CuSCN), zinc oxide, 2,2',7,7'-tetratetra(N,N-p-methoxyaniline)-9, 9'-spirodifluorene (Spiro-OMeTAD), poly[bis(4-phenyl)((2,4,6-trimethylphenyl)amine] (PTAA), and [4-(3,6-dimethyl-9H-carbazole-9-yl)butyl]phosphate (Me-4PACz), etc., without specific limitations.

[0061] In some embodiments, in order to further improve the photoelectric conversion efficiency, an interface treatment layer may be added between different film layers in the first electrode layer 131, the functional layer 132 and the second electrode layer 133, such as a passivation layer for passivating defects in the light-absorbing layer disposed on one side of the light-absorbing layer 1322, or a blocking layer for blocking hole transport disposed on one side of the electron transport layer.

[0062] like Figure 2b and Figure 2cAs shown, in the embodiments of the present application, the battery 12 is encapsulated between the first substrate 101 and the second substrate 102, and the battery 12 is sealed by the first sealing layer 14 to reduce the moisture entering the inside of the battery assembly; the first sealing layer 14 covers at least part of the battery 12, the first sealing layer 14 includes a first sub-layer 141 close to the battery 12 and a second sub-layer 142 away from the battery 12, and at a preset temperature, the flowability of the second sub-layer 142 is greater than that of the first sub-layer 141, so that the setting of the second sub-layer 142 with greater flowability can allow the lamination process of the battery assembly to be performed at a lower temperature, and the second sub-layer 142 with greater flowability makes up for the problem of insufficient flowability of the first sub-layer 141 in low-temperature lamination, cooperates with the first sub-layer 141 to fill small gaps, thereby improving the water and oxygen barrier property of the first sealing layer 14, increasing the sealing effect of the first sealing layer 14 on the battery assembly, and the greater flowability increases the filling efficiency of the first sealing layer 14, thereby being able to reduce the lamination time; the reduction of the lamination temperature and the reduction of the lamination time can avoid or alleviate the decomposition or phase change of the film layer (such as the light-absorbing layer) in the battery 12, thereby reducing the performance loss of the battery 12. In actual operation, the second sub-layer 142 may

[0063] Here, the preset temperature can be the temperature received by the first sealing layer 14 when the lamination process of the battery assembly is performed in actual operation. In some embodiments, by using the technical solution of the present application, compared with related technologies, the lamination temperature can be reduced by 10-20°C (including the end point value), such as 10°C, 15°C, 20°C, etc., and the lamination time can be shortened by 5-10 min (including the end point value), such as 5 min, 8 min, 10 min, etc. In some embodiments, by using the technical solution of the present application, the lamination temperature can be controlled to be between 60-140°C (including the end point value, such as between 60-120°C, between 60-135°C, between 70-130°C, or between 70-140°C, etc.), and the lamination time can be controlled to be between 20-25 min (including the end point value), such as 15 min, etc.

[0064] In some embodiments, the material of the first sublayer 141 includes one or more of polyolefin elastomer (POE), ethylene-vinyl acetate copolymer (EVA), polyvinyl butyral (PVB), thermoplastic polyurethane elastomer (TPU), thermoplastic polyolefin (TPO), and polyethylene foam (EPE). In some embodiments, the thickness of the first sublayer 141 is between 0.3 mm and 0.5 mm (inclusive), for example, 0.4 mm. Thus, the material of the first sublayer 141 includes a low-melting-point material, and / or the thickness of the first sublayer 141 is within the above range, to adapt it to a lower lamination temperature and promote its flowability in low-temperature lamination processes.

[0065] In some embodiments, the material of the second sublayer 142 includes one or more of solid silicone rubber (e.g., low-temperature vulcanized solid silicone rubber), liquid silicone rubber, epoxy resin, polydimethylsiloxane, etc., wherein the silicone rubber includes one or more of dimethyl silicone rubber, methyl vinyl silicone rubber, low-phenyl silicone rubber, etc.; the epoxy resin includes solid epoxy resin and / or liquid epoxy resin, and the polydimethylsiloxane includes liquid polydimethylsiloxane and / or solid polydimethylsiloxane. In some embodiments, the thickness of the second sublayer is between 0.5 mm and 1 mm (inclusive), for example 0.8 mm. Thus, the material of the second sublayer 142 includes a material with high fluidity at a preset temperature, and / or the thickness of the second sublayer 142 is within the above range, thereby increasing the synergistic flow effect of the second sublayer 142, and the second sublayer 142 has a low melting point, thereby reducing the lamination temperature; in addition, the second sublayer 142 has the characteristic of low-temperature curing, which can better protect the battery assembly after curing.

[0066] It should be noted that the battery module of this application can be a battery module before lamination, during lamination, or after lamination. When the battery module is a battery module before lamination, the material of the second sublayer 142 can be a liquid material or a solid material; when the battery module is a battery module during lamination, the material of the second sublayer 142 can be a liquid material; and when the battery module is a battery module after lamination, the material of the second sublayer 142 can be a solid material.

[0067] like Figure 2a to Figure 2c As shown, in some embodiments, the battery assembly further includes at least one busbar 15, one end of which is connected to the battery 12, and the other end extends out from the space formed by the first substrate 101 and the second substrate 102. In practice, there may be two busbars 15, which are respectively connected to the positive and negative terminals of the battery 12 to draw out the current generated by the battery 12. In practice, the material of the busbar 15 includes one or more of copper, aluminum, silver, gold, tin-plated copper, or their alloys.

[0068] In some embodiments, the busbar 15 includes at least a first sub-part 151, which is located between the first substrate 101 and the second substrate 102 and extends in a direction substantially parallel to the plane of the first substrate 101. The battery assembly further includes a buffer layer 17, which is located between the first substrate 101 and the second substrate 102 and covers at least a portion of the first sub-part 151 along the extension direction of the first sub-part 151. Thus, during the lamination process of the battery assembly, the buffer layer 17 acts as a buffer to relieve the lamination stress on the first sub-part 151, thereby reducing the lamination stress inside the battery assembly.

[0069] In some embodiments, the width of the buffer layer 17 may be equal to or slightly larger than the width of the first sub-part 151. Here, width refers to the length of the buffer layer 17 and the first sub-part 151 extending in a direction perpendicular to the extending direction of the first sub-part 151.

[0070] In some embodiments, the first sub-part 151 includes a first sub-segment 1511 and a second sub-segment 1512 connected together, and the buffer layer 17 at least covers the first sub-segment 1511. The battery assembly further includes a conductive tape 16, which is located on the side surface of the battery 12 facing away from the first substrate 101, and the first sub-segment 1511 is sandwiched between the conductive tape 16 and at least a portion of the buffer layer 17. Thus, the busbar 15 achieves electrical connection with the battery 12 through the conductive tape 16, and the conductive tape 16, the first sub-segment 1511, and the buffer layer 17 form a sandwich structure, which protects the first sub-segment 1511 and buffers the lamination stress, further alleviating the lamination stress on the first sub-segment 1511. In actual operation, the conductive tape 16 can be a conductive cloth-based tape and / or a conductive rubber tape, etc.

[0071] like Figure 2a As shown in Figure (1), in some embodiments, the conductive tape 16 and the first segment 1511 are disposed on the side surface of the sub-battery 13 located at the edge along the first direction away from the first substrate 101 and extend along the extension direction of the sub-battery 13. The second segment 1512 is connected to the first segment 1511 and extends towards the middle region of the battery 12 on the side of the battery 12 away from the first substrate 101. However, it is not limited to this. The first segment 1511 can also be electrically connected to other sub-batteries 13, and the second segment 1512 can also be disposed in other locations. For example, the second segment 1512 can also be disposed on at least one side of the battery 12 in the extension direction of the sub-battery 13.

[0072] like Figure 2cAs shown, in some embodiments, the buffer layer 17 at least covers the second sub-segment 1512, and the second sub-segment 1512 and the buffer layer 17 covering the second sub-segment 1512 are located between the first sub-layer 141 and the battery 12; the battery assembly also includes: an insulating layer 18, the insulating layer 18 is located on the side surface of the battery 12 facing away from the first substrate 101, and the second sub-segment 1512 is sandwiched between the insulating layer 18 and at least part of the buffer layer 17. Thus, the insulating layer 18 is used to separate the second sub-segment 1512 and part of the battery 12 to avoid the risk of short circuit, and the insulating layer 18, the second sub-segment 1512 and the buffer layer 17 also form a sandwich structure, which can further alleviate the lamination stress on the second sub-segment 1512.

[0073] like Figure 2a As shown in Figure (2), the buffer layer 17 can simultaneously cover the first sub-segment 1511 and the second sub-segment 1512.

[0074] It should be noted that, in this application, the extension of the first sub-part 151 along a direction substantially parallel to the plane of the first substrate 101 means that the extension direction of the first sub-part 151 is parallel or approximately parallel to the plane of the first substrate 101, or that the extension direction of a portion of the first sub-part 151 is parallel to the plane of the first substrate 101, while the extension direction of a portion of the first sub-part 151 is approximately parallel to the plane of the first substrate 101. Here, the approximately parallelism may be caused by the different thicknesses of the film layer at different locations below the first sub-part 151.

[0075] In some embodiments, the hardness of the buffer layer 17 is less than the hardness of the first sub-layer 141. In some embodiments, the material of the buffer layer may include one or more of butyl tape, ethylene propylene diene monomer (EPDM) tape, ethylene-vinyl acetate copolymer (EVA) tape, silicone rubber tape, etc. Thus, by providing a buffer layer 17 with lower material hardness above the first sub-part 151, and by using the buffer layer 17 to separate the first sub-part 151 from the first sub-layer 141 with higher hardness, the effect of relieving the lamination stress on the first sub-part 151 can be increased.

[0076] like Figure 2c As shown, the first sealing layer 14 covers all sub-cells 13 except for the sub-cells 13 located at the edge along the first direction. However, it is not limited to this. The first sealing layer 14 can also cover the entire battery 12, that is, it can also cover the sandwich structure composed of conductive tape 16, first sub-segment 1511 and buffer layer 17 located at the edge of battery 12 along the first direction.

[0077] like Figure 2cAs shown, in an embodiment, the busbar 15 can further include a second sub-portion 152 connected with the first sub-portion 151; the battery assembly can further include at least one through-hole structure 19, the second sub-portion 152 passing through the first sealing layer 14 and out of the through-hole structure 19 to lead out the current generated by the battery 12. In some embodiments, a junction box can be provided on the second substrate 102 to lead the second sub-portion 152 into the junction box. In actual operation, the through-hole structure 19 can be filled with a sealing material (not shown).

[0078] As shown, Figure 2a to Figure 2c in some embodiments, the edges of the battery 12 are recessed inwardly relative to the edges of the first substrate 101 and the second substrate 102; the battery assembly can further include a second sealing layer 21 provided along the edges of the first substrate 101 and the second substrate 102, and the second substrate 102 and the first substrate 101 are sealedly connected through the second sealing layer 21. The material of the second sealing layer 21 includes but is not limited to butyl rubber.

[0079] As shown, Figure 2b and Figure 2c in some embodiments, the second sealing layer 21 can further cover the sandwich structure composed of the conductive adhesive tape 16, the first sub-portion 1511 and the buffer layer 17, which can be achieved by the following way: the second sealing layer 21 has good flowability during the lamination process, thus when the lamination process is performed, it will spread to the edges of the battery 12 and fill the gaps at the edges of the battery 12, so as to increase the sealing effect of the second sealing layer 21 and further relieve the lamination stress suffered by the busbar 15. Here, in the case where the first sealing layer 14 covers the sandwich structure composed of the conductive adhesive tape 16, the first sub-portion 1511 and the buffer layer 17, the second sealing layer 21 can also cover the part of the first sealing layer 14 located at the edges.

[0080] As shown, Figure 3a and Figure 3b in some embodiments, the second sub-portion 152 passes through the second sub-layer 142 and out of the through-hole structure 19.

[0081] in some embodiments, the flowability of the buffer layer 17 is less than that of the second sub-layer 142 at a preset temperature, so that the buffer layer 17 can play a role of setting the shape of the second sub-portion 1512 during the lamination process, further increasing the stress relieving effect thereof.

[0082] As shown, Figure 3b the second sub-portion 152 passes through the second sub-layer 142 and out of the through-hole structure 19.

[0083] Figure 3a and Figure 3b The second sub-layer 142 covers the other sub-cells 13 except the sub-cell 13 located at the edge along the first direction. However, the second sub-layer 142 can also cover the entire cell 12, i.e., can also cover the sandwich structure composed of the conductive adhesive tape 16, the first sub-section 1511 and the buffer layer 17 located at the edge of the cell 12. Here, in the case where the second sub-layer 142 covers the sandwich structure composed of the conductive adhesive tape 16, the first sub-section 1511 and the buffer layer 17, the second sealing layer 21 can also cover the part of the second sub-layer 142 located at the edge.

[0084] The present application will be further described in detail below in conjunction with the specific embodiments, but the embodiments of the present application are not limited thereto.

[0085] Embodiment 1:

[0086] Embodiment 1 corresponds to the present application Figure 2a to Figure 2c The structure shown, the preparation process of embodiment 1 is as follows:

[0087] (1) Etch and clean the transparent conductive glass, and blow dry for standby; prepare a 20 nm thick nickel oxide material as a hole transport layer (first transport layer) on the glass substrate; prepare a perovskite light-absorbing layer (the material of the perovskite light-absorbing layer has a structural formula of Cs 0.05 FA 0.95 PbI3, with a thickness of 500 nm) on the perovskite light-absorbing layer; prepare a 50 nm thick C 60 material as an electron transport layer (second transport layer) on the perovskite light-absorbing layer; prepare a 100 nm thick Cu material as a second electrode layer on the electron transport layer to form a cell 12 on the transparent conductive glass;

[0088] (2) Perform edge cleaning test on the cell 12;

[0089] (3) Set bus bars 15 (copper strips, with a thickness of 0.3 mm) at the anode and cathode of the cell 12, respectively, and set conductive adhesive tapes 16 (material is cloth-based conductive adhesive tape, with a thickness of 0.1 mm) under part of the bus bars 15; set a buffer layer 17 on the bus bars 15, and the material of the buffer layer 17 is a butyl tape with a thickness of 0.5 mm;

[0090] (4) Lay a second sealing layer 21 on the edge of the first substrate 101, and the second sealing layer 21 is located at the four sides of the cell 12; the material of the second sealing layer 21 is butyl rubber;

[0091] (5) lay the first sub-layer 141 on the battery 12, and lay the second sub-layer 142 on the first sub-layer 141; the material of the first sub-layer 141 is POE (the manufacturer is Hangzhou Foster Applied Materials Co., Ltd., and the model is XUR150), and the thickness is 0.3 mm; the material of the second sub-layer 142 is polydimethylsiloxane (the manufacturer is Dow Corning Corporation, and the model is DC184), and the thickness is 0.5 mm;

[0092] (6) cover a hole steel toughened glass (as the second substrate 102) with the same size as the transparent conductive glass on the structure formed in steps (1) to (5), so that the hole steel toughened glass and the transparent conductive glass are as close as possible to avoid the situation of cracking during lamination, and the drainage bar 15 is led out from the hole position, and the drainage bar 15 is laid across the lower part of the battery 12 with an insulating layer;

[0093] (7) put the structure formed in step 6 into a laminator, set the parameters, and complete the lamination operation;

[0094] (8) set a junction box at the hole position of the hole steel toughened glass, and lead the bus bar 15 into the junction box; and coat adhesive on the bottom periphery of the junction box;

[0095] (9) use a glue gun to inject 1:1 mixed silicone gel into the junction box, and after the glue is completely cured, the top cover can be buckled.

[0096] Example 2:

[0097] The difference between Example 2 and Example 1 is that the material of the first sub-layer 141 in Example 2 is EVA (the manufacturer is Hangzhou Foster Applied Materials Co., Ltd., and the model is S806), and the thickness is 0.3 mm.

[0098] Example 3:

[0099] The difference between Example 3 and Example 1 is that the step (3) of Example 3 does not set the conductive tape 16 and the buffer layer 17.

[0100] Example 4:

[0101] The difference between Example 4 and Example 2 is that the step (3) of Example 4 does not set the conductive tape 16 and the buffer layer 17.

[0102] Comparative Example 1:

[0103] The difference between Comparative Example 1 and Example 1 is that Comparative Example 1 does not set the second sub-layer 142, the conductive tape 16 and the buffer layer 17.

[0104] Comparative Example 2:

[0105] The difference between Comparative Example 2 and Example 2 is that Comparative Example 2 does not have the second sub-layer 142, the conductive adhesive tape 16 and the buffer layer 17.

[0106] The performance of the solar cells prepared in the examples and comparative examples was tested to obtain the performance loss of Example 1, Example 2, Comparative Example 1 and Comparative Example 2 after performing the lamination process compared with before performing the lamination process. Here, the performance loss refers to the loss of the power generation of the battery assembly. The specific testing process is as follows: under the irradiation of standard simulated sunlight (AM1.5G, 100 mW / cm 2 ), the performance of the battery assembly before and after performing the lamination process was tested to obtain the I-V curve; according to the I-V curve and the data fed back by the testing equipment, the short-circuit current Jsc(unit: mA / cm 2 ), the open-circuit voltage Voc(unit: V), the maximum light output current Jmpp(unit mA) and the maximum light output voltage Vmpp(unit: V) can be obtained; the power generation P1 of the battery assembly before performing the lamination process and the power generation P2 after performing the lamination process were calculated by the formula P = Jmpp x Vmpp(unit mW); the performance loss of the battery assembly after performing the lamination process was calculated by the formula: performance loss = (P1-P2) / P1*100%. The test results are shown in Table 1:

[0107] Table 1

[0108]

[0109]

[0110] As can be seen from the above table, compared with Comparative Example 1 and Comparative Example 2, the battery assembly manufactured by using the manufacturing method of the present application can significantly reduce the lamination time, the lamination temperature and the performance loss after lamination.

[0111] The above examples are only used to illustrate the technical solutions of the present application, but not limit the same; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the examples of the present application, and they should be covered in the scope of the claims and the description of the present application. Especially, as long as there is no structural conflict, each technical feature mentioned in each example can be combined in any way. The present application is not limited to the specific examples disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A battery assembly, comprising: The battery assembly comprises: a first substrate, a second substrate on the first substrate, and a battery encapsulated between the first substrate and the second substrate; a first sealing layer between the battery and the second substrate and covering at least part of the battery; wherein the first sealing layer comprises a first sub-layer and a second sub-layer on the side of the first sub-layer away from the battery, the materials of the first sub-layer and the second sub-layer are different, and at a preset temperature, the flowability of the second sub-layer is greater than that of the first sub-layer.

2. The battery assembly of claim 1, wherein, The battery assembly further comprises: at least one bus bar, one end of the bus bar being connected with the battery, and the other end being led out from the space formed by the first substrate and the second substrate; the bus bar at least comprises a first sub-portion, the first sub-portion being located between the first substrate and the second substrate and extending in a direction substantially parallel to the plane of the first substrate; a buffer layer between the first substrate and the second substrate and covering at least part of the first sub-portion in the extension direction of the first sub-portion.

3. The battery assembly of claim 2, wherein, The first sub-portion comprises a first sub-segment and a second sub-segment connected with each other, and the buffer layer covers at least the first sub-segment; the battery assembly further comprises: a conductive adhesive tape on the surface of the battery away from the first substrate, and the first sub-segment is sandwiched between the conductive adhesive tape and at least part of the buffer layer.

4. The battery assembly of claim 2, wherein, The first sub-portion comprises a first sub-segment and a second sub-segment connected with each other, and the buffer layer covers at least the second sub-segment, and the second sub-segment and the buffer layer covering the second sub-segment are located between the first sub-layer and the battery; the battery assembly further comprises: an insulating layer on the surface of the battery away from the first substrate, and the second sub-segment is sandwiched between the insulating layer and at least part of the buffer layer.

5. The battery assembly of claim 2, wherein, The first sub-portion comprises a first sub-segment and a second sub-segment connected with each other, and the buffer layer covers at least the second sub-segment, and the second sub-segment and the buffer layer covering the second sub-segment are located between the first sub-layer and the second sub-layer.

6. The battery assembly of any one of claims 2-5, wherein, The hardness of the buffer layer is less than the hardness of the first sub-layer; and / or, at the preset temperature, the flowability of the buffer layer is less than that of the second sub-layer.

7. The battery assembly of any one of claims 1-6, wherein, The battery assembly satisfies one or more of the following conditions: (1) the material of the first sub-layer comprises one or more of polyolefin elastomer, ethylene-vinyl acetate copolymer, polyvinyl butyral ester, thermoplastic polyurethane elastomer, thermoplastic polyolefin, and polyethylene foam; (2) the material of the second sub-layer comprises one or more of solid silicone rubber, liquid silicone rubber, epoxy resin, and polydimethylsiloxane; (3) the thickness of the first sub-layer is between 0.3 mm and 0.5 mm; (4) the thickness of the second sub-layer is between 0.5 mm and 1 mm.

8. The battery assembly of any one of claims 2-6, wherein, The material of the buffer layer comprises one or more of butyl tape, ethylene-propylene-diene rubber tape, ethylene-vinyl acetate copolymer tape, and silicone rubber tape.

9. The battery assembly of any one of claims 1-8, wherein, The battery comprises a light-absorbing layer, which comprises one or more of a perovskite light-absorbing layer, an amorphous silicon light-absorbing layer, a copper-indium-gallium-selenium light-absorbing layer, a cadmium telluride light-absorbing layer, a gallium arsenide light-absorbing layer, and an organic dye light-absorbing layer.

10. The battery assembly of claim 9, wherein, The light-absorbing layer comprises a perovskite light-absorbing layer; the battery further comprises a first electrode layer and a second electrode layer, and the perovskite light-absorbing layer is located between the first electrode layer and the second electrode layer.

11. The battery assembly of claim 10, wherein, The battery further comprises a first transport layer and / or a second transport layer, wherein the first transport layer is located between the first electrode layer and the perovskite light-absorbing layer, the second transport layer is located between the perovskite light-absorbing layer and the second electrode layer, the first transport layer is one of an electron transport layer or a hole transport layer, and the second transport layer is the other of an electron transport layer or a hole transport layer.

12. An electrical device, characterized by The power-consuming device comprises the battery assembly according to any one of claims 1 to 11.

13. A power generation device characterized by comprising: The power-generating device comprises the battery assembly according to any one of claims 1 to 11.

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