Novel semiconductor chip

Abstract

The utility model relates to the field of semiconductor components, in particular to a novel semiconductor chip, and aims to solve the problems that in the prior art, in the using process, a wiring area is unreasonable in design, production cost is increased, chips are distributed unevenly, local overheating is prone to being caused, and the service life of the chips is greatly shortened. The novel semiconductor chip comprises a first substrate, the first substrate is square, four end corners of the first substrate are provided with chamfers, a plurality of rows and columns of chips are uniformly fixed on the surface of the first substrate, a second substrate is bonded on the chips, a gap arranged on the second substrate is matched with the first substrate to form a wiring area, and the wiring area is exposed out of the chips. The chips exposed out of the wiring area are fixed in a horizontal row, and the chips are used for fixedly connecting wires by using tin soldering points; the wiring area is reasonable in design, the production efficiency is improved, the chip is good in heat dissipation, and the product service life is prolonged.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor components, and in particular to a novel semiconductor chip. Background Technology

[0002] Traditional semiconductor chips present numerous inconveniences in wiring operations. On the one hand, the wiring area design of the chips is not reasonable enough, and operators often need to spend a lot of time finding suitable wiring points when performing wiring operations. This is not only inefficient but also prone to wiring errors, increasing production costs and product defect rates. On the other hand, the chip layout is often uneven, which causes uneven heat distribution among the chips and is prone to local overheating. Local overheating not only reduces the chip's operating speed but may also cause chip damage, greatly shortening the chip's lifespan. Therefore, a new type of semiconductor chip is proposed. Utility Model Content

[0003] This utility model addresses the fact that current equipment and existing technologies lack suitable products to solve the aforementioned problems. In practice, unreasonable wiring area design increases production costs, and uneven chip distribution easily leads to localized overheating, significantly shortening chip lifespan. This invention provides a novel semiconductor chip with a rationally designed wiring area, improving production efficiency, providing excellent heat dissipation, and extending product lifespan, effectively solving the problems mentioned in the background section.

[0004] The technical solution adopted by this utility model to solve the above problems is as follows:

[0005] A novel semiconductor chip includes a first substrate and a second substrate, on which chips are respectively disposed. When the first substrate and the second substrate are asymmetrically assembled and bonded, a wiring area is formed. The wiring area is provided with solder joints to fix and connect wires.

[0006] The first substrate has a side length of 20 mm, and the chip is 1.75 mm away from the edge of the first substrate.

[0007] The chip is bonded to the surface of the first substrate.

[0008] The chip is soldered onto the surface of the first substrate.

[0009] The connection area is the region formed by the connection between the notch in the second substrate and the first substrate.

[0010] The notch is concave.

[0011] The notch is convex.

[0012] Compared with the prior art, this utility model has the following advantages:

[0013] By designing a dedicated wiring area, wiring is greatly facilitated for staff, improving wiring efficiency and accuracy. At the same time, it ensures that the chips are evenly distributed on the substrate, guaranteeing uniform heat dissipation and comprehensively improving the performance and reliability of semiconductor chips, meeting the demands of modern electronic devices for high-performance chips. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a novel semiconductor chip according to the first embodiment of this utility model;

[0015] Figure 2 This is a planar schematic diagram of a novel semiconductor first substrate according to the first embodiment of this utility model;

[0016] Figure 3 This is a schematic planar view of a novel semiconductor first substrate according to the second embodiment of this utility model;

[0017] Figure 4 This is a schematic diagram of the plan and dimensions of a novel semiconductor first substrate according to the second embodiment of this utility model;

[0018] Figure 5 This is a schematic diagram of the overall structure of the second substrate in the third embodiment of this utility model;

[0019] Figure 6 This is a schematic diagram of the second substrate notch in the third embodiment of this utility model;

[0020] Figure 7 This is a schematic diagram of the convex notch on the second substrate according to the third embodiment of this utility model;

[0021] Figure 8 This is a schematic diagram of the concave notch of the second substrate in the third embodiment of this utility model;

[0022] The labels in the diagram are as follows: 1. First substrate; 2. Second substrate; 3. Wiring area; 4. Solder joint; 5. Chip; 6. Notch; 7. Wire. Detailed Implementation

[0023] The following are specific embodiments of the present invention, and the technical solution of the present invention will be further described in conjunction with the accompanying drawings. However, the present invention is not limited to these embodiments.

[0024] like Figure 1-8 As shown, this utility model provides a novel semiconductor chip, including a first substrate and a second substrate. The first substrate and the second substrate are respectively provided with chips. When the first substrate and the second substrate are asymmetrically assembled and bonded, a wiring area is formed. The wiring area is provided with solder joints to fix and connect the wires.

[0025] like Figure 1-2As shown, the first substrate 1 of the first embodiment of this utility model is generally square. To meet different application needs, the first substrate 1 can also be circular, fan-shaped, or other shapes. Some specific applications may require a custom-shaped substrate to adapt to special installation requirements or space constraints. Chamfering is applied to its four corners to reduce the possibility of substrate wear and damage, extend the substrate's lifespan, and improve durability. Several rows of chips 5 are fixed to the surface of the first substrate 1 in a uniform arrangement. The overall shape of the second substrate 2 matches that of the first substrate 1, and the chips 5 are fixed to the surface of the second substrate 2. The chip 5 is positioned corresponding to the surface of the first substrate 1; the second substrate 2 has a notch 6. When the first substrate 1 and the second substrate 2 are asymmetrically assembled and bonded, a wiring area can be formed. The notch 6 is designed so that the chip 5 that needs to be wired can be exposed for subsequent wire connection and other operations; in order to facilitate efficient production operations, the chip 5 that needs to be connected to the wire area is distinguished from other chips 5. Specifically, the chip in the wiring area 3 is horizontally fixed on the surface of the first substrate 1, compared to most other chips 5; at the same time, the exposed chip 5 is connected and fixed with the wire 7 that needs to be connected using solder joints 4.

[0026] The first substrate 1 has a side length of 20 mm, and the chip 5 is 1.75 mm away from the edge of the first substrate 1.

[0027] like Figure 3-4 The second embodiment of this utility model is shown. The first substrate 1 has a side length of 20 mm, and the chip 5 is 1.75 mm away from the edge of the first substrate 1. The chips 5 are evenly distributed on the first substrate 1, which can make the heat spread more evenly on the substrate and avoid local overheating. The heat generated by each chip has a relatively independent and balanced heat dissipation space, which prevents the performance of some chips from degrading or being damaged due to uneven heat dissipation. At the same time, it provides a regular space for wiring planning, which makes it easier for engineers to connect the lines according to fixed spacing and pattern, reduce the crossing and tangling of lines, reduce the difficulty of wiring and the probability of errors, and improve production efficiency and product consistency.

[0028] The chip 5 is bonded to the surface of the first substrate 1.

[0029] The chip 5 is soldered onto the surface of the first substrate 1.

[0030] Chip 5 is fixed to the first substrate 1 by bonding or welding, which can ensure a stable connection between chip 5 and the substrate. During the operation of chip 5, it can effectively resist the influence of external forces such as vibration and impact, prevent chip displacement or detachment, and ensure stable chip operation.

[0031] The notch 6 is convex; the notch 6 is concave.

[0032] Furthermore, such as Figure 5-8The second substrate 2 shown is based on the first embodiment and has a notch 6 of a specific shape. The second substrate 2 can be convex or concave, etc., to form the notch 6, and is not limited to this type. Figure 4-8 As shown, this allows for precise exposure of the chip 5 that needs wiring, greatly facilitating wiring operations, reducing the probability of misoperation, and improving production efficiency. On the other hand, it also protects the chip 5 that does not need wiring, reducing the impact of external environmental factors such as dust and moisture on the chip 5, thereby improving the stability and lifespan of the chip 5 and ensuring product performance.

[0033] The specific embodiments described herein are merely illustrative examples illustrating the spirit of this invention. Those skilled in the art to which this invention pertains may make various modifications or additions to the described specific embodiments or use similar methods to replace them, without departing from the spirit of this invention or exceeding the scope defined by the appended claims.

Claims

1. A novel semiconductor chip comprising a first substrate (1) and a second substrate (2), characterized in that: The first substrate (1) and the second substrate (2) are respectively provided with a chip (5), the first substrate (1) and the second substrate (2) are asymmetrically assembled and adhered to form a wiring area (3), the wiring area (3) is provided with a tin soldering point (4) for fixedly connecting a lead wire (7).

2. A novel semiconductor chip as claimed in claim 1, characterized in that: The first substrate (1) has a side length of 20 mm, and the chip (5) is 1.75 mm away from the edge of the first substrate (1).

3. A novel semiconductor chip as claimed in claim 1, wherein: The chip (5) is adhered to the surface of the first substrate (1).

4. A novel semiconductor chip as claimed in claim 1, wherein: The chip (5) is welded to the surface of the first substrate (1).

5. A novel semiconductor chip as described in claim 1, characterized in that: The second substrate (2) can be provided with a notch (6), and the notch (6) is concave.

6. A novel semiconductor chip as claimed in claim 5, characterized in that: The notch (6) is convex.

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