Photonic assembly

Abstract

A photonic component includes an electronic integrated circuit die. A semiconductor device includes a semiconductor substrate, a plurality of semiconductor devices on a horizontal plane of the semiconductor substrate, a plurality of first dielectric material layers burying a plurality of first metal interconnect structures, a dielectric pillar structure extending vertically through each of the first dielectric material layers, and a dielectric layer of a first bonding layer burying a plurality of first metal bonding pads, wherein the first metal bonding pads of the first group have an overlapping region with the dielectric pillar structure in a plan view; and a photonic integrated circuit die including a plurality of waveguides, a plurality of photonic devices, a plurality of second dielectric material layers embedding a plurality of second metal interconnect structures, and a dielectric layer of a second bonding layer embedding a second metal bonding pad bonded to the first metal bonding pad.

Description

TECHNICAL FIELD

[0001] Embodiments of the present utility model relate to a photonic assembly of a photonic integrated circuit die and an electronic integrated circuit die, and particularly relate to a dielectric post structure and a configuration of metal bonding pads. BACKGROUND

[0002] Photonic integrated circuits and electronic integrated circuits are widely used in modern electronic products. Electronic integrated circuits include semiconductor devices formed in semiconductor dies. Photonic integrated circuits include photonic components formed in photonic dies. Photonic integrated circuits rely on light energy, supported by a laser source, to improve integration and speed and reduce heat. Methods of fabricating photonic integrated circuits can employ monolithic photonic integration or hybrid photonic integration. Applications of photonic integrated circuits encompass automotive sensors, healthcare systems, and data communications. Photonic integrated circuits can provide advantages such as energy efficiency, high speed, and integration compatibility with electronic integrated circuits. SUMMARY

[0003] The present disclosure aims to provide a photonic assembly to solve at least one of the above problems.

[0004] A photonic assembly provided by an embodiment of the present disclosure includes: an electronic integrated circuit die including a semiconductor substrate, a plurality of semiconductor devices on a surface of the semiconductor substrate, a plurality of first dielectric material layers embedding a plurality of first metal interconnect structures, a dielectric post structure vertically extending through each of the first dielectric material layers, and a dielectric layer having a first bonding layer with a plurality of first metal bonding pads formed therein, wherein a first set of the first metal bonding pads has an overlapping area with the dielectric post structure in a plan view; and a photonic integrated circuit die including a plurality of waveguides, a plurality of photonic devices, a plurality of second dielectric material layers embedding a plurality of second metal interconnect structures, and a dielectric layer having a second bonding layer with a plurality of second metal bonding pads formed therein, wherein the second metal bonding pads are bonded to the first metal bonding pads.

[0005] According to one embodiment of the present disclosure, the plurality of second metal bonding pads are bonded to the plurality of first metal bonding pads via metal-to-metal bonding, wherein the plurality of second metal bonding pads directly contact the plurality of first metal bonding pads.

[0006] According to one embodiment of the present disclosure, the electronic integrated circuit die further includes a dielectric protection liner laterally surrounding the dielectric post structure and contacting each of the plurality of first dielectric material layers.

[0007] According to one embodiment of the present disclosure, the electronic integrated circuit die further includes a semiconductor lens including a portion of the semiconductor substrate, having a convex semiconductor surface, and located between the dielectric post structure and the semiconductor substrate.

[0008] According to one of the embodiments of the present disclosure, the dielectric protective liner contacts the convex semiconductor surface of the semiconductor lens and the vertically extending sidewall of the semiconductor substrate.

[0009] According to one of the embodiments of the present disclosure, the dielectric protective liner contacts the convex semiconductor surface of the semiconductor lens and the vertically extending sidewall of the semiconductor substrate.

[0010] According to one of the embodiments of the present disclosure, the dielectric protective liner contacts the convex semiconductor surface of the semiconductor lens and the vertically extending sidewall of the semiconductor substrate.

[0011] According to one of the embodiments of the present disclosure, the dielectric protective liner contacts the convex semiconductor surface of the semiconductor lens and the vertically extending sidewall of the semiconductor substrate.

[0012] According to one of the embodiments of the present disclosure, the dielectric protective liner contacts the convex semiconductor surface of the semiconductor lens and the vertically extending sidewall of the semiconductor substrate.

[0013] According to one of the embodiments of the present disclosure, the dielectric protective liner contacts the convex semiconductor surface of the semiconductor lens and the vertically extending sidewall of the semiconductor substrate. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 Figure 1 is a vertical sectional view of a first intermediate embodiment structure for forming an electronic integrated circuit die in the first embodiment of the present application.

[0015] Figure 2A Figure 2 is a vertical sectional view of the first intermediate embodiment structure after forming a via cavity in the first embodiment of the present application.

[0016] Figure 2B Figure 3 is a top view of the first intermediate embodiment structure of Figure 2A , while the tangent line A-A' corresponds to the tangent plane of the vertical section of Figure 2A .

[0017] Figure 3 Figure 4 is a vertical sectional view of the first intermediate embodiment structure after forming a semiconductor lens in the first embodiment of the present application.

[0018] Figure 4 Figure 5 is a vertical sectional view of the first intermediate embodiment structure after forming a dielectric protective liner in the first embodiment of the present application.

[0019] Figure 5 Figure 6 is a vertical sectional view of the first intermediate embodiment structure after forming a dielectric pillar structure in the via cavity in the first embodiment of the present application.

[0020] Figure 6 Figure 7 is a vertical sectional view of the first intermediate embodiment structure after forming a dielectric layer of a first bonding layer, a cavity, and an integrated pad and a via cavity in the first embodiment of the present application.

[0021] Figure 7A Figure 8 is a vertical sectional view of the first intermediate embodiment structure after forming a first metal bonding pad in the first embodiment of the present application.

[0022] Figure 7B Figure 9 is a top view of the first intermediate embodiment structure of Figure 7A , while the tangent line A-A' corresponds to the tangent plane of the vertical section of Figure 7A .

[0023] Figure 7C Figure 10 is a top view of other settings of the first intermediate embodiment structure of Figure 7A , while the tangent line A-A' corresponds to the tangent plane of the vertical section of Figure 7A .

[0024] Figure 8 Figure 11 is a vertical sectional view of a photonic integrated circuit die in the first embodiment of the present application.

[0025] Figure 9The vertical sectional view of the first intermediate embodiment structure after the semiconductor lens is formed in the second embodiment of the utility model.

[0026] Figure 10 The vertical sectional view of the first intermediate embodiment structure after the semiconductor lens is formed in the second embodiment of the utility model.

[0027] Figure 11 The vertical sectional view of the first intermediate embodiment structure after the semiconductor lens is formed in the second embodiment of the utility model.

[0028] Figure 12 The vertical sectional view of the second intermediate embodiment structure for forming the semiconductor lens after forming the dielectric layer of the lower side passivation layer in the second embodiment of the utility model.

[0029] Figure 13A The vertical sectional view of the second intermediate embodiment structure after forming the via hole cavity in the second embodiment of the utility model.

[0030] Figure 13B The vertical sectional view of the second intermediate embodiment structure after forming the via hole cavity in the second embodiment of the utility model. Figure 13A The vertical sectional view of the second intermediate embodiment structure after forming the via hole cavity in the second embodiment of the utility model. Figure 13A The vertical sectional view of the second intermediate embodiment structure after forming the via hole cavity in the second embodiment of the utility model.

[0031] Figure 14 The vertical sectional view of the second intermediate embodiment structure after forming the via hole cavity in the second embodiment of the utility model.

[0032] Figure 15 The vertical sectional view of the second intermediate embodiment structure after forming the via hole cavity in the second embodiment of the utility model.

[0033] Figure 16 The vertical sectional view of the second intermediate embodiment structure after forming the via hole cavity in the second embodiment of the utility model.

[0034] Figure 17A The vertical sectional view of the second intermediate embodiment structure after forming the via hole cavity in the second embodiment of the utility model.

[0035] Figure 17B The vertical sectional view of the second intermediate embodiment structure after forming the via hole cavity in the second embodiment of the utility model. Figure 17A The vertical sectional view of the second intermediate embodiment structure after forming the via hole cavity in the second embodiment of the utility model. Figure 17A The vertical sectional view of the second intermediate embodiment structure after forming the via hole cavity in the second embodiment of the utility model.

[0036] Figure 18The vertical sectional view of the second intermediate embodiment structure after forming the first metal bonding pad in the second embodiment of the utility model.

[0037] Figure 19A The vertical sectional view of the second intermediate embodiment structure after forming the first metal bonding pad in the second embodiment of the utility model.

[0038] Figure 19B For Figure 19A The top view of the second intermediate embodiment structure, and the tangent A-A' corresponds to the tangent surface of the vertical sectional view. Figure 19A

[0039] Figure 19C For Figure 19A The top view of the second intermediate embodiment structure, and the tangent A-A' corresponds to the tangent surface of the vertical sectional view. Figure 19A

[0040] Figure 20 The vertical sectional view of the photonic integrated circuit die in the second embodiment of the utility model.

[0041] Figure 21 The vertical sectional view of the second intermediate embodiment structure after forming the bonding assembly containing the photonic integrated circuit die and the electronic integrated circuit die in the second embodiment of the utility model.

[0042] Figure 22 The vertical sectional view of the second intermediate embodiment structure after attaching the fiber access unit and the packaging substrate to the composite die in the second embodiment of the utility model.

[0043] Figure 23 The vertical sectional view of the second intermediate embodiment structure after attaching the packaging substrate to the printed circuit board in the second embodiment of the utility model.

[0044] Figure 24 The flow chart of the general process steps for forming the photonic assembly in the embodiment of the utility model.

[0045] The reference signs are as follows:

[0046] A-A': tangent

[0047] OPR: optical path region

[0048] t1: first thickness

[0049] t2: second thickness

[0050] 99: vertical optical path

[0051] 99A: first optical path​​

[0052] 99B: second optical path

[0053] 100: printed circuit board

[0054] 110: printed circuit board substrate

[0055] 120: fiber access unit

[0056] 150: optical fiber

[0057] 180: printed circuit board bond pad

[0058] 190: solder joint

[0059] 200: package substrate

[0060] 210: core substrate

[0061] 214: through-core via structure

[0062] 240: board-side surface area layer circuitry

[0063] 242: board-side insulating layer

[0064] 244: board-side wiring interconnects

[0065] 248: board-side bond pad

[0066] 260: chip-side surface area layer circuitry

[0067] 262: chip-side insulating layer

[0068] 264: chip-side wiring interconnects

[0069] 268: substrate bond pad

[0070] 292: board-to-substrate underfill material portion

[0071] 490: solder material portion

[0072] 492: die package underfill material portion

[0073] 600: electronic integrated circuit die

[0074] 610: semiconductor substrate

[0075] 614: semiconductor lens

[0076] 620: semiconductor device

[0077] 631: via cavity

[0078] 632: dielectric protective liner

[0079] 634: dielectric post structure

[0080] 660: first dielectric material layer

[0081] 670: dielectric layer of passivation layer

[0082] 672: dielectric layer of first passivation layer

[0083] 674: dielectric layer of second passivation layer

[0084] 676: dielectric layer of third passivation layer

[0085] 678: etch stop dielectric layer

[0086] 680: first metal interconnect structure

[0087] 690: dielectric layer of first bonding layer

[0088] 695: via hole portion

[0089] 696: first bonding via

[0090] 697: pad hole

[0091] 697A: pad layer hole

[0092] 697B: integrated pad and via hole

[0093] 698: first metal bonding pad

[0094] 698A: first group

[0095] 698B: second group

[0096] 700: photonic integrated circuit die

[0097] 718: substrate side bonding pad

[0098] 720: photonic device

[0099] 740: waveguide

[0100] 750: optical deflector

[0101] 760: second dielectric material layer

[0102] 780: second metal interconnect structure

[0103] 782: substrate side metal interconnect structure

[0104] 784: interconnect via structure

[0105] 786: electronic integrated circuit die side metal interconnect structure

[0106] 790: dielectric layer of second bonding layer

[0107] 798: second metal bonding pad

[0108] 800: composite die

[0109] 2410, 2420, 2430, 2440, 2450, 2460, 2470: steps DETAILED DESCRIPTION

[0110] The following detailed description can be read in connection with the accompanying drawings to assist in a full understanding of the various aspects of the application. It is noted that the various structures can be drawn to scale in the drawings for the purpose of simplification and clarity. Indeed, the dimensions of the various structures can be arbitrarily increased or decreased for the sake of clarity.

[0111] The following detailed description provides different embodiments or examples of the application. The described embodiments and examples are provided as a single illustration of the application only, and are not intended to limit the scope of the application. For example, while the statements above and below form first members on second members include embodiments in which the first and second members are in direct contact, they also include embodiments in which additional members are disposed between the first and second members. Moreover, numerous instances of like reference numerals can be repeated elsewhere in the detailed description and in the drawings for the purpose of simplicity and clarity. However, elements having the same reference numerals can not necessarily be identical with one another, but can include like components that can have different dimensions or other slight differences from one another.

[0112] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of describing one element's or feature's relation to another element or feature as illustrated in the figures. The spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices or apparatuses can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can be interpreted accordingly. Like reference numerals can refer to like elements throughout the description and the drawings, unless otherwise indicated. A description of functions or operations of a device or system can be provided herein in terms of performing certain actions or providing certain functionality, which can be described herein in the context of a method or other function. The actions and functionality can be implemented within one or more devices or apparatuses by one or more components of the one or more devices or apparatuses processing information as it moves through the one or more devices or apparatuses. For example, the one or more components can process information to generate output information or to

[0113] A compact universal photonic engine (COUPE) includes a combination of photonic integrated circuits and electronic integrated circuits that provide optoelectronic transport. The COUPE can handle optical signals using an electronic signal transport system. The COUPE integrates various optical components, electro-optical conversion devices, and optical fibers. In the optoelectronic device, a laser plays an important role. The optical fiber can be used to transmit the laser to the COUPE.

[0114] Various embodiments disclosed herein can provide a photonic assembly including a photonic integrated circuit die and an electronic integrated circuit die, where the electronic integrated circuit die includes a dielectric pillar structure in an optical path. Metal bonding pads in the electronic integrated circuit die can be configured such that a first set of metal bonding pads is formed in a peripheral region of the dielectric pillar structure (a region that laterally surrounds a region of the optical path) and a second set of metal bonding pads is formed outside the region of the dielectric pillar structure. The first set of metal bonding pads is configured around the optical path region to avoid blocking the optical path through the electronic integrated circuit die. The first set of metal bonding pads provides additional bonding between a set of metal bonding pads in the photonic integrated circuit die to increase the bonding strength between the electronic integrated circuit die and the photonic integrated circuit die. Various embodiments of the present disclosure will be described with reference to the drawings.

[0115] Figure 1 The first intermediate embodiment structure shown can be used to form an electronic integrated circuit die. The first embodiment structure can include a semiconductor substrate 610, which can be a portion of a semiconductor wafer such as a commercially available silicon wafer having a diameter of 150 mm, 200 mm, 300 mm, or 450 mm. In one embodiment, a two-dimensional periodic array of electronic integrated circuit dies can be formed on the semiconductor wafer using the process steps described herein in sequence. The portion of the first embodiment structure corresponds to a unit region of a two-dimensional array of unit regions used to form the two-dimensional periodic array of electronic integrated circuit dies.

[0116] A semiconductor device 620 can be formed on the semiconductor substrate 610 in each unit region of the first embodiment structure. The semiconductor device 620 can include any group of semiconductor devices known in the art for use in forming an electronic integrated circuit. For example, the semiconductor device 620 can include a field effect transistor, a diode, a resistor, a capacitor, an inductor, or a variety of other types of semiconductor devices that can be formed on a semiconductor substrate.

[0117] A first metal interconnect structure 680 formed in a first dielectric material layer 660 can be formed on the semiconductor device 620 and the semiconductor substrate 610. The first dielectric material layers 660 each include an interlayer dielectric material such as an undoped silicate glass, a doped silicate glass, an organosilicate glass, a nitrided material, silicon oxynitride, silicon carbonitride, a dielectric metal oxide, or the like. The first dielectric material layers 660 can also be considered dielectric layers of an electronic integrated circuit interconnect level. The first metal interconnect structure 680 can also be considered an electronic integrated circuit metal interconnect structure.

[0118] The first metal interconnect structure 680 includes multiple layers of first metal lines and first metal via structures located on the first dielectric material layer 660. The first metal interconnect structure 680 may include tungsten, copper, or aluminum. Other suitable metal materials are also within the scope of this embodiment. The formation method of each of the first metal interconnect structures 680 may be a single damascene method, a double damascene method, or depositing metal material and using a photolithographically patterned etching mask (such as a patterned photoresist layer) and an anisotropic etching process to pattern the metal material. The total number of metal line layers in the first metal interconnect structure 680 may be 1 to 20, but a greater number of metal line layers may also be used. In some embodiments, the top layer of the first metal interconnect structure 680 may include an aluminum-based metal pad. Regions without any first metal interconnect structures 680 may be formed in each unit region of the structure of the first embodiment. This region may then be used to form optical paths.

[0119] The dielectric layer 670 of the passivation layer may be formed on the first dielectric material layer 660. The dielectric layer 670 of the passivation layer may include at least one dielectric diffusion barrier layer, which can block the diffusion of hydrogen, moisture, and metallic impurities. In the example described, the dielectric layer 670 of the passivation layer may include a dielectric layer 672 containing a first passivation layer of silicon oxide, a dielectric layer 674 containing a second passivation layer of a dielectric diffusion barrier material such as silicon nitride or silicon carbonitride, and a dielectric layer 676 containing a third passivation layer of second silicon oxide. The thickness of the dielectric layer 672 of the first passivation layer may be from 50 nm to 500 nm, but may also be smaller or larger. The thickness of the dielectric layer 674 of the second passivation layer may be from 50 nm to 500 nm, but may also be smaller or larger. The thickness of the dielectric layer 676 of the third passivation layer may be from 50 nm to 1000 nm, but may also be smaller or larger.

[0120] like Figure 2A and Figure 2B As shown, photoresist (not shown) can be applied to the dielectric layer 670 of the passivation layer, and the photoresist can be photolithographically patterned to form openings in areas in the plan view that do not have the first metal interconnect structure 680. The plan view referred to herein is an illustration of all elements in the structure projected vertically onto a horizontal plane. In the first embodiment structure, the vertical direction refers to the direction perpendicular to the upper surface of the semiconductor substrate 610, and the horizontal plane refers to any plane parallel to the vertical direction. The openings in the photoresist layer are large enough to accommodate optical paths subsequently formed in the electronic integrated circuit die. For example, the diameter of the openings in the photoresist layer can be from 100 micrometers to 600 micrometers, such as 200 micrometers to 400 micrometers, but smaller or larger diameters can also be used.

[0121] An anisotropic etch process can be performed to transfer the pattern of openings in the photoresist layer through the dielectric layer 670 of the passivation layer and the first dielectric material layer 660, and optionally into the upper portion of the semiconductor substrate 610. The via cavity 631 can be through the dielectric layer 670 of the passivation layer and the first dielectric material layer 660, and optionally into the upper portion of the semiconductor substrate 610. The via cavity 631 can have a circular or substantially circular horizontal cross-sectional area. The via cavity 631 can have a cylindrical vertically extending flat sidewall that extends from the semiconductor substrate 610 to the topmost surface of the dielectric layer 670 of the passivation layer. The bottom of the via cavity 631 can physically expose the recessed horizontal surface and the cylindrical vertically extending surface of the semiconductor substrate 610. The photoresist can then be removed, and the removal method can be ashing.

[0122] As shown in FIG. 6B, the physically exposed portion of the semiconductor substrate 610 can be patterned to form a semiconductor lens 614. The semiconductor lens 614 can be a focusing lens that can reduce the beam width of light passing through the semiconductor lens 614. In one embodiment, the semiconductor lens 614 can have a convex semiconductor surface with the center of the convex semiconductor surface being the highest point and the periphery of the convex semiconductor surface being the lowest point. Figure 3

[0123] The method of forming the semiconductor lens 614 can be any semiconductor lens patterning method known in the art. For example, a gray-tone photoresist layer (not shown) can be applied into the via cavity 631 and over the dielectric layer 670 of the passivation layer, and the gray-tone photoresist layer can be photo-patterned to form photoresist material portions having variable thickness profiles. An anisotropic etch process can be performed that is selective to etching the material of the semiconductor substrate 610 relative to the dielectric material of the third dielectric layer 676 to form the semiconductor lens 614. It should be understood that the figures are generally not shown to scale, and the diameter of the via cavity 631 can be at least 3 times and / or at least 10 times or more than the depth of the via cavity 631. It is therefore possible to form a suitable patterned gray-tone photoresist material portion in the via cavity 631. Other patterning methods can also be employed to form the semiconductor lens 614.

[0124] In general, the method of forming the semiconductor lens 614 can be to pattern a portion of the semiconductor substrate 610 under the via cavity 631. The semiconductor lens 614 can comprise a portion of the semiconductor substrate 610, can have a convex semiconductor surface, and can be formed at the bottom of the via cavity 631. The diameter of the semiconductor lens 614 can be 20% to 95%, such as 30% to 90%, of the diameter of the via cavity 631. The height of the semiconductor lens 614 can be 100 nm to 10,000 nm, although smaller or larger heights can also be employed.

[0125] As shown in FIG. 6B, the physically exposed portion of the semiconductor substrate 610 can be patterned to form a semiconductor lens 614. The semiconductor lens 614 can be a focusing lens that can reduce the beam width of light passing through the semiconductor lens 614. In one embodiment, the semiconductor lens 614 can have a convex semiconductor surface with the center of the convex semiconductor surface being the highest point and the periphery of the convex semiconductor surface being the lowest point. Figure 4 ​As shown, a dielectric protective pad 632 can be compliantly deposited on the physically exposed surfaces of the semiconductor lens 614, the first dielectric material layer 660, and the dielectric layer 670 of the passivation layer. The dielectric protective pad 632 comprises at least one dielectric material such as silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, at least one dielectric metal oxide, or a combination thereof. Other suitable dielectric materials are also within the scope of this embodiment. The deposition method of the dielectric protective pad 632 can be a compliant deposition process such as chemical vapor deposition or atomic layer deposition. The thickness of the dielectric protective pad 632 can be from 10 nm to 1000 nm, but smaller or larger thicknesses are also possible.

[0126] The dielectric protective pad 632 contacts each of the first dielectric material layer 660, the protruding semiconductor surface of the semiconductor lens 614, and the vertically extending sidewalls of the semiconductor substrate 610. The dielectric protective pad 632 includes a cylindrical vertically extending portion that contacts each of the first dielectric material layer 660 and the vertically extending sidewalls of the semiconductor substrate 610. The dielectric protective pad 632 also includes a horizontally extending portion that contacts the upper surface of the topmost layer of the passivation dielectric layer 670. The bottom profile of the dielectric protective pad 632 has a recessed lower surface that contacts the protruding upper surface of the semiconductor lens 614. The thickness of the dielectric protective pad 632 is chosen to avoid constructive interference of reflected light generated by the lower and upper surfaces of the bottom profile of the dielectric protective pad 632, thereby minimizing reflections at the interface between the dielectric protective pad 632 and the semiconductor lens 614.

[0127] like Figure 5 As shown, dielectric filler material can be deposited in the remaining space of the via cavity 631. The dielectric filler material may include a planarizable transparent dielectric material such as silicon oxide or a polymer material. A planarization process can be performed to remove excess portion of the dielectric filler material on a horizontal plane of the topmost horizontal surface of the horizontal extension of the dielectric protective pad 632 on the dielectric layer 670 containing the passivation layer. The planarization process may include a chemical mechanical planarization process. The retained portion of the dielectric filler material in the via cavity 631 may form a dielectric pillar structure 634. The upper surface of the dielectric pillar structure 634 may lie in a horizontal plane of the upper surface of the horizontal extension containing the dielectric protective pad 632. A first optical path 99A passes through the central portion of the dielectric pillar structure 634, the semiconductor lens 614, and the lower portion of the semiconductor substrate 610.

[0128] like Figure 6As shown, a dielectric material can be deposited on the horizontally extending portions of the dielectric protective liner 632 and the dielectric pillar structures 634 to form a dielectric layer 690 of the first bonding layer. The dielectric material of the dielectric layer 690 of the first bonding layer can include an undoped silicate glass or a doped silicate glass, for example. The thickness of the dielectric layer 690 of the first bonding layer can be from 10 nm to 5 microns, although lesser or greater thicknesses can also be employed. The dielectric layer 690 of the first bonding layer can contact the horizontally extending portions of the dielectric protective liner 632 and can also contact the upper surfaces of the dielectric pillar structures 634.

[0129] A first photoresist layer (not shown) can be applied on the dielectric layer 690 of the first bonding layer and can be photo-patterned to form a pattern of separate openings on a set of the first metal interconnect structures 680 at the topmost level of the first metal interconnect structures 680. A first anisotropic etching process can be performed to form separate via openings through the dielectric layer 690 of the first bonding layer and the horizontally extending portions of the dielectric protective liner 632, and optionally through one or more of the dielectric layers 670 of the passivation layers. The first photoresist layer can then be removed, and the removal method can be ashing.

[0130] A second photoresist layer (not shown) can be applied on the dielectric layer 690 of the first bonding layer and can be photo-patterned to form a pattern of separate openings with a pattern of bonding pads. In one embodiment of the present application, a first set of the separate openings can be formed in the area enclosed by the sidewalls of the via voids 631 (now filled with portions of the dielectric pillar structures 634 and the dielectric protective liner 632) in a plan view, i.e., in the area defined by the outer sidewalls of the vertically extending portions of the dielectric protective liner 632 in a plan view. In addition, a central region of the area defined by the sidewalls of the via voids 631 does not have any openings in the second photoresist layer in a plan view, so that the openings in the second photoresist layer do not have any overlapping area with the first optical path 99A. A second set of the separate openings can be formed outside the area enclosed by the sidewalls of the via voids 631 in a plan view, so that each of the second set of the separate openings encloses an area of an individual via opening through the dielectric layer 690 of the first bonding layer.

[0131] A second anisotropic etching process can be performed to transfer the pattern of openings in the second photoresist layer through the dielectric layer 690 of the first bonding layer. Pad-shaped voids through the dielectric layer 690 of the first bonding layer under the separate openings in the second photoresist layer and the pre-existing via openings (through the dielectric layer 690 of the first bonding layer, the dielectric protective liner 632, and optionally through one or more of the dielectric layers 670 of the passivation layers) and can vertically extend through all of the dielectric layers 670 of the passivation layers to the upper surfaces of the individual first metal interconnect structures 680 at the topmost level of the first metal interconnect structures 680.

[0132] A pad cavity 697A passes through the dielectric layer 690 of the first bonding layer beneath the first group of separate openings in the second photoresist layer, while an integrated pad and via cavity 697B passes through the dielectric layer 690 of the first bonding layer beneath the second group of separate openings in the second photoresist layer. The pad cavity 697A and the integrated pad and via cavity 697B can be considered together as a pad cavity 697. In one embodiment, the pad cavity 697A may extend vertically into the upper portion of the dielectric pillar structure 634. The integrated pad and via cavity 697B may include a pad cavity portion and a via cavity portion 695, the pad cavity portion passing through the dielectric layer 690 of the first bonding layer, and the via cavity portion 695 extending vertically through the dielectric layer 670 of the dielectric protective pad 632 and the passivation layer. In one embodiment, the chemical agent in the second anisotropic etching process is selective for the material of the dielectric protective pad 632, and the depth of each pad cavity portion can be the same as the thickness of the dielectric layer 690 of the first bonding layer. The second photoresist layer can then be removed, and the removal method can be ashing.

[0133] Although the present invention is described using a through-hole priority dual patterning process that forms the through-hole opening before forming the pad cavity, the embodiments described herein also consider forming the pad cavity before forming the through-hole opening.

[0134] like Figure 7A , Figure 7B and Figure 7C As shown, at least one metal filler material can be deposited in the pad void 697 and the via void portion 695, and then the metal filler material is planarized to form a first metal bonding pad 698 and a first bonding via 696. For example, a metal barrier pad and / or a metal adhesion pad can be deposited by physical vapor deposition or chemical vapor deposition, followed by a metal seed layer deposited by physical vapor deposition. The metal barrier pad and / or the metal adhesion pad may include metal barrier materials such as titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium, tantalum, or the like. Other suitable metal materials are also within the scope of this embodiment. The metal seed layer may include copper. Metal filler material for metal-to-metal bonding can then be deposited in the remaining volume of the pad void 697 and the via void portion 695. In the example described, an electroplating process can be performed to deposit a metal filler material such as copper in the remaining volume of the pad void 697 and the via void portion 695. A planarization process, such as chemical mechanical polishing, can be performed to remove at least one portion of the metal filler material from a horizontal plane on the upper surface of the dielectric layer 690 containing the first bonding layer. The retained portion of the at least one metal filler material includes the first metal bonding pad 698.

[0135] The first metal bond pads 698 can include a first type of metal bond pad and a second type of metal bond pad. The first type of metal bond pad can fill the pad layer voids 697A, and the second type of metal bond pad can fill the integrated pad and via voids 697B. The first type of metal bond pad can be collectively considered as a first set 698A of first metal bond pads 698, and the second type of metal bond pad can be collectively considered as a second set 698B of first metal bond pads 698.

[0136] In one embodiment of the present application, the first metal bond pads 698 of the first set 698A have an overlap region with the dielectric post structures 634 in a plan view (e.g., a top view), and the first metal bond pads 698 of the second set 698B are formed outside the region of the dielectric post structures 634 in the plan view. In other words, the first metal bond pads 698 of the first set 698A are formed in a region that overlaps the dielectric post structures 634 in the plan view. In one embodiment, all of the first metal bond pads 698 of the first set 698A are located in a region defined by the inner sidewalls of the vertically extending portions of the dielectric protection liner 632, and the vertically extending portions extend through the first dielectric material layer 660 in the plan view. In one embodiment, the first metal bond pads 698 of the first set 698A do not have any region that overlaps the vertically extending portions of the dielectric protection liner 632. Thus, the first metal bond pads 698 of the first set 698A do not directly contact the horizontally extending portions of the dielectric protection liner 632, and do not contact any other portions of the dielectric protection liner 632. Figure 7B

[0137] The first metal bond pads 698 of the second set 698B each have no overlap region with the dielectric post structures 634 in the plan view. The first metal bond pads 698 of the second set 698B can be formed completely outside the region of the via holes 631. In one embodiment, the first metal bond pads 698 of the second set 698B can contact the horizontally extending portions of the dielectric protection liner 632.

[0138] As shown in FIGS. 6A and 6B, the optical path region OPR does not have any first metal bond pads 698 formed on the central portions of the dielectric post structures 634. In one embodiment, the radius of the optical path region OPR is greater than the nearest neighbor distance of the first metal bond pads 698 of the second set 698B. In one embodiment, the optical path region OPR has an overlap region with the semiconductor lens 614 in the plan view. In one embodiment, all of the regions of the semiconductor lens 614 can be located in the region of the optical path region OPR. In general, the first metal bond pads 698 can have a rectangular shape (as shown in FIG. 6A), a circular shape (as shown in FIG. 6B), or other two-dimensional closed shape in the plan view. Figure 7B Figure 7C As shown in FIGS. 6A and 6B, the optical path region OPR does not have any first metal bond pads 698 formed on the central portions of the dielectric post structures 634. In one embodiment, the radius of the optical path region OPR is greater than the nearest neighbor distance of the first metal bond pads 698 of the second set 698B. In one embodiment, the optical path region OPR has an overlap region with the semiconductor lens 614 in the plan view. In one embodiment, all of the regions of the semiconductor lens 614 can be located in the region of the optical path region OPR. In general, the first metal bond pads 698 can have a rectangular shape (as shown in FIG. 6A), a circular shape (as shown in FIG. 6B), or other two-dimensional closed shape in the plan view. Figure 7B Figure 7C As shown in FIGS. 6A and 6B, the optical path region OPR does not have any first metal bond pads 698 formed on the central portions of the dielectric post structures 634. In one embodiment, the radius of the optical path region OPR is greater than the nearest neighbor distance of the first metal bond pads 698 of the second set 698B. In one embodiment, the optical path region OPR has an overlap region with the semiconductor lens 614 in the plan view. In one embodiment, all of the regions of the semiconductor lens 614 can be located in the region of the optical path region OPR. In general, the first metal bond pads 698 can have a rectangular shape (as shown in FIG. 6A), a circular shape (as shown in FIG. 6B), or other two-dimensional closed shape in the plan view. ​​​

[0139] In one embodiment, the first metal bonding pads 698 of the first group 698A each have a first thickness t1 that is greater than a thickness of the dielectric layer 690 of the first bonding layer, and each include an individual portion that protrudes into the dielectric pillar structure 634. The depth of the protrusion can be 100 nm to 1000 nm, but smaller or larger protrusion depths can also be employed. The first metal bonding pads 698 of the second group 698B each include a pad portion and a via portion. The pad portion has a second thickness t2 that is less than the first thickness t1, and the via portion extends through the dielectric protection liner 632. In one embodiment, the second thickness t2 can be the same as the thickness of the dielectric layer 690 of the first bonding layer.

[0140] An electronic integrated circuit die 600 is formed in each of the unit regions of the first embodiment structure, where the semiconductor substrate 610 in each of the unit regions is a portion of a semiconductor wafer. A two-dimensional periodic array of electronic integrated circuit dies 600 can be formed. The electronic integrated circuit die 600 each includes the semiconductor substrate 610, the semiconductor lens 614 (including a portion of the semiconductor substrate 610 and a convex semiconductor surface), the semiconductor device 620 on a horizontal surface of the semiconductor substrate 610, the first dielectric material layer 660 to bury the first metal interconnect structure 680, the dielectric pillar structure 634 vertically extending through each of the layers of the first dielectric material layer 660 and having an area that overlaps the semiconductor lens 614 in a plan view, and the dielectric layer 690 of the first bonding layer to bury the first metal bonding pads 698. The first metal bonding pads 698 of the first group 698A have an area that overlaps the dielectric pillar structure 634 in a plan view.

[0141] Figure 8 A photonic integrated circuit die 700 is shown. In some embodiments, a two-dimensional periodic array of photonic integrated circuit dies 700 can be located on a carrier wafer (not shown). In this embodiment, Figure 8 The photonic integrated circuit die 700 shown can be located in a unit region in a two-dimensional periodic array of photonic integrated circuit dies 700. The two-dimensional periodic array of photonic integrated circuit dies 700 can have the same period as the two-dimensional periodic array of electronic integrated circuit dies 600 described above.

[0142] The photonic integrated circuit die 700 can include a variety of photonic devices 720 known in the art; an optical deflector 750 configured to change the direction of a light beam between a vertical direction and a horizontal direction along the second optical path 99B; waveguides 740 providing optical paths to and from optical junctions of the variety of photonic devices 720 and including horizontal beam paths for light beams impinging on or emanating from the optical deflector 750; and a second metal interconnect structure 780 configured to provide electrical signals to a variety of electrical junctions of the photonic devices 720. The photonic devices 720 can include optical switches, optical memory devices, and / or other devices that can generate, modulate, and / or receive optical signals.

[0143] The optical deflector 750 can include a device that changes the direction of a light beam from a horizontal direction to a vertical direction, or vice versa. The optical deflector 750 can be adjacent to a set of waveguides 740 and can be configured to change the direction of light between a horizontal direction through the set of waveguides 740 and a vertical direction through the second dielectric material layer 760. In one embodiment, the optical deflector 750 can include an in-die mirror that is tilted 45 degrees with respect to the vertical direction. The in-die mirror can include a reflective layer stack configured to maximize reflection at a 45 degree angle of incidence. In another embodiment, the optical deflector 750 can include a grating coupler that can be optically connected to at least one waveguide 740 via evanescent coupling at the end of the grating coupler. In one embodiment, the grating coupler includes an optical grating having a period along the horizontal direction and can include a periodic pattern of alternating transparent and non-transparent sections. The period of the periodic pattern can be selected to maximize optical coupling of light at the wavelength of the optical signal propagating through the waveguide 740. As light contacts the grating of the grating coupler from the vertical direction, the light is scattered. The grating dimensions can be selected such that light constructively interferes only in the direction of the waveguide 740. The same principle can be used for light exiting the waveguide 740 and impinging on the grating coupler such that constructive interference occurs only in the vertical direction, e.g., the direction of light exit.

[0144] The waveguides 740 include a high refractive index material to confine photons therein. For example, the waveguides 740 can include silicon nitride or silicon. The lateral dimensions and thickness of the waveguides 740 can be selected to maximize total internal reflection.

[0145] The second metal interconnect structure 780 can be formed in the second dielectric material layer 760. The second metal interconnect structure 780 can include substrate side metal interconnect structures 782 on one side of the waveguides 740, electronic integrated circuit die side metal interconnect structures 786 on the other side of the waveguides 740, and interconnect via structures 784 extending vertically through the layers of photonic devices 720 and waveguides 740 and providing electrical connections between the substrate side metal interconnect structures 782 and the electronic integrated circuit die side metal interconnect structures 786.

[0146] The dielectric layer 790 of the second bonding layer has a second metal bonding pad 798 formed therein, and may be formed on one side of the electronic integrated circuit die-side metal interconnect structure 786. The second metal bonding pad 798 is electrically connected to the electronic integrated circuit die-side metal interconnect structure 786, and its configuration pattern may be a mirror image of the first metal bonding pad 698 of the electronic integrated circuit die 600. A substrate-side bonding pad 718 may be provided to be electrically connected to the substrate-side metal interconnect structure 782, and the substrate-side bonding pad 718 may have a physically exposed bonding surface. The pattern of the substrate-side bonding pad 718 may be a mirror image of the bonding pad on the package substrate, and the photonic integrated circuit die may then be bonded to the bonding pad on the package substrate.

[0147] like Figure 9 As shown, it can be joined Figure 8 Photonic integrated circuit die 700 to Figure 7C Electronic integrated circuit (IC) dies 600 are used to form composite dies 800. In embodiments where photonic IC dies 700 are located within a two-dimensional array of photonic IC dies 700 and electronic IC dies 600 are located within a two-dimensional array of electronic IC dies 600, wafer-to-wafer bonding can be performed to bond the two-dimensional array of photonic IC dies 700 to the two-dimensional array of electronic IC dies 600. The carrier wafer used for the photonic IC die 700 can then be separated (if used). Each composite die 800 comprises a bonded assembly of the photonic IC die 700 and the electronic IC die 600. The method of bonding the photonic IC die 700 to the individual electronic IC die 600 can be to bond a second metal bonding pad 798 to a first metal bonding pad 698, and the bonding method can be metal-to-metal bonding, such as copper-to-copper bonding. After metal-to-metal bonding, the second metal bonding pad 798 directly contacts the first metal bonding pad 698.

[0148] In one embodiment, the photonic integrated circuit die 700 and the electronic integrated circuit die 600 can be brought into contact with each other such that the second metal bonding pads 798 each contact an individual first metal bonding pad 698. An anneal process can be performed with heating and pressing the electronic integrated circuit die 600 and the photonic integrated circuit die 700 towards each other. In this anneal process, the average size of the metal grains in the first metal bonding pads 698 and the second metal bonding pads 798 can grow such that a set of grain boundaries grow and cross the level of contact of the first metal bonding pads 698 and the second metal bonding pads 798. Each pair of first metal bonding pads 698 and second metal bonding pads 798 forms a continuous metal grain that can provide adhesion strength to each other and provide a metal-to-metal bond between the first metal bonding pads 698 and the second metal bonding pads 798. In one embodiment, the first metal bonding pads 698 and the second metal bonding pads 798 can comprise copper pads and the metal-to-metal bond can be a copper-to-copper bond.

[0149] In addition, the surface of the dielectric layer 790 of the second bonding layer can be bonded to the surface of the dielectric layer 690 of the first bonding layer via a dielectric-to-dielectric bond such that the photonic integrated circuit die 700 is bonded to the electronic integrated circuit die 600 via a hybrid bond. The heating can be to 200°C to 400°C, but lower or higher temperatures can also be used. The anneal process with heating can be for 30 minutes to 360 minutes, but less or more time can also be used.

[0150] In general, the second metal bonding pads 798 can be bonded to the first metal bonding pads 698 via a metal-to-metal bond in which the second metal bonding pads 798 directly contact the first metal bonding pads 698. The photonic integrated circuit die 700 and the electronic integrated circuit die 600 can be aligned to each other such that light impinging on or emanating from the optical deflector 750 can pass through the dielectric post structure 634, the semiconductor lens 614, and a portion of the semiconductor substrate 610 that has an overlap region with the dielectric post structure 634 in a plan view. A vertical optical path 99 can be formed between the optical deflector 750 and the physically exposed distal surface of the semiconductor substrate 610.

[0151] The semiconductor substrate 610 can be thinned as appropriate to an optical thickness and the thinning method can be grinding, polishing, a non-isotropic etching process, and / or an isotropic etching process. The thickness of the thinned semiconductor substrate 610 can be 5 microns to 300 microns, but smaller or larger thicknesses can also be used.

[0152] As Figure 10As shown, the composite die 800 can be bonded to a package substrate 200. The package substrate 200 can be a core package substrate containing a core substrate 210, or a coreless package substrate that does not contain a package core. The package substrate 200 can instead comprise a System-on-integrated packaging substrate (SoIS) containing a redistribution layer, an interlayer dielectric layer, and / or at least one embedded interposer (e.g., a silicon interposer). Such a System-on-integrated packaging substrate can include layer-to-layer interconnects using substrate side solder material portions, micro-bumps, underfill material portions (e.g., molded underfill material portions), and / or adhesive films. While the present embodiments are described with respect to a core package substrate, it is to be understood that the scope of the present embodiments is not limited to any particular type of substrate package. For example, a System-on-integrated packaging substrate can be used in place of a core package substrate. In some embodiments that use a System-on-integrated packaging substrate, the core substrate 210 can comprise a glass epoxy board containing an array of through-board holes. The array of through-core via structures 214 includes metal material in the through-board holes. The through-core via structures 214 can or can not each include a cylindrical hollow therein. Dielectric liners (not shown) can optionally be used to electrically isolate the through-core via structures 214 from the core substrate 210.

[0153] The package substrate 200 can include a board side surface area layer circuit 240 and a chip side surface area layer circuit 260. The board side surface area layer circuit can include a board side insulating layer 242 having board side wiring interconnects 244 formed therein. The chip side surface area layer circuit 260 can include a chip side insulating layer 262 having chip side wiring interconnects 264 formed therein. The board side insulating layer 242 and the chip side insulating layer 262 can comprise a photosensitive epoxy material that can be photo-patterned and cured. The board side wiring interconnects 244 and the chip side wiring interconnects 264 can comprise copper that can be deposited by electroplating into patterns in the board side insulating layer 242 or the chip side insulating layer 262.

[0154] In one embodiment, the chip-side surface area layer circuit 260 includes chip-side wiring interconnects 264 connected to an array of substrate bond pads 268. The array of substrate bond pads 268 can be configured for connection via controlled collapse chip connection solder ball bonding. The board-side surface area layer circuit 240 includes board-side wiring interconnects 244 connected to an array of board-side bond pads 248. The array of board-side bond pads 248 is configured to accommodate solder joints of a size larger than the size of the controlled collapse chip connection solder balls. While the present embodiment is described with reference to the package substrate 200 including both the chip-side surface area layer circuit 260 and the board-side surface area layer circuit 240, one of the chip-side surface area layer circuit 260 and the board-side surface area layer circuit 240 can be omitted or replaced by an array of bond structures such as micro-bumps. In such a case, the chip-side surface area layer circuit 260 can be replaced by an array of micro-bumps or any other array of bond structures.

[0155] In one embodiment, the package substrate 200 includes a first horizontal surface to face the composite die 800. In a subsequent assembly process, the first horizontal surface faces the composite die 800 with its substrate-facing horizontal surface. The package substrate 200 also includes a second horizontal surface opposite the first horizontal surface. The substrate bond pads 268 of the package substrate 200 can be located on the first horizontal surface of the package substrate 200 and can be mirror images of the pattern of the substrate-side bond pads 718.

[0156] In particular, the solder material portions 490 can each be bonded to an individual substrate bond pad 268 and an individual substrate-side bond pad 718. A reflow process can be performed to reflow the solder material portions 490, and thus each of the solder material portions 490 is bonded to an individual substrate bond pad 268 and an individual substrate-side bond pad 718.

[0157] An underfill material can be applied to the gap between the composite die 800 and the package substrate 200. The underfill material can include any underfill material known in the art. An underfill material portion can be formed around the array of substrate-side bond pads 718, the array of substrate bond pads 268, and the array of solder material portions 490 in the gap between the composite die 800 and the package substrate 200. The underfill material portion is formed around the composite die 800 and the package substrate 200, and thus can be considered a die package underfill material portion 492.

[0158] The fiber access unit 120 can be attached to the upper surface of the semiconductor substrate 610, and the attachment method can employ optical glue (not shown). The fiber access unit 120 described herein refers to any external device that can optically couple the optical fiber 150 to an optical path such as the vertical optical path 99.

[0159] As Figure 11As shown, a printed circuit board 100 may be provided, comprising a printed circuit board substrate 110 and printed circuit board bonding pads 180. The printed circuit board 100 includes printed circuitry (not shown) on at least one side of the printed circuit board substrate 110. An array of solder contacts 190 may be formed to bond an array of board-side bonding pads 248 to the array of printed circuit board bonding pads 180. The solder contacts 190 may be formed by applying an array of solder balls between the array of board-side bonding pads 248 and the array of printed circuit board bonding pads 180, and allowing the array of solder balls to reflow. Additional underfill portions, such as board-to-substrate underfill portions 292, may be formed around the solder contacts 190, and may be formed by applying and shaping the underfill material. A package substrate 200 may be attached to the printed circuit board 100 via the array of solder contacts 190.

[0160] Figure 12 This is the second embodiment structure used to form an electronic integrated circuit die in the second intermediate embodiment of the present invention. The second embodiment structure can be derived from... Figure 1 The first intermediate embodiment structure shown omits, for example, the dielectric layer 676 of the third passivation layer. The dielectric layer 672 of the first passivation layer and the dielectric layer 674 of the second passivation layer can be considered together as the dielectric layer (672, 674) of the lower passivation layer.

[0161] like Figure 13A and Figure 13B As shown, they can be combined. Figure 2A and 2B The described process steps form a via 631 that penetrates the dielectric layer 670 of the passivation layer and the first dielectric material layer 660, and extends into the upper portion of the semiconductor substrate 610. The via 631 may have a circular or substantially circular horizontal cross-sectional area. The via 631 may have cylindrical, vertically extending, flat sidewalls that extend from the semiconductor substrate 610 to the top surface of the dielectric layer 670 of the passivation layer. The bottom of the via 631 may physically expose the recessed horizontal surface and the cylindrical, vertically extending surface of the semiconductor substrate 610. Generally, the structural characteristics of the via 631 may be the same as the corresponding unit in the first intermediate embodiment, except that the dielectric layer 676 of the third passivation layer in this process step is not present in the structure of the second intermediate embodiment.

[0162] like Figure 14 As shown, it can be performed Figure 3 The process steps shown are used to form a semiconductor lens 614 under the via 631. The structural characteristics of the semiconductor lens 614 may be the same as those of the corresponding unit in the first embodiment.

[0163] like Figure 15 As shown, it can be performed Figure 4The process steps shown are performed to form a dielectric protection liner 632. The dielectric protection liner 632 contacts the first dielectric material layers 660, the convex semiconductor surface of the semiconductor lens 614, and the vertically extending sidewalls of the semiconductor substrate 610. The dielectric protection liner 632 includes a cylindrical vertically extending portion and a horizontally extending portion. The cylindrical vertically extending portion contacts each of the first dielectric material layers 660 and the vertically extending sidewalls of the semiconductor substrate 610, while the horizontally extending portion contacts the upper surface of the dielectric layer 670 of the topmost passivation layer. The dielectric protection liner 632 includes a bottom profile having a concave lower surface that contacts the convex upper surface of the semiconductor lens 614. The thickness of the dielectric protection liner 632 is selected to avoid constructive interference of reflected light from the upper and lower surfaces of the profile portion of the dielectric protection liner 632 to minimize reflection at the interface of the dielectric protection liner 632 and the semiconductor lens 614. One of the dielectric layers (672, 674) of the passivation layer of the dielectric layer 670 of the passivation layer is located between the first dielectric material layer 660 and the horizontally extending portion of the dielectric protection liner 632.

[0164] As shown in FIG. 6A, the process steps shown are performed to form a dielectric pillar structure 634 in the via cavity 631. The upper surface of the dielectric pillar structure 634 can be located in a horizontal plane that contains the upper surface of the horizontally extending portion of the dielectric protection liner 632. The first optical path 99A passes through a central portion of the dielectric pillar structure 634, the semiconductor lens 614, and the lower portion of the semiconductor substrate 610. Figure 16 Figure 5 As shown in FIG. 6B, the process steps shown are performed to form a third passivation layer dielectric layer 676 and an etch stop dielectric layer 678 on the dielectric protection liner 632 and the dielectric pillar structure 634. The material composition and thickness of the third passivation layer dielectric layer 676 can be the same as the corresponding elements in the first embodiment structure. The etch stop dielectric layer 678 includes a dielectric material that has an etch resistance that is greater than the etch resistance of the dielectric material of the second bonding layer dielectric layer that is subsequently formed. The etch stop dielectric layer 678 can include silicon nitride, silicon oxynitride, silicon carbon nitride, a dielectric metal oxide, or a combination thereof. The thickness of the etch stop dielectric layer 678 can be in the range of 10 nm to 1000 nm, although lesser or greater thicknesses can also be employed. The third passivation layer dielectric layer 676 and the etch stop dielectric layer 678 can be considered here as upper passivation layer dielectric layers. The first passivation layer dielectric layer 672, the second passivation layer dielectric layer 674, the third passivation layer dielectric layer 676, and the etch stop dielectric layer 678 can be collectively considered as the passivation layer dielectric layer 670.

[0165] As shown in FIG. 6B, the process steps shown are performed to form a dielectric pillar structure 634 in the via cavity 631. The upper surface of the dielectric pillar structure 634 can be located in a horizontal plane that contains the upper surface of the horizontally extending portion of the dielectric protection liner 632. The first optical path 99A passes through a central portion of the dielectric pillar structure 634, the semiconductor lens 614, and the lower portion of the semiconductor substrate 610. Figure 17A Figure 17B As shown in FIG. 6B, the process steps shown are performed to form a third passivation layer dielectric layer 676 and an etch stop dielectric layer 678 on the dielectric protection liner 632 and the dielectric pillar structure 634. The material composition and thickness of the third passivation layer dielectric layer 676 can be the same as the corresponding elements in the first embodiment structure. The etch stop dielectric layer 678 includes a dielectric material that has an etch resistance that is greater than the etch resistance of the dielectric material of the second bonding layer dielectric layer that is subsequently formed. The etch stop dielectric layer 678 can include silicon nitride, silicon oxynitride, silicon carbon nitride, a dielectric metal oxide, or a combination thereof. The thickness of the etch stop dielectric layer 678 can be in the range of 10 nm to 1000 nm, although lesser or greater thicknesses can also be employed. The third passivation layer dielectric layer 676 and the etch stop dielectric layer 678 can be considered here as upper passivation layer dielectric layers. The first passivation layer dielectric layer 672, the second passivation layer dielectric layer 674, the third passivation layer dielectric layer 676, and the etch stop dielectric layer 678 can be collectively considered as the passivation layer dielectric layer 670.

[0166] ​​A photoresist layer (not shown) can be applied over the etch stop dielectric layer 678, and the photoresist layer can be photo-patterned to form openings in the optical path region OPR. A non-isotropic etching process can be performed to remove a portion of the etch stop dielectric layer 678 under the openings in the photoresist layer. The openings in the etch stop dielectric layer 678 define the area of the optical path region OPR. The photoresist layer can then be removed, and the removal method can be ashing. In one embodiment, the optical path region OPR has an overlapping area with the semiconductor lens 614 in a plan view. In one embodiment, all areas of the semiconductor lens 614 can be located in the area of the optical path region OPR.

[0167] As shown in FIG. 6A, a dielectric material can be deposited over the etch stop dielectric layer 678 to form a dielectric layer 690 of a first bonding layer. The dielectric material can be used for dielectric-to-dielectric bonding of the dielectric layer 690 of the first bonding layer. For example, the dielectric material of the dielectric layer 690 of the first bonding layer can include undoped silicate glass or doped silicate glass. The thickness of the dielectric layer 690 of the first bonding layer can be 10 nm to 5 microns, although smaller or larger thicknesses can also be employed. The dielectric layer 690 of the first bonding layer can be vertically separated from the horizontally extending portions of the dielectric protection liner 632 (and the dielectric pillar structures 634) by the dielectric layer 676 of the third passivation layer and the etch stop dielectric layer 678. Figure 18 A first photoresist layer (not shown) can be applied over the dielectric layer 690 of the first bonding layer, and the first photoresist layer can be photo-patterned to form a separate pattern of openings over a set of the first metal interconnect structures 680 (which are located in the topmost first metal interconnect structures 680). A first non-isotropic etching process can be performed to form separate via openings through the dielectric layer 690 of the first bonding layer and the etch stop dielectric layer 678, and optionally into one or more of the dielectric layer 676 of the third passivation layer, the horizontally extending portions of the dielectric protection liner 632, the dielectric layer 674 of the second passivation layer, and the dielectric layer 672 of the first passivation layer. The first photoresist layer can then be removed, and the removal method can be ashing.

[0168]

[0169] ​A second photoresist layer (not shown) can be applied on the dielectric layer 690 of the first bonding layer, and the second photoresist layer can be photo-patterned to form separate openings with a pattern of bonding pads. In one embodiment of the present application, a first set of separate openings has an overlapping area with the sidewall of the via cavity 631 (now the portion of the dielectric pillar structure 634 and the dielectric protection liner 632) in a plan view, i.e., an overlapping area with the outside sidewall of the vertically extended portion of the dielectric protection liner 632 in a plan view. In addition, the center region of the area defined by the sidewall of the via cavity 631 in a plan view does not have any opening in the second photoresist layer, so that the openings in the second photoresist layer do not have any overlapping area with the first optical path 99A. A second set of separate openings can be formed outside the area enclosed by the sidewall of the via cavity 631 in a plan view, so that each of the second set of separate openings encloses an individual via opening through the dielectric layer 690 of the first bonding layer.

[0170] A second isotropic etching process can be performed to transfer the photoresist pattern in the second photoresist layer through the dielectric layer 690 of the first bonding layer. Pad-shaped cavities are formed through the dielectric layer 690 of the first bonding layer under the separate openings in the second photoresist layer. The previously existing via openings through the dielectric layer 690 of the first bonding layer and the etch stop dielectric layer 678, and optionally through the dielectric layer 676 of the third passivation layer, the dielectric protection liner 632, and the dielectric layer 674 of the second passivation layer, can vertically extend through all the dielectric layers 670 of the passivation layers to the top surface of the individual first metal interconnect structures 680 of the topmost layer of the first metal interconnect structures 680.

[0171] Pad layer cavities 697A can be formed through the dielectric layer 690 of the first bonding layer under the first set of separate openings in the second photoresist layer, and integrated pad and via cavities 697B can be formed through the dielectric layer 690 of the first bonding layer under the second set of separate openings in the second photoresist layer. The pad layer cavities 697A and the integrated pad and via cavities 697B can be collectively regarded as pad cavities 697. The etch stop dielectric layer 678 can act as an etch stop structure during the second anisotropic etching process. Thus each of the pad cavities 697 includes a lower surface which is a physically exposed upper surface portion of the etch stop dielectric layer 678. The integrated pad and via cavities 697B can include a pad cavity portion and a via cavity portion 695, the pad cavity portion through the dielectric layer 690 of the first bonding layer, and the via cavity portion 695 vertically extending through each of the dielectric layers 670 of the passivation layers. In one embodiment, the depth of each pad cavity portion can be the same as the thickness of the dielectric layer 690 of the first bonding layer. The second photoresist layer can then be removed, and the removal method can be ashing.

[0172] Although the embodiments of this utility model are described using a through-hole priority dual patterning process that forms through-hole openings before forming through-hole openings, the embodiments described here also take into account forming through-hole openings before forming through-hole openings.

[0173] like Figure 19A , Figure 19B and Figure 19C As shown, at least one metal filler material can be deposited in the pad void 697 and the via void portion 695, and then the metal filler material is planarized to form a first metal bonding pad 698 and a first bonding via 696. For example, a metal barrier pad and / or a metal adhesive pad can be deposited, and the deposition method can be physical vapor deposition or chemical vapor deposition. Next, a metal seed layer can be deposited, and the deposition method can be physical vapor deposition. The metal barrier pad and / or the metal adhesive pad may include metal barrier materials such as titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium, tantalum, or the like. Other suitable metal materials are also within the scope of this embodiment. The metal seed layer may include copper. Then, a metal filler material for metal-to-metal bonding can be deposited in the remaining volume of the pad void 697 and the via void portion 695. In the example described, an electroplating process can be performed to deposit a metal filler material such as copper in the remaining volume of the pad void 697 and the via void portion 695. A planarization process, such as chemical mechanical polishing, can be performed to remove at least one portion of the metal filler material from a horizontal plane on the upper surface of the dielectric layer 690 containing the first bonding layer. The retained portion of the at least one metal filler material may include the first metal bonding pad 698 and the first bonding via 696.

[0174] The first metal bonding pad 698 may include a first group 698A and a second group 698B of first metal bonding pads 698. The first group 698A of first metal bonding pads 698 fills the pad layer voids 697A, while the second group 698B of first metal bonding pads 698 fills the integrated pads and through-hole voids 697B. Generally, the first metal bonding pad 698 in the plan view may be... Figure 19B The rectangle shown Figure 19C The circle or other two-dimensional closed shape shown.

[0175] In one embodiment of this utility model, the first metal bonding pad 698 of the first group 698A is shown in a plan view (e.g.) Figure 19B or Figure 19CThe first metal bonding pads 698 of the first group 698A each have an individual perimeter that has an overlap region with the dielectric column structure 634 in plan view. In one embodiment, at least one of the first metal bonding pads 698 of the first group 698A has an individual perimeter that has an overlap region with the vertically extending portion of the dielectric protection liner 632 that extends vertically through the first dielectric material layer 660 in plan view. In some embodiments, at least one of the metal bonding pads 698 of the first group 698A is entirely within the area of the dielectric column structure 634 in plan view and does not have any overlap region with the vertically extending portion of the dielectric protection liner 632 that extends vertically through the first dielectric material layer 660 in plan view. The first metal bonding pads 698 can each have an individual perimeter that has an overlap region with the etch stop dielectric layer 678. In one embodiment, all of the first metal bonding pads 698 can be formed outside of the optical path region OPR.

[0176] The first metal bonding pads 698 of the second group 698B each have an individual perimeter that does not have any overlap region with the dielectric column structure 634 in plan view. The first metal bonding pads 698 of the second group 698B can be entirely formed outside of the via void 631. In one embodiment, the first metal bonding pads 698 of the second group 698B can contact the horizontally extending portion of the dielectric protection liner 632.

[0177] The optical path region OPR does not have any of the first metal bonding pads 698 and is located on a central portion of the dielectric column structure 634. In one embodiment, the optical path region OPR has a radius that is greater than a nearest neighbor distance of the first metal bonding pads of the second group 698B. In one embodiment, the optical path region OPR has an overlap region with the semiconductor lens 614 in plan view. In one embodiment, all of the area of the semiconductor lens 614 can be located within the area of the optical path region OPR.

[0178] In one embodiment, the first metal bonding pads 698 can each have a same thickness that is not less than a thickness of the first bonding layer dielectric layer 690 on the etch stop dielectric layer 678. The first metal bonding pads 698 selected from the first metal bonding pads 698 each include an individual lower surface to contact an upper surface of the etch stop dielectric layer 678. The first bonding layer dielectric layer 690 contacts the etch stop dielectric layer 678 and is vertically separated from the dielectric protection liner 632.

[0179] An electronic integrated circuit die 600 can be formed in each of the unit regions of the first embodiment structure, where the semiconductor substrates 610 in the unit regions are each a portion of a semiconductor wafer. A two-dimensional periodic array of electronic integrated circuit dies 600 can be formed. The electronic integrated circuit die 600 includes the semiconductor substrate 610; a semiconductor lens 614 including a portion of the semiconductor substrate 610 and having a convex semiconductor surface; a semiconductor device 620 on a horizontal surface of the semiconductor substrate 610; a first dielectric material layer 660 embedding a first metal interconnect structure 680; a dielectric pillar structure 634 extending vertically through each of the layers of the first dielectric material layer 660 and having an overlap region with the semiconductor lens in a plan view; and a dielectric layer 690 of a first bonding layer embedding a first metal bonding pad 698. The first metal bonding pads 698 of a first set 698A have an overlap region with the dielectric pillar structure 634 in a plan view.

[0180] As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided. Figure 20 As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided. Figure 20 The photonic integrated circuit die 700 of FIG. 1 1 1 can be derived from the photonic integrated circuit die 700 of FIG. 1 1 0, with the difference that the pattern of the second metal bonding pads 798 is adjusted to be a mirror image of the pattern of the first metal bonding pads 698 of the electronic integrated circuit die 600 shown in FIG. 1 0. Figure 8 The photonic integrated circuit die 700 of FIG. 1 1 1 can be derived from the photonic integrated circuit die 700 of FIG. 1 1 0, with the difference that the pattern of the second metal bonding pads 798 is adjusted to be a mirror image of the pattern of the first metal bonding pads 698 of the electronic integrated circuit die 600 shown in FIG. 1 0. Figure 19A The photonic integrated circuit die 700 of FIG. 1 1 1 can be derived from the photonic integrated circuit die 700 of FIG. 1 1 0, with the difference that the pattern of the second metal bonding pads 798 is adjusted to be a mirror image of the pattern of the first metal bonding pads 698 of the electronic integrated circuit die 600 shown in FIG. 1 0. 19B The photonic integrated circuit die 700 of FIG. 1 1 1 can be derived from the photonic integrated circuit die 700 of FIG. 1 1 0, with the difference that the pattern of the second metal bonding pads 798 is adjusted to be a mirror image of the pattern of the first metal bonding pads 698 of the electronic integrated circuit die 600 shown in FIG. 1 0.

[0181] As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided. Figure 21 As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided. Figure 9 As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided. Figure 20 As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided. Figure 19A As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided. Figure 19B As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided.

[0182] As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided. Figure 22 As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided. Figure 10 As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided.

[0183] As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided. Figure 23 As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided. Figure 11 As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided.

[0184] Figure 24 As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided.

[0185] As shown in FIG. 1 1 1, a photonic integrated circuit die 700 of a second embodiment of the present application can be provided. Figure 1 Figure 12 ​As shown in step 2420 and

[0186] As shown in step 2430 and Figure 1 , Figure 12 As shown in step 2440 and

[0187] As shown in step 2450 and Figure 2A , Figure 2B , Figure 13A and Figure 13B As shown in step 2460 and

[0188] As shown in step 2470 and Figure 3 and Figure 14 As shown in step 2480 and

[0189] As shown in step 2490 and Figure 4 , Figure 5 , Figure 15 and Figure 16 As shown in step 2500 and

[0190] As shown in step 2510 and Figure 6 and Figure 18 As shown in step 2520 and

[0191] As shown in step 2530 and Figure 7A , Figure 7B , Figure 19A and Figure 19B As shown in step 2540 and

[0192] In some embodiments, the above method further comprises providing a photonic integrated circuit die including a plurality of waveguides, a plurality of photonic devices, a plurality of second dielectric material layers to bury a plurality of second metal interconnect structures, a second bonding layer of dielectric layers to bury a plurality of second metal bonding pads; and bonding the second metal bonding pads to the first metal bonding pads to attach the photonic integrated circuit die to the electronic integrated circuit die.

[0193] In some embodiments, the photonic integrated circuit die in the above method includes an optical deflector adjacent to a set of waveguides and configured to change a direction of movement of light between a horizontal direction through the set of waveguides and a vertical direction through the second dielectric material layer; and the photonic integrated circuit die and the electronic integrated circuit die are aligned to each other such that light impinging on or emanating from the optical deflector passes through the dielectric pillar structure, the semiconductor lens, and a portion of the semiconductor substrate that overlaps the dielectric pillar structure in a plan view.

[0194] In some embodiments, the second metal bonding pad is bonded to the first metal bonding pad via a metal-to-metal bond, wherein the second metal bonding pad directly contacts the first metal bonding pad.

[0195] In some embodiments, the first metal bonding pads of the second set are formed outside of a region of the dielectric pillar structure in a plan view; an optical path region, free of any first bonding metal pads formed on a central portion of the dielectric pillar structure, such that a radius of the optical path region is greater than a nearest neighbor distance of the first metal bonding pads of the second set; and the optical path region has an overlapping region with the semiconductor lens in a plan view.

[0196] In accordance with all of the drawings and various embodiments of the present application, a photonic assembly is provided, including: an electronic integrated circuit die 600 including a semiconductor substrate 610, a plurality of semiconductor devices 620 on a horizontal surface of the semiconductor substrate 610, a plurality of first dielectric material layers 660 embedding a plurality of first metal interconnect structures 680, a dielectric pillar structure 634 extending vertically through each of the first dielectric material layers 660, and a dielectric layer 690 having a first bonding layer with a plurality of first metal bonding pads 698 formed therein, wherein a first set 698A of the first metal bonding pads 698 has an overlapping region with the dielectric pillar structure 634 in a plan view; and a photonic integrated circuit die 700 including a plurality of waveguides 740, a plurality of photonic devices 720, a plurality of second dielectric material layers 760 embedding a plurality of second metal interconnect structures 780, and a dielectric layer 790 having a second bonding layer with a plurality of second metal bonding pads 798 formed therein, wherein the second metal bonding pads 798 are bonded to the first metal bonding pads 698.

[0197] In an embodiment, the second metal bonding pads 798 are bonded to the first metal bonding pads 698 via metal-to-metal bonding, where the second metal bonding pads 798 directly contact the first metal bonding pads 698. In an embodiment, the electronic integrated circuit die 600 further includes a dielectric protection liner 632 laterally surrounding the dielectric pillar structure 634 and contacting each of the first dielectric material layers 660. In an embodiment, the electronic integrated circuit die 600 further includes a semiconductor lens 614 including a portion of the semiconductor substrate 610, having a convex semiconductor surface, and located between the dielectric pillar structure 634 and the semiconductor substrate 610. In an embodiment, the dielectric protection liner 632 contacts the convex semiconductor surface of the semiconductor lens 614 and the vertically extending sidewalls of the semiconductor substrate 610.

[0198] In an embodiment, the electronic integrated circuit die 600 includes a dielectric layer 670 of a passivation layer located between the first dielectric material layer 660 and the dielectric layer 690 of the first bonding layer; and a first of the dielectric layer 670 of a passivation layer located between the first dielectric material layer 660 and the horizontally extending portion of the dielectric protection liner 632. In an embodiment, the dielectric layer 690 of the first bonding layer contacts the horizontally extending portion of the dielectric protection liner 632.

[0199] In an embodiment, the first metal bonding pads 698 of the first set 698A do not directly contact the horizontally extending portion of the dielectric protection liner 632; and the first metal bonding pads 698 of the second set 698B have no area of overlap with the dielectric pillar structure 634 in plan view and contact the horizontally extending portion of the dielectric protection liner 632.

[0200] In an embodiment, a second of the dielectric layer 670 of a passivation layer includes an etch stop dielectric layer 678 located between the horizontally extending portion of the dielectric protection liner 632 and the dielectric layer 690 of the first bonding layer; and the first metal bonding pads 698 each include an individual lower surface to contact an upper surface of the etch stop dielectric layer 678. In some embodiments, the dielectric layer 690 of the first bonding layer contacts the etch stop dielectric layer 678 and is vertically separated from the dielectric protection liner 632.

[0201] Another embodiment provides a photonic assembly, comprising: an electronic integrated circuit die 600 including a semiconductor substrate 610; a semiconductor lens 614 including a portion of the semiconductor substrate 610 and having a convex semiconductor surface; a plurality of semiconductor devices 620 located on a horizontal surface of the semiconductor substrate 610; a plurality of first dielectric material layers 660 having a plurality of first metal interconnect structures 680 formed therein; a dielectric pillar structure 634 extending vertically through each of the first dielectric material layers 660 and having an overlapping area with the semiconductor lens 614 in a plan view; and a first bonding layer of dielectric layers 690 having a plurality of first metal bonding pads 698 formed therein, wherein a first set 698A of the first metal bonding pads 698 has an overlapping area with the dielectric pillar structure 634 in a plan view; and a photonic integrated circuit die 700 including a plurality of waveguides 740; a plurality of photonic devices 720; a plurality of second dielectric material layers 760 to embed a plurality of second metal interconnect structures 780; and a second bonding layer of dielectric layers 790 having a plurality of second metal bonding pads 798 formed therein, wherein the second metal bonding pads 798 are bonded to the first metal bonding pads 698.

[0202] In some embodiments, the electronic integrated circuit die 600 includes a dielectric protection liner 632 to laterally surround the dielectric pillar structure 634 and contact each of the first dielectric material layers 660; the electronic integrated circuit die 600 includes a plurality of passivation layers of dielectric layers 670 between the first dielectric material layers 660 and the first bonding layer of dielectric layers 690; and a first one of the passivation layers of dielectric layers 670 is between the first dielectric material layers 660 and a horizontally extending portion of the dielectric protection liner 632. In an embodiment, all of the first set of the first metal bonding pads 698 are within an area defined by an inner sidewall of a vertically extending portion of the dielectric protection liner 632 that vertically extends through the first dielectric material layers 660 in a plan view.

[0203] In an embodiment, the first set 698A of the first metal bonding pads 698 each have a first thickness t1 that is greater than a thickness of the first bonding layer of dielectric layers 690 and each include a respective portion to protrude into the dielectric pillar structure 634; and the second set 698B of the first metal bonding pads 698 each have no overlapping area with the dielectric pillar structure 634 in a plan view and each include a pad portion and a via portion, the pad portion having a second thickness that is less than the first thickness, and the via portion extending through the dielectric protection liner 632. In an embodiment, at least one of the first set 698A of the first metal bonding pads 698 has an overlapping area with a vertically extending portion of the dielectric protection liner 632 that vertically extends through the first dielectric material layers 660 in a plan view.

[0204] The various embodiments of the present application can be used to provide metal bonding pads in the peripheral region of the dielectric post structure 634, which includes the vertical optical path 99 without blocking the light beam. By providing metal bonding pads in the peripheral region of the dielectric post structure 634, the bonding strength between the electronic integrated circuit die 600 and the photonic integrated circuit die 700 can be increased, and the structural reliability of the hybrid die 800 can be improved.

[0205] The structures of the above-described embodiments are beneficial for those skilled in the art to understand the embodiments of the present application. The term "comprising" in each embodiment inherently discloses additional embodiments in which the term "comprising" is replaced with "consisting essentially of" or "consisting of", unless otherwise explicitly stated. Whenever two or more elements are listed in the same or different paragraphs, a Markush group is implied. Whenever the present application uses the term "comprising", the term "comprising" is used in the sense where it is open-ended, and the compositions, methods, and apparatuses disclosed herein can consist of more than what is listed. Whenever the present application uses the term "comprising", it is also intended that the application can also consist only of the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of more than the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of only the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of more than the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of only the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of more than the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of only the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of more than the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of only the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of more than the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of only the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of more than the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of only the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of more than the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of only the listed elements. Whenever the present application uses the term "comprising", it is also intended that the application can also consist of more than the listed elements.

Claims

1. A photonic assembly, comprising: An electronic integrated circuit die including a semiconductor substrate, a plurality of semiconductor devices on a surface of the semiconductor substrate, a plurality of first dielectric material layers embedding a plurality of first metal interconnect structures, a dielectric pillar structure vertically extending through each of the plurality of first dielectric material layers, and a first bonding layer of dielectric layers having a plurality of first metal bonding pads formed therein, wherein a first set of the plurality of first metal bonding pads has an overlap area with the dielectric pillar structure in a plan view; and A photonic integrated circuit die including a plurality of waveguides, a plurality of photonic devices, a plurality of second dielectric material layers embedding a plurality of second metal interconnect structures, and a second bonding layer of dielectric layers having a plurality of second metal bonding pads formed therein, wherein the plurality of second metal bonding pads are bonded to the plurality of first metal bonding pads. The plurality of second metal bonding pads are bonded to the plurality of first metal bonding pads via metal-to-metal bonding, wherein the plurality of second metal bonding pads directly contact the plurality of first metal bonding pads.

2. The photonic assembly of claim 1, wherein, The electronic integrated circuit die further includes a dielectric protection liner laterally surrounding the dielectric pillar structure and contacting each of the plurality of first dielectric material layers.

3. The photonic assembly of claim 1, wherein, The electronic integrated circuit die further includes a semiconductor lens including a portion of the semiconductor substrate, having a convex semiconductor surface, and located between the dielectric pillar structure and the semiconductor substrate.

4. The photonic assembly of claim 3, wherein, The dielectric protection liner contacts the convex semiconductor surface of the semiconductor lens and a vertically extending sidewall of the semiconductor substrate.

5. The photonic assembly of claim 4, wherein, An electronic integrated circuit die including a semiconductor substrate; 6. A photonic assembly, comprising: A semiconductor lens including a portion of the semiconductor substrate and having a convex semiconductor surface; A plurality of semiconductor devices on a surface of the semiconductor substrate; a plurality of first dielectric material layers embedding a plurality of first metal interconnect structures; A dielectric pillar structure vertically extending through each of the plurality of first dielectric material layers and having an overlap area with the semiconductor lens in a plan view; and a first bonding layer of dielectric layers having a plurality of first metal bonding pads formed therein, wherein a first set of the plurality of first metal bonding pads has an overlap area with the dielectric pillar structure in a plan view; and A photonic integrated circuit die including a plurality of waveguides; a plurality of photonic devices; a plurality of second dielectric material layers embedding a plurality of second metal interconnect structures; a second bonding layer of dielectric layers having a plurality of second metal bonding pads formed therein, wherein the plurality of second metal bonding pads are bonded to the plurality of first metal bonding pads.

7. The photonic assembly of claim 6, wherein: The electronic integrated circuit die includes a dielectric protection liner laterally surrounding the dielectric pillar structure and contacting each of the plurality of first dielectric material layers; The electronic integrated circuit die includes a plurality of passivation layers of dielectric layers between the plurality of first dielectric material layers and the first bonding layer of dielectric layers; and A first of the plurality of passivation layers of dielectric layers is between the plurality of first dielectric material layers and a horizontally extending portion of the dielectric protection liner. ​ ​ 8. The photonic package of claim 7, wherein, All of the first set of first metal bonding pads are located in an area defined by inner sidewalls of vertically extending portions of the dielectric protective liner that vertically extend through the first dielectric material layers in plan view.

9. The photonic assembly of claim 7, wherein, The first set of first metal bonding pads each have a first thickness that is greater than a thickness of the dielectric layer of the first bonding layer, and each include a respective portion to protrude into the dielectric pillar structure; and The second set of first metal bonding pads each have no area of overlap with the dielectric pillar structure in plan view and each include a pad portion having a second thickness that is less than the first thickness and a via portion that extends through the dielectric protective liner.

10. The photonic package of claim 7, wherein, At least one of the first set of first metal bonding pads has an area of overlap with the vertically extending portions of the dielectric protective liner that vertically extend through the first dielectric material layers in plan view.

Images