Naked-eye 3D display circuit for realizing 3D interleaving function and naked-eye 3D display equipment

Abstract

The utility model discloses a naked-eye 3D display circuit and naked-eye 3D display equipment for realizing a 3D interleaving function, and the circuit comprises a first connector which is used for receiving a 2D or 3D signal transmitted by a front end and outputting the 2D or 3D signal through a first signal group; the 3D interleaving circuit is used for receiving an output signal of the first connector, distinguishing the signal and outputting the signal through a signal output end; the second connector is used for receiving an output signal of the 3D interleaving circuit and outputting the output signal through a second interface; and the power supply circuit is in power supply connection with the first connector, the 3D interleaving circuit and the second connector. According to the utility model, the naked-eye 3D display circuit is utilized to realize the processing of a naked-eye 3D interleaving algorithm, and the use of GPU resources is fully reduced, so that high-resolution naked-eye 3D display can be realized on equipment with low GPU configuration, and powerful technical support is provided for the popularization of naked-eye 3D display equipment.

Description

Technical Field

[0001] This utility model relates to the field of display technology, specifically to a naked-eye 3D display circuit and naked-eye 3D display device that realizes 3D interleaving function. Background Technology

[0002] With the development of technology, various display devices have emerged in an endless stream, and traditional 2D displays can no longer meet people's needs for immersion and realism. As an emerging display technology, naked-eye 3D display technology has the advantage of achieving 3D effects without wearing special glasses, and shows great application potential in entertainment, education, medical care, advertising and other fields.

[0003] In glasses-free 3D display technology, 3D interlacing processing is achieved through algorithms. Therefore, it often requires high-end GPU graphics cards to achieve high-resolution glasses-free 3D display. This places high demands on the performance parameters of display terminal devices, thus limiting the widespread adoption of this technology. Summary of the Invention

[0004] Purpose of the invention: To address the above-mentioned shortcomings, this utility model provides a naked-eye 3D display circuit and a naked-eye 3D display device that realizes 3D interleaving function. The naked-eye 3D display circuit realizes the processing of naked-eye 3D interleaving algorithm, which greatly reduces the use of GPU resources, thereby enabling high-resolution naked-eye 3D display on devices with low GPU configuration.

[0005] Technical solution: To achieve the above objectives, this utility model provides a naked-eye 3D display circuit that realizes 3D interlacing function, comprising:

[0006] The first connector has a first interface for receiving 2D or 3D signals transmitted from the front end and outputting them through a first signal group;

[0007] The 3D interleaving circuit includes a signal input terminal and a signal output terminal, wherein the signal input terminal is connected to a first signal group for receiving the output signal of the first connector, distinguishing and processing the signal, and then sending it to the signal output terminal;

[0008] The second connector has a second interface. The second connector is connected to the signal output terminal through the second signal group and is used to receive the output signal of the 3D interleaving circuit and output it through the second interface.

[0009] The power supply circuit is connected to the first connector, the 3D interlacing circuit and the second connector respectively.

[0010] Specifically, the process of distinguishing and processing the signal includes:

[0011] If it is a 2D signal, it passes directly; if it is a 3D signal, it is interleaved.

[0012] Specifically, both the first interface and the second interface are VBO interfaces, and both the first signal group and the second signal group are VBO signal groups.

[0013] More specifically, the first signal group includes a first hot-plug signal, a first lock signal, a first IIC signal, and a first differential signal, and the second signal group includes a second hot-plug signal, a second lock signal, a second IIC signal, and a second differential signal. Both the first differential signal and the second differential signal use 2N lanes of data signals, where N = 1, 2, 4, and each lane of data signal is a differential signal.

[0014] More specifically, the 3D interleaving circuit includes a 3D interleaving chip, wherein the HTPDN-IN, LOCKN-IN, and VBO-IN pins of the 3D interleaving chip are respectively used to connect to a first hot-plug signal, a first lock signal, and a first differential signal, thereby forming a signal input terminal; the HTPDN-OUT, LOCKN-OUT, and VBO-OUT pins are respectively used to connect to a second hot-plug signal, a second lock signal, and a second differential signal, thereby forming a signal output terminal; and the IIC pin is used to connect to a first IIC signal and a second IIC signal, thereby forming a signal input and output terminal.

[0015] Specifically, the naked-eye 3D display circuit further includes one or more of the following structures:

[0016] The third connector has a third interface and is connected to the 3D interleaving circuit via a third signal group to receive external commands and firmware data.

[0017] The fourth connector has a fourth interface and is connected to the 3D interleaving circuit via a fourth signal group for receiving external commands and transmitting status information.

[0018] More specifically, the third interface and the fourth interface are respectively an IIC interface and a UART interface, and the third signal group and the fourth signal group are respectively an IIC signal group and a UART signal group.

[0019] Specifically, the power supply circuit includes a first voltage input terminal and first to fifth voltage output terminals, used to step down the DC voltage connected to the first voltage input terminal to 1.1V, 3.3V, 1.2V, 1.8V and 2.5V, and then output them through the first to fifth voltage output terminals respectively.

[0020] Specifically, the power supply circuit includes:

[0021] The first step-down circuit includes a first voltage input terminal and a first voltage output terminal, used to step down the DC voltage connected to the first voltage input terminal to 1.1V, and then output it through the first voltage output terminal;

[0022] The second step-down circuit includes a first voltage input terminal and a second voltage output terminal, which is used to step down the DC voltage connected to the first voltage input terminal to 3.3V and then output it through the second voltage output terminal;

[0023] The third step-down circuit includes a third voltage output terminal, which is used to step down the 3.3V voltage output from the second voltage output terminal to 1.2V, and then output it through the third voltage output terminal;

[0024] The fourth step-down circuit includes a fourth voltage output terminal, which is used to step down the 3.3V voltage output from the second voltage output terminal to 1.8V, and then output it through the fourth voltage output terminal;

[0025] The fifth step-down circuit includes a fifth voltage output terminal, which is used to step down the 3.3V voltage output from the second voltage output terminal to 2.5V, and then output it through the fifth voltage output terminal.

[0026] In addition, this utility model also provides a glasses-free 3D display device, including: a driver board and a display panel, wherein the driver board is connected to the display panel through any of the above-mentioned glasses-free 3D display circuits.

[0027] Beneficial effects: This utility model forms a stable, reliable, and standard naked-eye 3D display circuit by using a first connector, a 3D interleaving circuit, a second connector, and a power supply circuit. This enables the processing of naked-eye 3D interleaving algorithms, significantly reducing the use of GPU resources. As a result, high-resolution naked-eye 3D display can be achieved on devices with low GPU configurations, providing strong technical support for the promotion of naked-eye 3D display devices. Attached Figure Description

[0028] Figure 1 This is a schematic block diagram of a naked-eye 3D display circuit in one embodiment of the present invention;

[0029] Figure 2 This is a signal connection block diagram of a 3D interleaving circuit in one embodiment of the present invention;

[0030] Figure 3 This is a signal connection circuit diagram of a 3D interleaving chip in one embodiment of the present invention;

[0031] Figure 4 This is a schematic block diagram of the power supply circuit in one embodiment of the present invention;

[0032] Figure 5 This is a circuit diagram of the step-down circuit 1 in one embodiment of the present invention;

[0033] Figure 6 This is a circuit diagram of the step-down circuit 2 in one embodiment of the present invention;

[0034] Figure 7 This is a circuit diagram of the step-down circuit 3 in one embodiment of the present invention;

[0035] Figure 8 This is a circuit diagram of the step-down circuit 4 in one embodiment of the present invention;

[0036] Figure 9 This is a circuit diagram of the step-down circuit 5 in one embodiment of the present invention;

[0037] Figure 10 This is a power supply connection circuit for a 3D interlacing chip in one embodiment of the present invention. Figure 1 ;

[0038] Figure 11 This is a power supply connection circuit for a 3D interlacing chip in one embodiment of the present invention. Figure 2 ;

[0039] Figure 12 This is an application scenario diagram of the naked-eye 3D display circuit in one embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, features, and advantages of this utility model more apparent and understandable, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this utility model. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments.

[0041] Reference Figure 1 This utility model provides a naked-eye 3D display circuit that realizes 3D interleaving function, mainly including a first connector, a 3D interleaving circuit and a second connector connected in sequence, and also includes a power supply circuit, which is connected to the first connector, the 3D interleaving circuit and the second connector respectively.

[0042] Specifically, the first connector is equipped with a VBO interface for receiving 2D or left-right format 3D signals sent by front-end devices such as driver boards, and outputting these signals to the 3D interleaving circuit through the VBO signal group (i.e., the first signal group). The 3D interleaving circuit includes a signal input terminal and a signal output terminal. The signal input terminal is connected to the first signal group and is used to receive the output signal from the first connector and to differentiate and process the signal. 2D signals pass directly without any processing, while left-right format 3D signals are interleaved and then sent to the signal output terminal. The second connector is connected to the signal output terminal through the VBO signal group (i.e., the second signal group) and is used to receive the output signal from the 3D interleaving circuit. The second connector is equipped with a VBO interface for outputting VBO signals to the display panel. The power supply circuit is used to input DC-IN voltage, which is stepped down and then outputs 1.1V, 3.3V, 1.2V, 1.8V, and 2.5V voltages to the 3D interleaving circuit.

[0043] Furthermore, the naked-eye 3D display circuit also includes a third connector and a fourth connector. The third connector is equipped with an IIC interface for receiving instructions and firmware data from the outside and then sending them to the 3D interleaving circuit through the IIC signal group (i.e., the third signal group). The fourth connector is equipped with a UART interface for receiving instructions and transmitting status information from the outside and then sending the instructions to the 3D interleaving circuit through the UART signal group (i.e., the fourth signal group) and transmitting the status information of the 3D interleaving circuit back.

[0044] More specifically, the 3D interleaving circuit includes voltage input terminals IN2 to IN6, signal input terminal IN8 and signal output terminal Out7, as well as signal input / output terminals INOUT2 and INOUT4. The first connector includes voltage input terminal IN7 and signal output terminal Out6. The second connector includes voltage input terminal IN4 and signal input terminal IN9. The power supply circuit includes voltage input terminal IN1 and voltage output terminals OUT1 to OUT5. The third connector includes signal input / output terminal INOUT1. The fourth connector includes signal input / output terminal INOUT3. The voltage input terminals IN2 to IN6 of the 3D interleaving circuit are connected to the voltage output terminals OUT1 to OUT5 of the power supply circuit, respectively, to receive 1.1V, 3.3V, 1.2V, 1.8V, and 2.5V voltages. The signal input terminal IN8 is connected to the signal output terminal Out6 of the first connector via the VBO signal group, to receive VBO signals sent by front-end devices such as processors. The signal output terminal Out7 is connected to the signal input terminal IN9 of the second connector via the VBO signal group, to output the VBO signal after 3D interleaving. The signal input / output terminal INOUT2 is connected to the signal input / output terminal INOUT1 of the third connector via the IIC signal group, to receive external commands and firmware data. The signal input / output terminal INOUT4 is connected to the signal input / output terminal INOUT3 of the fourth connector via the UART signal group, to receive external commands and transmit status information. Furthermore, the voltage input terminals IN1, IN4, and IN7 are all used to connect to DC-IN voltage.

[0045] For example, refer to Figure 2The VBO signal group of the first connector includes a first hot-plug signal HTPDN-IN, a first lock signal LOCKN-IN, a first IIC signal SCL-IN / SDA-IN, and a first differential signal VR0~7P / N-IN. The first hot-plug signal HTPDN-IN and the first lock signal LOCKN-IN are control signals used to control the data transmission status. The first IIC signal SCL-IN / SDA-IN is a communication signal used for command transmission and firmware updates. The first differential signal VR0~7P / N-IN is a high-speed data signal used to realize 2D / 3D image data transmission. The second connector... The device's VBO signal group includes a second hot-plug signal HTPDN-OUT, a second lock signal LOCKN-OUT, a second IIC signal SCL-OUT / SDA-OUT, and a second differential signal VR0~7P / N-OUT. The second hot-plug signal HTPDN-OUT and the second lock signal LOCKN-OUT are control signals used to control the data transmission status. The second IIC signal SCL-OUT / SDA-OUT is a communication signal used for command transmission and firmware updates. The second differential signal VR0~7P / N-OUT is a high-speed data signal used to realize 2D / 3D image data transmission.

[0046] More specifically, the first differential signal VR0~7P / N-IN uses 8 lanes of data signal, namely VR0P-IN, VR0N-IN, VR1P-IN, VR1N-IN, VR2P-IN, VR2N-IN, VR3P-IN, VR3N-IN, VR4P-IN, VR4N-IN, VR5P-IN, VR5N-IN, VR6P-IN, VR6N-IN, VR7P-IN, and VR7N-IN. Each lane uses a pair of differential signal lines, and the maximum input data rate can reach 3.75Gbps. Correspondingly, the second differential signal VR0~7P / N-OUT also uses 8 lanes of data signal, namely VT0P-OUT, VT0N-OUT, VT1P-OUT, VT1N-OUT, VT2P-OUT, VT2N-OUT, VT3P-OUT, VT3N-OUT, VT4P-OUT, VT4N-OUT, VT5P-OUT, VT5N-OUT, VT6P-OUT, VT6N-OUT, VT7P-OUT, and VT7N-OUT. Each lane uses a pair of differential signal lines, and the maximum output data rate can reach 3.75Gbps. This solution supports video signals with resolutions up to 4K, refresh rates of 60Hz, and color depths of 24bpp, and is suitable for glasses-free 3D display systems.

[0047] For example, refer to Figure 3The core of the 3D interleaving circuit uses a Z2D4K01 3D interleaving chip. The HP-O and LK-O pins (P3 and R3) of the 3D interleaving chip are used to connect to the first hot-plug signal HTPDN-IN and the first lock signal LOCKN-IN. The VR0 to 7N / P pins (N1, P2, P1, R2, R1, T2, T1, U2, U1, V2, V1, W2, W1, Y2, Y1, AA2) are connected to the first differential signals VR0 to 7P / N-IN via capacitors C512 to C527, thus forming the signal input terminal IN8. The HP-I and LK-I pins (C14 and C15) are used to connect to the second hot-plug signal HTPDN-OUT and the second lock signal LOCKN-OUT. The VT0 to 7N / P pins (A13, B14, A15) are connected to the first differential signals VR0 to 7P / N-IN via capacitors C512 to C527, thus forming the signal input terminal IN8. 4. Pins B15, A15, B16, A16, B17, A17, B18, A18, B19, A19, B20, A20, and B21 are connected to the second differential signals VR0 to 7P / N-OUT via capacitors C528 to C543, thus forming the signal output terminal Out7; the IICS_SCL and IICS_SDA pins (i.e., pins T3 and U3) are used to connect the first IIC signal SCL-IN / SDA-IN and the second IIC signal SCL-OUT / SDA-OUT, and simultaneously connect to the IIC signal SCL-IN / SDA-IN of the third connector, thus forming the signal input / output terminal INOUT2; the P3_0 and P3_1 pins (i.e., pins C22 and C21) are used to connect to the UART signals RXD and TXD of the fourth connector, thus forming the signal input / output terminal INOUT4.

[0048] For example, the first connector is a 51-pin connector of model FI-RE51S-HF-R1500, which has a VBO interface. Some pins of this connector are connected to the signal input terminal IN8 of the 3D interleaving circuit through the aforementioned VBO signal group, and some pins are connected to the voltage input terminal IN1 of the power supply circuit through the DC-IN voltage signal line.

[0049] For example, the second connector also uses a 51-pin connector of model FI-RE51S-HF-R1500, which has a VBO interface. Some pins of this connector are connected to the signal output terminal OUT7 of the 3D interleaving circuit through the aforementioned VBO signal group, and some pins are connected to the voltage input terminal IN1 of the power supply circuit through the DC-IN voltage signal line.

[0050] For example, the third connector is a 4-pin connector of model HC-XHB-4A-X, which has an IIC interface. Some pins of this connector are connected to the signal input / output terminal INOUT2 of the 3D interleaved chip through the IIC signal group, which is used to receive IIC commands and burn firmware.

[0051] For example, the fourth connector is a 4-pin connector of model KH-PH-4P-Z, which has a UART interface. Some pins of this connector are connected to the signal input / output terminal INOUT4 of the 3D interleaving chip through the UART signal group to receive UART commands and printing status information.

[0052] For example, refer to Figure 4 The power supply circuit includes step-down circuits 1 to 5 (i.e., the first to fifth step-down circuits). The voltage input terminal IN1 of step-down circuits 1 and 2 is used to connect to the DC-IN voltage. Specifically, the DC-IN voltage can be a common screen power supply voltage within the range of 5V-12V. After being stepped down by the DC-CDC converter, the DC-IN voltage outputs 1.1V through the voltage output terminal OUT1 and 3.3V through the voltage output terminal OUT2. The voltage input terminals of step-down circuits 3, 4, and 5 are connected to the voltage output terminal OUT2 to connect to the 3.3V voltage. After being stepped down by the LDO, the 3.3V voltage is output through the voltage output terminals OUT3, OUT4, and OUT5, respectively, resulting in 1.2V, 1.8V, and 2.5V. For more details, refer to [reference needed]. Figure 1 The 3D interleaving circuit includes voltage input terminals IN2 to IN6. Voltage input terminal IN2 is connected to voltage output terminal OUT1, voltage input terminal IN3 is connected to voltage output terminal OUT2, voltage input terminal IN4 is connected to voltage output terminal OUT3, voltage input terminal IN5 is connected to voltage output terminal OUT4, and voltage input terminal IN6 is connected to voltage output terminal OUT5, thereby powering the 3D interleaving circuit. Furthermore, the first voltage input terminal IN1 is connected to the first connector and the second connector via DC voltage signal lines. The DC-DC converter circuit, as a commonly used DC power conversion circuit, features high efficiency, stable voltage, and low cost; the LDO circuit, as a voltage conversion circuit, features low price, stable voltage, and low ripple.

[0053] Specifically, refer to Figure 5The step-down circuit 1 includes a first step-down chip, which is a SY8286A chip. Its IN1 / 2 / 3 pins (i.e., pins 2, 3, and 4) are connected to the voltage input terminal IN1 through inductor L110, and grounded through capacitors C138, C141, C142, and C143. Simultaneously, the IN1 / 2 / 3 pins are connected to the EN pin (i.e., pin 9) through resistor R129, and the EN pin is grounded through resistor R340. The IN1 / 2 / 3 pins are also connected to the MODE pin (i.e., pin 8) through resistor R131, and the MODE pin is grounded through resistor R139. The ILMT pin (i.e., pin 10) is grounded through resistor R140, and the BYP pin (i.e., pin 12) is grounded through resistor R140. The GND1, GND2, and G1 pins (i.e., pins 6, 14, and 17) are grounded through capacitor C155, and the VCC pin (i.e., pin 13) is grounded through capacitor C156; the FB pin (i.e., pin 11) is grounded through resistor R117 and connected to the voltage output terminal OUT1 through resistor R132, and also connected to the voltage output terminal OUT1 through a series resistor R136 and capacitor C145. The voltage output terminal OUT1 is grounded through capacitors C146 to C149 in parallel; the LX1 / 2 / 3 pins (i.e., pins 5, 15, and 16) are connected to the voltage output terminal OUT1 through inductor L24, and the BS pin (i.e., pin 1) is connected to the LX1 / 2 / 3 pins through capacitor C139.

[0054] Specifically, refer to Figure 6 The step-down circuit 2 includes a second step-down chip, which is a SY8113IADC chip. Its IN pin (i.e., pin 5) is connected to the voltage input terminal IN1 through inductor L101 and grounded through parallel capacitors C158 and C159. At the same time, the IN pin is connected to the EN pin (i.e., pin 4) through resistor R101. The EN pin is grounded through parallel resistor R342 and capacitor C106. The FB pin (i.e., pin 3) is connected to the voltage output terminal OUT2 through parallel resistor R102 and capacitor C100 and grounded through resistor R105. The voltage output terminal OUT2 is grounded through parallel capacitors C102 to C104. The LX pin (i.e., pin 6) is connected to the voltage output terminal OUT2 through inductor L23. At the same time, the BS pin (i.e., pin 1) is connected to the LX pin through capacitor C157. The GND pin (i.e., pin 2) is grounded.

[0055] Specifically, refer to Figure 7The step-down circuit 3 includes a third step-down chip, which is an MP8904 chip. Its IN pin (i.e., pin 8) is connected to the voltage output terminal OUT2 and grounded through capacitor C575. At the same time, the IN pin is connected to the EN pin (i.e., pin 5) through resistor R343, and the EN pin is grounded through resistor R344. The FB pin (i.e., pin 4) is connected to the voltage output terminal OUT3 through resistor R300 and grounded through resistor R301. The voltage output terminal OUT3 is grounded through capacitor C576. The PG pin (i.e., pin 3) outputs voltage and is connected to the voltage output terminal OUT3 through resistor R299. The OUT pin (i.e., pin 1) is connected to the voltage output terminal OUT3, and the GND pins (i.e., pins 6 and 9) are grounded.

[0056] Specifically, refer to Figure 8 The step-down circuit 4 includes a fourth step-down chip, which is an MP8801 chip. Its IN pin (i.e., pin 1) is connected to the voltage output terminal OUT2 and grounded through capacitor C579. At the same time, the IN pin is connected to the EN pin (i.e., pin 3) through resistor R347, and the EN pin is grounded through resistor R348. The FB pin (i.e., pin 4) is connected to the voltage output terminal OUT4 through resistor R304 and grounded through resistor R305. The OUT pin (i.e., pin 5) is connected to the voltage output terminal OUT4, and the voltage output terminal OUT4 is grounded through capacitor C580. The GND pin (i.e., pin 2) is grounded.

[0057] Specifically, refer to Figure 9 The step-down circuit 5 includes a fifth step-down chip, which is an MP8801 chip. Its IN pin (i.e., pin 1) is connected to the voltage output terminal OUT2 and grounded through capacitor C577. At the same time, the IN pin is connected to the EN pin (i.e., pin 3) through resistor R345, and the EN pin is grounded through resistor R346. The FB pin (i.e., pin 4) is connected to the voltage output terminal OUT5 through resistor R302 and grounded through resistor R303. The OUT pin (i.e., pin 5) is connected to the voltage output terminal OUT5, and the voltage output terminal OUT5 is grounded through capacitor C578. The GND pin (i.e., pin 2) is grounded.

[0058] Continue to refer to Figure 10The 26 VDD pins of the 3D interleaving chip (i.e., pins T17, T18, R18, J7, L16, L17, L18, M17, M18, N17, N18, P17, P18, R17, E5, E6, E7, F5, F6, F7, G5, G6, G7, H5, H6, H7), four PLL_AVDD11 pins (i.e., pins Y11, Y9, D19, Y10), two VBORX_AVDD11 pins (i.e., pins Y4, AA4), and two VBOTX_AVDD11 pins (i.e., pins D12, D13) are all connected to the voltage output terminal OUT1, and are grounded through capacitors C228~C230, C330~342, C362~C394, C493~C496, and C499~C502. In addition, all ninety-five VSS pins of the 3D interleaving chip (i.e., pins E8~E11, F8~F14, G8~G14, H8~H14, J8~J14, K7~K14, L7~L15, M7~M16, N7~N15, P9~P15, R9~R15, T9~T15, U9~U11, V9~V11), four PLL_AVSS11 pins (i.e., pins W9~W11, E18), two VBORX_AVSS11 pins (i.e., pins AB3, AB4) and two VBOTX_AVSS11 pins (i.e., pins E12, E13) are grounded.

[0059] Continue to refer to Figure 11The seventeen VDD33 pins of the 3D interleaving chip (i.e., pins F18, G17, G18, H17, H18, J17, J18, K17, K18, P5, P6, R5, R6, T5, T6, U5, U6) are connected to the voltage output terminal OUT2 and grounded through capacitors C405 to C427; five VDDQDIE pins (i.e., pins Y16 to Y20) and five VDDQDDR pins (i.e., pins V16 to V18, W17, W...) 18) The five VDD2 pins (i.e., pins U19, U20, V19, W19, W20) are connected to the voltage output terminal OUT3, and grounded through capacitors C293~C306 and C458~C468; the four VDD1 pins (i.e., pins P20, R19, R20, T19) are connected to the voltage output terminal OUT4, and grounded through capacitors C276~C279 and C286~C292; the four PLL_AVDD25 pins (i.e., pins Y6~Y8, D20) and the four MIPIIN_AV The DD pin (i.e., pins D4, E4, F4, G4), four MIPIOUT_AVDD pins (i.e., pins C5, D5~D7), six VBORX_AVDD25 pins (i.e., pins N3, N4, P4, R4, T4, U4) and six VBOTX_AVDD25 pins (i.e., pins C18, D14~D17, E17) are connected to the voltage output terminal OUT5, and are grounded through capacitors C207~C209, C317~C329, C475~C492, and C503~C504. In addition, the 3D interleaving chip has eight VSSQ pins (i.e., pins U12-U14, V12-V14, W12, Y12), five VSSQDDR pins (i.e., pins U15-U18, V15), four VSSDDR pins (i.e., pins N16, P16, R16, T16), four PLL0_AVSS pins (i.e., pins W6-W8, D18), six MIPIIN_AGND pins (i.e., pins A1, B2, H4, J4, K4, L4), and five MIPIOUT_A The GND pins (i.e., pins C10, D8~D11), the seven VBORX_AVSS25 pins (i.e., pins M1, W4, AA3, AB2, N2, V4, Y3), the six VBOTX_AVSS25 pins (i.e., pins A12, E14~E16, B13, C13), and the seventeen VSSD pins (i.e., pins F15, G15, G16, H15, H16, J15, J16, K15, K16, P7, P8, R7, R8, T7, T8, U7, U8) are all grounded.

[0060] In addition, this utility model also provides a naked-eye 3D display device, which includes: a driver board, a 3D signal processing board (i.e., the naked-eye 3D display circuit mentioned above) and a display panel; wherein the driver board is used to receive image data sent by a front-end device such as a host, and the 3D signal processing board performs 3D interleaving processing after receiving the data and outputs it to the display panel.

[0061] For example, refer to Figure 12 The glasses-free 3D display device includes a driver board, a 3D signal processing board (i.e., the aforementioned glasses-free 3D display circuit), an adapter board, and a 2D / 3D switchable screen. The PC host transmits each frame of the image data to the driver board via an HDMI / DP signal cable. The driver board performs protocol conversion on the received image data and then outputs it to the 3D signal processing board (i.e., the aforementioned glasses-free 3D display circuit that implements 3D interleaving) via a VBO signal cable. The 3D signal processing board performs 3D interleaving processing on the image data and then outputs it to the adapter board via a VBO signal cable. At the same time, the 3D signal processing board also feeds back the 2D / 3D image status to the driver board via GPIO signal lines. The adapter board performs protocol conversion on the received VBO signal and then outputs it to the 2D / 3D switchable screen via an eDP signal cable.

[0062] Furthermore, the naked-eye 3D display device also includes an eye-tracking module and a 3D signal control board. The 3D signal control board receives control commands from the driver board and transmits 2D / 3D membrane switching signals to the 2D / 3D switchable screen via FPC signal lines. It also receives positioning signals from the eye-tracking module and connects to the 3D signal processing board via I2C signal lines to enable 2D / 3D state reading and switching, as well as 3D parameter reading and writing. Additionally, an external power supply is connected to each module inside the display device via the driver board.

[0063] By utilizing the aforementioned glasses-free 3D display circuit, high-performance conversion of 3D signals can be achieved, significantly reducing the use of GPU resources. This enables high-resolution glasses-free 3D display on devices with limited GPU configurations. Furthermore, this invention is adaptable to different models of display terminal devices, achieving industry-leading stereoscopic 3D visual effects while maintaining high cost-effectiveness.

[0064] The above are merely specific embodiments of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A glasses-free 3D display circuit for realizing 3D interlacing function, characterized in that, include: The first connector has a first interface for receiving 2D or 3D signals transmitted from the front end and outputting them through a first signal group; The 3D interleaving circuit includes a signal input terminal and a signal output terminal, wherein the signal input terminal is connected to a first signal group for receiving the output signal of the first connector, distinguishing and processing the signal, and then sending it to the signal output terminal; The second connector has a second interface. The second connector is connected to the signal output terminal through the second signal group and is used to receive the output signal of the 3D interleaving circuit and output it through the second interface. The power supply circuit is connected to the first connector, the 3D interlacing circuit and the second connector respectively.

2. The naked-eye 3D display circuit according to claim 1, characterized in that, The specific steps for distinguishing and processing this signal are as follows: If it is a 2D signal, it passes directly; if it is a 3D signal, it is interleaved.

3. The naked-eye 3D display circuit according to claim 1, characterized in that, Both the first interface and the second interface are VBO interfaces, and both the first signal group and the second signal group are VBO signal groups.

4. The naked-eye 3D display circuit according to claim 3, characterized in that, The first signal group includes a first hot-plug signal, a first lock signal, a first IIC signal, and a first differential signal. The second signal group includes a second hot-plug signal, a second lock signal, a second IIC signal, and a second differential signal. Both the first differential signal and the second differential signal use 2N lanes of data signals, where N = 1, 2, 4, and each lane of data signal is a differential signal.

5. The naked-eye 3D display circuit according to claim 4, characterized in that, The 3D interleaving circuit includes a 3D interleaving chip, wherein the HTPDN-IN, LOCKN-IN, and VBO-IN pins of the 3D interleaving chip are respectively used to connect to a first hot-plug signal, a first lock signal, and a first differential signal, thereby forming a signal input terminal; the HTPDN-OUT, LOCKN-OUT, and VBO-OUT pins are respectively used to connect to a second hot-plug signal, a second lock signal, and a second differential signal, thereby forming a signal output terminal; and the IIC pin is used to connect to a first IIC signal and a second IIC signal, thereby forming a signal input and output terminal.

6. The naked-eye 3D display circuit according to claim 1, characterized in that, It also includes one or more of the following structures: The third connector has a third interface and is connected to the 3D interleaving circuit via a third signal group to receive external commands and firmware data. The fourth connector has a fourth interface and is connected to the 3D interleaving circuit via a fourth signal group for receiving external commands and transmitting status information.

7. The naked-eye 3D display circuit according to claim 6, characterized in that, The third and fourth interfaces are IIC and UART interfaces, respectively, and the third and fourth signal groups are IIC and UART signal groups, respectively.

8. The naked-eye 3D display circuit according to claim 1, characterized in that, The power supply circuit includes a first voltage input terminal and first to fifth voltage output terminals, used to step down the DC voltage connected to the first voltage input terminal to 1.1V, 3.3V, 1.2V, 1.8V and 2.5V, and then output them through the first to fifth voltage output terminals respectively.

9. The naked-eye 3D display circuit according to claim 1, characterized in that, The power supply circuit includes: The first step-down circuit includes a first voltage input terminal and a first voltage output terminal, used to step down the DC voltage connected to the first voltage input terminal to 1.1V, and then output it through the first voltage output terminal; The second step-down circuit includes a first voltage input terminal and a second voltage output terminal, which is used to step down the DC voltage connected to the first voltage input terminal to 3.3V and then output it through the second voltage output terminal; The third step-down circuit includes a third voltage output terminal, which is used to step down the 3.3V voltage output from the second voltage output terminal to 1.2V, and then output it through the third voltage output terminal; The fourth step-down circuit includes a fourth voltage output terminal, which is used to step down the 3.3V voltage output from the second voltage output terminal to 1.8V, and then output it through the fourth voltage output terminal; The fifth step-down circuit includes a fifth voltage output terminal, which is used to step down the 3.3V voltage output from the second voltage output terminal to 2.5V, and then output it through the fifth voltage output terminal.

10. A glasses-free 3D display device, characterized in that, include: A driver board and a display panel, wherein the driver board is connected to the naked-eye 3D display circuit and the display panel as described in any one of claims 1 to 9.

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