High-precision capacitance detection circuit

Abstract

A high-precision capacitance detection circuit comprises a first current source Iref1, a detection capacitor CIN, a third switch SW3, a first reference capacitor Cref1, a first switch SW1, a second reference capacitor Cref2, a second switch SW2, a second current source Iref2, a detection resistor Rref, a comparator, an MOS switch tube, a counter and an oscillator. The capacitance detection circuit has the advantages that by introducing the reference capacitor, capacitance detection errors caused by non-ideal factors of an existing capacitance detection scheme are eliminated, so that the precision of capacitance detection is improved, and the detection scheme can be applied to the scenes of microphone detection, touch capacitance key capacitance detection and the like.

Description

Technical Field

[0001] This utility model relates to the field of capacitance detection technology, specifically to a high-precision capacitance detection circuit. Background Technology

[0002] Capacitive detection technology is required in scenarios such as electronic cigarette microphones and capacitive touch button detection.

[0003] However, in the capacitance detection scheme implemented with chips, capacitance detection errors will occur due to the influence of voltage, temperature and current source ratio errors, resistance deviations, comparator offsets and reference clock deviations. In order to reduce the influence of these non-ideal factors, we propose a technical solution to improve the accuracy of capacitance detection. Utility Model Content

[0004] We propose a scheme to improve the accuracy of capacitance detection.

[0005] A high-precision capacitance detection circuit includes a first current source Iref1, a detection capacitor CIN, a third switch SW3, a first reference capacitor Cref1, a first switch SW1, a second reference capacitor Cref2, a second switch SW2, a second current source Iref2, a detection resistor Rref, a comparator, a MOS switch, a counter, and an oscillator. The output terminal of the first current source Iref1 is connected to one end of the first switch SW1, the second switch SW2, and the third switch SW3, respectively. The first current source Iref1 is connected to the non-inverting input terminal of the comparator. The other end of the third switch SW3 is connected to the detection capacitor CIN. The first switch SW1 is connected to the first reference capacitor Cref1, and the second switch SW2 is connected to the second reference capacitor Cref2. The output terminal of the second current source Iref2 is connected to the inverting input terminal of the comparator and the detection resistor Rref, respectively. The output terminal of the comparator is connected to the gate of the MOS switch. The source of the MOS switch is grounded, and the drain of the MOS switch is connected to the output terminal of the first current source Iref1. The output terminal of the comparator is also connected to the input terminal of the counter, and the output terminal of the oscillator is connected to the clock input terminal of the counter.

[0006] Preferably, a single-sided delay circuit is further provided between the output terminal of the comparator and the gate of the MOS switch.

[0007] Compared with the prior art, the advantages of this utility model are: by introducing a reference capacitor, the capacitance detection error caused by non-ideal factors in the existing capacitance detection scheme is eliminated, thereby improving the accuracy of capacitance detection. This detection scheme can be applied to scenarios such as microphone detection and touch capacitive button capacitance detection. Attached Figure Description

[0008] Figure 1This is a circuit block diagram of this utility model;

[0009] Figure 2 This is the circuit diagram for the capacitance detection of this utility model. Detailed Implementation

[0010] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0011] See Figure 1 As shown, a high-precision capacitance detection circuit includes a first current source Iref1, a detection capacitor CIN, a third switch SW3, a first reference capacitor Cref1, a first switch SW1, a second reference capacitor Cref2, a second switch SW2, a second current source Iref2, a detection resistor Rref, a comparator, a MOS switch, a counter, and an oscillator. The output terminal of the first current source Iref1 is connected to one end of the first switch SW1, the second switch SW2, and the third switch SW3, respectively. The first current source Iref1 is connected to the non-inverting input terminal of the comparator. The other end of the third switch SW3 is connected to the detection capacitor CIN. The first switch SW1 is connected to the first reference capacitor Cref1, and the second switch SW2 is connected to the second reference capacitor Cref2. The output terminal of the second current source Iref2 is connected to the inverting input terminal of the comparator and the detection resistor Rref, respectively. The output terminal of the comparator is connected to the gate of the MOS switch. The source of the MOS switch is grounded, and the drain of the MOS switch is connected to the output terminal of the first current source Iref1. The output terminal of the comparator is also connected to the input terminal of the counter, and the output terminal of the oscillator is connected to the clock input terminal of the counter.

[0012] The first switch SW1, the second switch SW2, and the third switch SW3 are controlled by the controller, which controls the power supply of the current source Iref1 to the first reference capacitor Cref1, the second reference capacitor Cref2, and the detection capacitor CIN, respectively.

[0013] First, switch SW3 is turned on. Current source Iref1 charges the sensing capacitor CIN, and another current source Iref2 powers the sensing resistor Rref. One end of the sensing capacitor CIN and the sensing resistor Rref are each connected to the input of a comparator. The comparator compares the voltage on the sensing capacitor CIN with the voltage on the sensing resistor Rref. When the voltage on the sensing capacitor CIN is higher than the voltage on the sensing resistor Rref, the comparator outputs a high level, the MOS switch is turned on, and the sensing capacitor CIN is grounded and discharged. After the discharge is complete, the comparator outputs a low level, the MOS switch is turned off, and the sensing capacitor CIN begins the next cycle of charging. The charging and discharging process is continuously cycled, forming an oscillating clock waveform. The oscillation period is denoted as T.

[0014] Under ideal conditions: T = Rref * CIN * Iref2 / Iref1, let K = Iref2 / Iref1, then T = Rref * CIN * K. To detect the capacitance value of CIN, the oscillator generates a fixed-frequency pulse clock signal Ts, which is then input to the counter. The number of oscillation periods T within a predetermined unit time window M * Ts is calculated to be N, then N * T = M * Ts. Therefore, we can obtain...

[0015] In non-ideal circumstances

[0016]

[0017] Terr is the error of the oscillator clock signal Ts under non-ideal conditions, Rref_err is the error of the sense resistor Rref, Kerr is the error of the ratio K of the first current source Iref1 and the second current source Iref2, Iref1_err is the error of the first current source Iref1, Vos is the comparator offset voltage, and Cp is the parasitic capacitance of the comparator's positive input.

[0018] When the third switch SW3 is closed and the first switch SW1 is opened, the first current source Iref1 supplies power to the first reference capacitor Cref1. The first reference capacitor Cref1 and the detection circuit form an oscillation circuit. Referring to the above derivation process, the calculation formula for the first reference capacitor Cref1 can be obtained as follows:

[0019]

[0020] With the third switch SW3 and the first switch SW1 closed, and the second switch SW2 opened, the first current source Iref1 supplies power to the second reference capacitor Cref2. The second reference capacitor Cref2 and the detection circuit form an oscillation circuit. Referring to the above derivation process, the calculation formula for the second reference capacitor Cref2 can be obtained as follows:

[0021]

[0022] By rearranging formulas (1), (2), and (3), and setting G = (Rref + Rref_err) * (K + Kerr) + Vos / (Iref1 + Iref1_err), we obtain the following formula:

[0023]

[0024] Perform the following operations on both sides of equations (4), (5), and (6). get

[0025] Formula (7) can be rearranged as follows:

[0026]

[0027] By following the steps above, a high-precision value of the detection capacitor CIN can be obtained, and this value eliminates all non-ideal factors in the circuit.

[0028] The data generated by the counter is output to the controller, and the values ​​of the first detection capacitor Cref1 and the second detection capacitor Cref2 are measured in advance by external devices. Through the above calculation steps, the value of the detection capacitor CIN with high precision can be obtained, and this value eliminates all non-ideal factors in the circuit; the counter and oscillator can also be integrated into the controller.

[0029] To ensure that the detection capacitor CIN can discharge completely, a single-sided delay circuit is set between the output of the comparator and the gate of the MOS switch. This ensures that the MOS switch is turned off only after the detection capacitor CIN has discharged to ground. This delay is a single-sided delay, which only applies to low-level signals and does not apply to high-level signals.

Claims

1. A high-precision capacitance detection circuit, characterized in that, The system includes a first current source Iref1, a detection capacitor CIN, a third switch SW3, a first reference capacitor Cref1, a first switch SW1, a second reference capacitor Cref2, a second switch SW2, a second current source Iref2, a detection resistor Rref, a comparator, a MOS switch, a counter, and an oscillator. The output of the first current source Iref1 is connected to one end of the first switch SW1, the second switch SW2, and the third switch SW3, respectively. The first current source Iref1 is also connected to the non-inverting input of the comparator. The other end of the third switch SW3 is connected to the detection capacitor CIN. The first switch SW1 is connected to the first reference capacitor Cref1, and the second switch SW2 is connected to the second reference capacitor Cref2. The output of the second current source Iref2 is connected to the inverting input of the comparator and the detection resistor Rref, respectively. The output of the comparator is connected to the gate of the MOS switch, the source of the MOS switch is grounded, and the drain of the MOS switch is connected to the output of the first current source Iref1. The output of the comparator is also connected to the input of the counter, and the output of the oscillator is connected to the clock input of the counter.

2. The high-precision capacitance detection circuit according to claim 1, characterized in that, A single-sided delay circuit is also provided between the output terminal of the comparator and the gate of the MOS switch.

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