B code generating device applied to embedded test environment
By combining a host computer and FPGA-designed B-code generator, the problem of high cost of traditional equipment is solved, achieving low-cost, high-precision B-code generation and simple encoding verification.
Patent Information
- Application Number
- CN202423114213.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2034-12-17
AI Technical Summary
Traditional B-code generators on the market are expensive and cannot meet the needs of embedded testing environments.
Design a B-code generator that combines a host computer and an FPGA to achieve data interaction through serial communication. Utilize the high-speed computing and programmable characteristics of the FPGA to generate accurate automatic timekeeping B-codes.
It achieves low-cost, high-precision B-code generation, improves the stability and accuracy of B-code generation, and simplifies the encoding verification process.
Smart Images
Figure CN223796882U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of electronic information and communication technology, specifically a B-code generator for use in embedded testing environments. Background Technology
[0002] Currently, my country's measurement, control, computing, communication, and meteorological testing equipment widely adopts the internationally recognized IRIG-B time code (B code for short) as its time synchronization standard. Its characteristics include high reliability, universal standardization, and flexible and convenient use. B code is a serial time format data, with one frame per second, each frame containing 100 code elements, and each code element lasting 10ms. As an internationally recognized standard time code, B code is widely used in embedded projects; however, traditional B code generators are relatively expensive. Summary of the Invention
[0003] This invention aims to reduce the cost of B-code generation equipment by designing a B-code generation device based on a host computer and an FPGA, specifically a B-code generation device for embedded testing environments. In this device, the host computer transmits the system time and receives the B-code decoding time. The hardware platform uses an FPGA as the main controller, which performs timing based on a 100MHz clock. It automatically keeps time using the received system time (year, month, day, hour, minute, second) as a reference and converts it into serial B-code output, providing automatic timekeeping B-code for embedded testing environments.
[0004] This utility model is achieved using the following technical solution: a B-code generator for an embedded testing environment, comprising a host computer and an FPGA, the host computer and the FPGA being connected via a serial port. The host computer is equipped with a system time transmission module, and the FPGA is equipped with a serial communication module, a timecode protocol parsing module, and a B-code generation module. The B-code generation module further includes a timekeeping module, a time conversion module, and a data processing module. The output of the serial communication module is connected to the input of the timecode protocol parsing module, the output of the timecode protocol parsing module is connected to the input of the timekeeping module, the output of the timekeeping module is connected to the input of the time conversion module, and the output of the time conversion module is connected to the input of the data processing module. The system time sending module sends the host computer system time to the FPGA via serial port. The serial communication module receives the time frame data sent by the system time sending module. The time code protocol parsing module parses the time frame data received by the serial communication module to obtain the B code encoded reference time. The timekeeping module receives the B code encoded reference time and outputs the decimal time code. The time conversion module converts the decimal time code to BCD time code. The data processing module converts the BCD time code to serial B code according to the B code encoding format.
[0005] The B code generating device applied to the embedded test environment, the host computer further has a decoding time receiving module.
[0006] The B code generating device has the advantages that: the B code generating device is simple and fast by combining the advantages of the host computer and the FPGA; the high-speed operation and programmable characteristics of the FPGA are used to improve the accuracy and stability of the B code generation; and the data interaction between the host computer and the FPGA is realized through serial communication, so that the accuracy of the B code generating device is verified. BRIEF DESCRIPTION OF DRAWINGS
[0007] Figure 1 The B code generating device has the advantages that: the B code generating device is simple and fast by combining the advantages of the host computer and the FPGA; the high-speed operation and programmable characteristics of the FPGA are used to improve the accuracy and stability of the B code generation; and the data interaction between the host computer and the FPGA is realized through serial communication, so that the accuracy of the B code generating device is verified. DETAILED DESCRIPTION
[0008] The B code generating device applied to the embedded test environment, the host computer further has a decoding time receiving module.
[0009] The host computer develops the decoding time receiving module and the system time sending module by using the QT framework to realize the sending function of the system time and the receiving function of the B code decoding time.
[0010] The FPGA is the core processing unit of the B code generating device and mainly realizes the B code generation function.
[0011] The FPGA includes a serial communication module, a time code protocol analysis module and a B code generation module.
[0012] The serial communication module is used for data transmission with the host computer. The module receives the system time frame data sent by the system time sending module as the input data of the time code protocol analysis module. The serial communication module complies with the UART protocol, in which data is transmitted in frames. Each frame of data includes one start bit, eight data bits, one check bit and one stop bit. The serial communication module of the FPGA is configured with the same baud rate, data bits, stop bits and check bits as the sender to ensure correct data reception. Inside the FPGA, the serial communication module detects signal changes on the serial line, identifies the start bit and starts receiving the data bits. After receiving the data bits, the corresponding check is performed according to whether the check bit is used. Finally, when the stop bit is detected, it indicates that a frame of data has been received.
[0013] The time code protocol analysis module parses the time frame data received by the serial communication module to obtain the B code encoding reference time and configuration parameters. The module performs data checking according to the frame protocol to ensure the accuracy of the time information obtained by the FPGA.
[0014] The B code generation module includes a time keeping module, a time conversion module and a data processing module.
[0015] The time keeping module keeps time at a clock frequency of 100 MHz based on the received B code encoding reference time, outputs a 64-bit decimal time code, and has a precision of 10 ns, realizing accurate automatic time keeping. The module judges the year. If the year is a leap year, the number of days in February of the current year is 29 days, otherwise the number of days in February of the current year is 28 days.
[0016] The time conversion module converts the decimal time representation into BCD time code suitable for the B code generation module. Since the time format in the B code encoding format is year / day / hour / minute / second, the time conversion module first converts the 64-bit decimal time code (16b: year, 8b: month, 8b: day, 8b: hour, 8b: minute, 16b: mseconds) output by the time keeping module into the 64-bit decimal time code (16b: year, 11b: day, 6b: hour, 7b: minute, 16b: seconds) in the B code encoding format, and then converts it into the 64-bit BCD time code (16b: year, 12b: day, 8b: hour, 8b: minute, 20b: mseconds) as the input data of the data processing module.
[0017] The data processing module realizes the B code encoding logic, converts the 64-bit BCD time code into serial B code according to the B code encoding format, and outputs it for the target device to receive and use.
[0018] The B code adopts a pulse width modulation mode to encode, a time frame period is 1s, and 100 code elements are contained, and each code element period is 10ms.
[0019] The data processing module extracts valid year, day, hour, minute and second information bits in the 64-bit BCD time code, recombines them according to the B code encoding format, and stores them in a 100-bit register w_code_10msecond. The module counts at a 100MHz clock, generates a millisecond enable signal en msconsend, a 10ms enable signal en_10msconsend and a second enable signal en_second. According to the 10ms enable signal en_10msconsend and the second enable signal en_second, the value of each bit in the register w_code_10msecond is extracted, and then each bit value in the w_code_10msecond is converted into a B code serial code output according to the millisecond enable signal en msconsend and the code element definition, to complete the B code conversion.
[0020] In order to verify the correctness of the B code generation device, the generated B code is connected to a B code decoding device (target device), and the decoded time is received by the upper computer.
Claims
1. A B-code generator for use in an embedded test environment, characterized by: The system comprises a host computer and an FPGA, the host computer and the FPGA are connected through a serial port, the host computer is provided with a system time sending module, the FPGA is provided with a serial port communication module, a time code protocol analysis module and a B code generating module, wherein the B code generating module comprises a time keeping module, a time conversion module and a data processing module; the output of the serial port communication module is connected with the input of the time code protocol analysis module, the output of the time code protocol analysis module is connected with the input of the time keeping module, the output of the time keeping module is connected with the input of the time conversion module, and the output of the time conversion module is connected with the input of the data processing module.
2. The B-code generator for use in an embedded test environment according to claim 1, characterized in that: The host computer is further provided with a decoded time receiving module.