Pixel circuit and display panel
By employing a compensation unit and capacitor coupling writing method in the pixel circuit of the OLED display panel, the problem of slow data signal writing speed at high refresh rates is solved, achieving fast data signal transmission and improved image quality stability.
Patent Information
- Application Number
- CN202520300225.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2035-02-24
AI Technical Summary
In existing technologies, OLED display panels suffer from problems such as low grayscale uniformity degradation and image retention due to insufficient writing time at high refresh rates, and the data signal writing speed is relatively slow.
A pixel circuit is employed, which controls the threshold voltage of the first transistor through a compensation unit and uses the first capacitor to achieve data signal coupling and writing. Combined with a dual-gate transistor, leakage current is reduced, thereby improving the accuracy and stability of data signal transmission.
After threshold voltage compensation, data signals are transmitted via coupling writing, which improves the writing speed of data signals and ensures the quality and stability of the displayed image.
Smart Images
Figure CN223797126U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display driver technology, specifically to a pixel circuit and a display panel. Background Technology
[0002] Organic light-emitting diodes (OLEDs) are a display technology based on electroluminescence from organic materials. They have core advantages such as self-illumination, high contrast, wide viewing angle, and flexibility. Each pixel is independently driven by a thin-film transistor (TFT) backplane. The quality of the displayed image is related to the stability of the power supply voltage. However, the voltage drop (IR drop) effect is common in pixel circuits. Therefore, it is usually necessary to compensate for the TFT threshold voltage (Vth) to improve the stability of the displayed image.
[0003] Currently, pixel circuits can use diode charging compensation Vth, which utilizes the diode's conduction characteristics to achieve dynamic compensation. However, the non-linear conduction characteristics of diodes can easily lead to slow data signal writing speeds. At ultra-high frequency refresh rates (such as 480Hz and above), insufficient writing time can easily cause problems such as deterioration of low grayscale uniformity or ghosting in the displayed image, resulting in poor display quality.
[0004] Therefore, improving the writing speed of data signals in pixel circuits is a problem that urgently needs to be solved. Utility Model Content
[0005] In view of the shortcomings of the prior art, this application provides a pixel circuit and a display panel.
[0006] In a first aspect, this application provides a pixel circuit, comprising:
[0007] Light-emitting unit;
[0008] The data writing unit is used to receive data signals;
[0009] The first transistor includes a control electrode, a first electrode connected in series with the light-emitting unit, and a second electrode.
[0010] A compensation unit, connected to the first transistor, is used to compensate the threshold voltage of the first transistor.
[0011] The first capacitor includes a first end connected to the data writing unit and a second end connected to the control electrode of the first transistor, so as to couple the data signal into the control electrode of the first transistor.
[0012] Optionally, the data writing unit includes a second transistor and a third transistor;
[0013] The second transistor includes a control electrode that receives the first scan signal, a first electrode that receives the data signal, and a second electrode that is connected to the first terminal of the first capacitor;
[0014] The third transistor includes a control electrode connected to a second scan signal, a first electrode connected to a first reset signal, and a second electrode connected to a first terminal of the first capacitor.
[0015] Optionally, the compensation unit includes a fourth transistor;
[0016] The fourth transistor includes a control electrode that receives the second scan signal, a first electrode that is connected to the second electrode of the first transistor, and a second electrode that is connected to the control electrode of the first transistor.
[0017] Optionally, the second transistor, the third transistor, and the fourth transistor are dual-gate transistors.
[0018] Optionally, it also includes a light-emitting control unit, which includes a fifth transistor and a sixth transistor;
[0019] The fifth transistor includes a control electrode that receives a first light emission control signal, a first electrode that receives a first power supply signal, and a second electrode that is connected to the first electrode of the first transistor.
[0020] The sixth transistor includes a control electrode that receives the second light-emitting control signal, a first electrode that is connected to the second electrode of the first transistor, and a second electrode that is connected to the anode of the light-emitting unit.
[0021] Optionally, it also includes a reset unit connected to the first transistor and the light-emitting unit, for resetting the series circuit in which the light-emitting unit is located.
[0022] Optionally, the reset unit includes a seventh transistor and an eighth transistor;
[0023] The seventh transistor includes a control electrode that receives a third scan signal, a first electrode that receives a second reset signal, and a second electrode that is connected to the first transistor.
[0024] The eighth transistor includes a control electrode that receives a reset control signal, a first electrode that receives a third reset signal, and a second electrode that is connected to the anode of the light-emitting unit.
[0025] Optionally, the reset unit further includes a ninth transistor;
[0026] The ninth transistor includes a control electrode connected to a third scan signal, a first electrode connected to a second reset signal, and a second electrode connected to the first transistor.
[0027] Optionally, it may also include a voltage regulator unit connected to the first capacitor, the voltage regulator unit including a second capacitor;
[0028] The first end of the second capacitor is connected to the first power signal, and the second end is connected to the first end of the first capacitor.
[0029] Secondly, in one embodiment, this application provides a display panel including the pixel circuit described above.
[0030] In summary, this application firstly achieves rapid compensation of the threshold voltage of the control electrode of the first transistor by controlling the switching between the second electrode and the control electrode of the first transistor through a compensation unit. After compensation, the data signal is coupled and written through the first capacitor, allowing the data signal to be directly transmitted to the control electrode of the first transistor in the form of a voltage jump. Thus, the voltage drop effect is offset after threshold voltage compensation, and the data signal is transmitted via coupled writing, improving the writing speed of the data signal while ensuring the quality of the displayed image. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a schematic diagram of a pixel circuit in one embodiment of this application;
[0033] Figure 2 This is a schematic diagram of a pixel circuit in another embodiment of this application;
[0034] Figure 3 This is a schematic diagram of the circuit connection of the pixel circuit in one embodiment of this application;
[0035] Figure 4 This is a schematic diagram of the circuit connection of the pixel circuit in another embodiment of this application;
[0036] Figure 5 This is a timing waveform diagram of the pixel circuit operation in one embodiment of this application;
[0037] Figure 6 This is a timing waveform diagram of the pixel circuit operation in another embodiment of this application.
[0038] Explanation of reference numerals in the attached diagram: 1. Light-emitting unit; 2. Data writing unit; 3. Compensation unit; 4. Light-emitting control unit; 5. Reset unit; 6. Voltage regulating unit. Detailed Implementation
[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0040] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified. In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to implement and use this application. In the following description, details are set forth for illustrative purposes. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid unnecessary detail that would obscure the description of this application. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.
[0041] Firstly, such as Figure 1 As shown, in one embodiment, this application provides a pixel circuit, which includes a light-emitting unit 1, a data writing unit 2, a first transistor T1, a compensation unit 3, and a first capacitor C1. The data writing unit 2 is used to receive data signals. The first transistor T1 includes a control electrode, a first electrode connected in series with the light-emitting unit 1, and a second electrode. The compensation unit 3 is connected to the first transistor T1 and is used to compensate for the threshold voltage of the first transistor T1. The first capacitor C1 includes a first terminal connected to the data writing unit 2 and a second terminal connected to the control electrode of the first transistor T1, so as to couple the data signal into the control electrode of the first transistor T1.
[0042] As an example, compensation unit 3 compensates for the threshold voltage of the first transistor T1 by controlling the switching between the second electrode and the gate of the first transistor T1. Taking the first electrode of the first transistor T1 connected to the first power supply signal as an example, the compensation unit 3 first controls the first transistor T1 to conduct, short-circuiting the second electrode and the control electrode of the first transistor T1. At this time, the potential of the second electrode of the first transistor T1 is equal to the potential of the control electrode of the first transistor T1. The conduction of the first transistor T1 requires that its gate-source voltage be less than the threshold voltage, i.e., VGS1 = VS1 - VG1 ≤ Vth. Wherein, VGS1 is the gate-source voltage of the first transistor T1, VS1 is the potential of the first electrode of the first transistor T1, VG1 is the potential of the control electrode of the first transistor T1, and Vth is the threshold voltage. Since the first electrode of the first transistor T1 is connected to the first power supply signal VDD, during the conduction process of the first transistor T1, constrained by its conduction condition, the potential of the control electrode of the first transistor T1 will gradually stabilize to VG1 = VDD - Vth. Then, the first transistor T1 is disconnected by the controller of the compensation unit 3. Since there is a parasitic capacitance in the first transistor T1, the control electrode potential of the first transistor T1 is suspended at VDD-Vth due to charge conservation, thereby realizing the compensation of the threshold voltage of the first transistor T1.
[0043] As an example, coupled writing refers to writing a data signal to the control electrode of the first transistor T1 through the coupling effect of the first capacitor C1. The coupling effect means that when the voltage at one end of the first capacitor C1 changes abruptly, the voltage at the other end will change by the same magnitude due to the charge conservation property of the capacitor. That is, when the data signal is transmitted to the first end of the first capacitor C1, a sudden change in the amplitude of the data signal will occur at the first end of the first capacitor C1, and the same sudden change will occur at the second end of the first capacitor C1. Since the second end of the second capacitor C2 is connected to the control electrode of the first transistor T1, the data signal is written to the control electrode of the first transistor T1 in a coupled manner.
[0044] In the above embodiment, firstly, the compensation unit 3 controls the switching between the second electrode and the control electrode of the first transistor T1, thereby achieving rapid compensation of the threshold voltage of the control electrode of the first transistor T1. After compensation, the data signal is coupled and written through the first capacitor C1, allowing the data signal to be directly transmitted to the control electrode of the first transistor T1 in the form of a voltage jump. In this way, the voltage drop effect is offset after threshold voltage compensation, and the data signal is transmitted in a coupled writing manner, which improves the writing speed of the data signal while ensuring the quality of the displayed image.
[0045] In some implementations, the data writing unit 2 includes a second transistor T2 and a third transistor T3. The second transistor T2 includes a control electrode connected to the first scan signal SCAN1, a first electrode connected to the data signal, and a second electrode connected to the first terminal of the first capacitor C1. The third transistor T3 includes a control electrode connected to the second scan signal SCAN2(n), a first electrode connected to the first reset signal VI1, and a second electrode connected to the first terminal of the first capacitor C1.
[0046] Combination Figure 3 The second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first terminal of the first capacitor C1 are connected to the first node D. SCAN1(n) represents the first scan signal SCAN1, which is used to control the writing of the data signal; SCAN2(n) represents the second scan signal SCAN2(n), which is used to reset the potential of the first node D and shift the data signal to be within the range required for display.
[0047] As an example, taking P-type transistors T2 and T3 as examples, firstly, the second scan signal SCAN2(n) is set to a low level to control the conduction of the third transistor T3. The first reset signal VI1 is connected to the first node D, thereby resetting the potential of the first node D to the amplitude of the first reset signal VI1. Then, the second transistor T2 is set to a low level to control the conduction of the first transistor, and the data signal is transmitted to the first node D. At this time, the potential change of the first node D can be expressed as ΔV = Vdata - Vvi1; where Vdata represents the amplitude of the data signal, and Vvi1 represents the amplitude of the first reset signal VI1. Since the first terminal of the first capacitor C1 is connected to the first node D, the voltage change at the first terminal of the first capacitor C1 is ΔV, causing the voltage at the second terminal of the first capacitor C1 to also change by ΔV, and this change ΔV is transmitted to the control electrode of the first transistor T1.
[0048] In the above embodiment, the first terminal of the first capacitor C1 is reset by the third transistor T3, which avoids the floating potential of the first capacitor C1 from interfering with the writing of the data signal. At the same time, the potential of the first capacitor C1 is reset to the amplitude of the first reset signal VI1, so that after the data signal is written, the voltage change at the first terminal of the first capacitor C1 is the difference between the amplitude of the data signal and the amplitude of the first reset signal VI1, thereby shifting the amplitude of the data signal to adjust the data signal to the required amplitude range. Finally, the data signal is written by utilizing the coupling effect of the first capacitor C1.
[0049] In some embodiments, the compensation unit 3 includes a fourth transistor T4. The fourth transistor T4 includes a control electrode connected to the second scan signal SCAN2(n), a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the control electrode of the first transistor T1.
[0050] Combination Figure 3 The second terminal of the first capacitor C1, the second electrode of the fourth transistor T4, and the control electrode of the first transistor T1 are connected to the second node Q. Taking the fourth transistor T4 as a P-type transistor as an example, when the second scan signal SCAN2(n) is at a low level, the fourth transistor T4 is turned on. At this time, the second electrode and the control electrode of the first transistor T1 are shorted through the fourth transistor T4. When the second scan signal SCAN2(n) is at a low-high level, the fourth transistor T4 is turned off, thereby disconnecting the connection between the second electrode and the control electrode of the first transistor T1. This allows the fourth transistor T4 to switch the connection between the second electrode and the control electrode of the first transistor T1, thereby compensating for the threshold voltage of the first transistor T1.
[0051] As an example, the second transistor T2, the third transistor T3, and the fourth transistor T4 are dual-gate transistors. Since the first node D and the second node Q are crucial for controlling the writing of data signals, the transistors associated with the first node D and the second node Q should have higher performance. Therefore, the use of dual-gate transistors for the second transistor T2, the third transistor T3, and the fourth transistor T4 reduces leakage current, minimizing the impact of leakage current on the potentials of the first node D and the second node Q, thus making the data signal transmission more accurate and stable.
[0052] Reference Figure 2 In some embodiments, the pixel circuit further includes a light-emitting control unit 4, which includes a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 includes a control electrode connected to a first light-emitting control signal EM1, a first electrode connected to a first power supply signal, and a second electrode connected to the first electrode of the first transistor T1. The sixth transistor T6 includes a control electrode connected to a second light-emitting control signal EM2, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the anode of the light-emitting unit 1.
[0053] As an example, taking the fifth transistor T5 and the sixth transistor T6 as P-type transistors, when the first light-emitting control signal EM1 is at a low level, the fifth transistor T5 is turned on, and the first power supply signal is transmitted to the first electrode of the first transistor T1 through the fifth transistor T5. After the data signal is written to the control electrode of the first transistor T1, the first transistor T1 is turned on in the linear region. When the second light-emitting control signal EM2 is at a low level, the sixth transistor T6 is turned on, and the sixth transistor T6 connects the second electrode of the first transistor T1 with the anode of the light-emitting unit 1, causing the light-emitting unit 1 to start emitting light.
[0054] As an example, the cathode of the light-emitting unit 1 is connected to a second power supply signal. The amplitude of the second power supply signal is lower than that of the first power supply signal, so that after the first power supply signal flows through the fifth transistor T5, the first transistor T1 and the sixth transistor T6 in sequence, the potential of the anode of the light-emitting unit 1 is higher than that of the cathode of the light-emitting unit 1, thereby enabling the light-emitting unit 1 to conduct light.
[0055] In the above embodiment, the fifth transistor T5 and the sixth transistor T6 are controlled by the first light-emitting control signal EM1 and the second light-emitting control signal EM2, respectively. When the fifth transistor T5 and the sixth transistor T6 are turned on at the same time, the light-emitting unit 1 will emit light. When one of the fifth transistor T5 and the sixth transistor T6 is turned off, the light-emitting unit 1 will not emit light, thereby realizing the control of the light-emitting device.
[0056] Reference Figure 3 ,and Figure 4 In some embodiments, the pixel circuit further includes a reset unit 5 connected to the first transistor T1 and the light-emitting unit 1, for resetting the series circuit in which the light-emitting unit 1 is located.
[0057] As an example, the series circuit containing the light-emitting unit 1 is a circuit composed of the fifth transistor T5, the first transistor T1, and the sixth transistor T6. The fifth transistor T5 and the first transistor T1 are connected to the third node A, the first transistor T1 and the sixth transistor T6 are connected to the fourth node B, and the sixth transistor T6 and the anode of the light-emitting unit 1 are connected to the fifth node C. The reset unit 5 resets the third node A, the fourth node B, and the fifth node C respectively.
[0058] Reference Figure 3As one embodiment of the reset unit 5, the reset unit 5 includes a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 includes a control electrode connected to the third scan signal SCAN2(n-6), a first electrode connected to the second reset signal VI2, and a second electrode connected to the first transistor T1. The eighth transistor T8 includes a control electrode connected to the reset control signal SN1, a first electrode connected to the third reset signal VI3, and a second electrode connected to the anode of the light-emitting unit 1.
[0059] As an example, SCAN2(n-6) represents the third scan signal SCAN2(n-6), which is cascaded with the second scan signal SCAN2(n); VI2 represents the second reset signal VI2; and VI3 represents the third reset signal VI3. When resetting the third node A and the fourth node B, the second scan signal SCAN2(n) and the third scan signal SCAN2(n-6) are simultaneously at a low level, causing the fourth transistor T4 to conduct, which in turn controls the first transistor T1 to conduct. Simultaneously, the fifth transistor T5 conducts, so the second reset signal VI2 is first transmitted to the fourth node B through the fifth transistor T5, resetting the fourth node B. Then, the second reset signal VI2 of the fourth node B is used to reset the third node A through the first transistor T1, pulling the potential of the third node A down to the second reset signal VI2, thus achieving the reset of both the third node A and the fourth node B. Finally, the reset control signal SN1 is set to a low level, which turns on the eighth transistor T8 and transmits the third reset signal VI3 to the fifth node C, thereby resetting the fifth node C.
[0060] Reference Figure 4 As another embodiment of the reset unit 5, the reset unit 5 further includes a ninth transistor T9. The ninth transistor T9 includes a control electrode connected to the third scan signal SCAN2(n-6), a first electrode connected to the second reset signal VI2, and a second electrode connected to the first transistor T1.
[0061] As an example, firstly, the second scan signal SCAN2(n) and the third scan signal SCAN2(n-6) are simultaneously controlled to a low level, so that the first transistor T1 and the ninth transistor T9 are turned on. This allows the second reset signal VI2 to be transmitted to the fourth node B through the ninth transistor T9, resetting the fourth node B. Then, the second reset signal VI2 at the fourth node B is transmitted through the first transistor T1 to reset the third node A, pulling the potential of the third node A down to the second reset signal VI2, thus resetting both the third node A and the fourth node B. Next, the third scan signal SCAN2(n-6) and the second light emission control signal EM2 are simultaneously controlled to a low level, so that the ninth transistor T9 and the sixth transistor T6 are simultaneously turned on. This allows the second reset signal VI2 to be transmitted to the fourth node B through the ninth transistor T9, and then from the fourth node B through the sixth transistor T6 to the fifth node C, thus resetting the fifth node C.
[0062] In some embodiments, the pixel circuit further includes a voltage regulator unit 6 connected to the first capacitor C1, and the voltage regulator unit 6 includes a second capacitor C2. The first terminal of the second capacitor C2 is connected to a first power signal, and the second terminal is connected to the first terminal of the first capacitor C1.
[0063] In the above embodiment, the first terminal of the second capacitor C2 is connected to a constant voltage first power supply signal, thereby stabilizing the voltage across the second capacitor C2, thereby stabilizing the first terminal of the first capacitor C1 connected thereto, so as to provide a reference voltage to the first capacitor C1 so that the first capacitor C1 can determine the amount of sudden voltage change.
[0064] This disclosure exemplarily describes the operation of a pixel circuit using two different reset methods. For the first reset method, the timing sequence of the pixel circuit is as follows: Figure 5 As shown.
[0065] First, during time period t1, both the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a high level, and the light-emitting unit 1 is turned off.
[0066] During time period t2, the third scan signal SCAN2(n-6) is in a low-level state, which controls the fifth transistor T5 to turn on and reset the second node B;
[0067] Then, during time period t3, the second scan signal SCAN2(n) and the third scan signal SCAN2(n-6) are both at a low level, controlling the seventh transistor T7 and the first transistor T1 to turn on, thereby controlling the third node A and the fourth node B to reset. At the same time, the third transistor T3 turns on, controlling the first node D to reset.
[0068] During the t4 period, the first light emission control signal EM1 is in a low-level state, which controls the sixth transistor T6 to turn on and transmit the first power supply signal to the first electrode of the first transistor T1.
[0069] Then, during the t5 period, the second scan signal SCAN2(n) is in a low-level state to control the fourth transistor T4 to turn on. The first power supply signal of the first electrode of the first transistor T1 is transmitted through the first transistor T1 and the fourth transistor T4 to the control electrode of the first transistor T1, and the control electrode potential of the first transistor T1 is adjusted to VDD-Vth, thereby completing the compensation of the threshold voltage of the first transistor T1.
[0070] During the t6 period, the first scan signal SCAN1 is at a low level, controlling the second transistor T2 to turn on. The data signal is written to the first node D, and a change in amplitude of Vdata-Vvi1 is generated at the first node D. This change is transmitted to the control electrode of the first transistor T1 through the coupling of the first capacitor C1, ultimately making the control electrode potential of the first transistor T1 VDD-Vth+Vdata-Vvi1, thus completing the writing of the data signal.
[0071] During time period t7, the reset control signal SN1 is at a low level, controlling the eighth transistor T8 to conduct and reset the anode potential of the light-emitting unit 1. Finally, after time period t7, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both at a low level, and the fifth transistor T5, the first transistor T1, and the sixth transistor T6 are all turned on simultaneously. The conduction level of the first transistor T1 is controlled by its control electrode potential, thereby realizing the light emission of the light-emitting unit 1.
[0072] For the second reset method, the timing sequence of the pixel circuit is as follows: Figure 6 As shown.
[0073] First, during period a1, the third scan signal SCAN2(n-6) and the second light emission control signal EM2 are at a low level, the ninth transistor T9 and the sixth transistor T6 are turned on, the second reset signal VI2 resets the fourth node B through the ninth transistor T9, and resets the fifth node C through the sixth transistor T6.
[0074] During time period a2, the second scan signal SCAN2(n) and the third scan signal SCAN2(n-6) are both at a low level, controlling the seventh transistor T7 and the first transistor T1 to turn on, thereby controlling the third node A and the fourth node B to reset. At the same time, the third transistor T3 turns on, controlling the first node D to reset.
[0075] During the a3-a5 period, its working process is similar to Figure 5The t4-t6 time period described in the time series is consistent and will not be repeated here.
[0076] Secondly, in one embodiment, this application provides a display panel including the pixel circuit described above.
[0077] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0078] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0079] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A pixel circuit, characterized by comprising: include: Light-emitting unit; The data writing unit is used to receive data signals; The first transistor includes a control electrode, a first electrode connected in series with the light-emitting unit, and a second electrode. A compensation unit, connected to the first transistor, is used to compensate the threshold voltage of the first transistor. The first capacitor includes a first end connected to the data writing unit and a second end connected to the control electrode of the first transistor, so as to couple the data signal into the control electrode of the first transistor.
2. The pixel circuit of claim 1, wherein, The data writing unit includes a second transistor and a third transistor; The second transistor includes a control electrode that receives the first scan signal, a first electrode that receives the data signal, and a second electrode that is connected to the first terminal of the first capacitor; The third transistor includes a control electrode connected to a second scan signal, a first electrode connected to a first reset signal, and a second electrode connected to a first terminal of the first capacitor.
3. The pixel circuit of claim 2, wherein, The compensation unit includes a fourth transistor; The fourth transistor includes a control electrode that receives the second scan signal, a first electrode that is connected to the second electrode of the first transistor, and a second electrode that is connected to the control electrode of the first transistor.
4. The pixel circuit of claim 3, wherein, The second transistor, the third transistor, and the fourth transistor are dual-gate transistors.
5. The pixel circuit according to claim 1, characterized in that, It also includes a light-emitting control unit, which includes a fifth transistor and a sixth transistor; The fifth transistor includes a control electrode that receives a first light emission control signal, a first electrode that receives a first power supply signal, and a second electrode that is connected to the first electrode of the first transistor. The sixth transistor includes a control electrode that receives the second light-emitting control signal, a first electrode that is connected to the second electrode of the first transistor, and a second electrode that is connected to the anode of the light-emitting unit.
6. The pixel circuit according to claim 1, characterized in that, It also includes a reset unit connected to the first transistor and the light-emitting unit, used to reset the series circuit in which the light-emitting unit is located.
7. The pixel circuit according to claim 6, characterized in that, The reset unit includes a seventh transistor and an eighth transistor; The seventh transistor includes a control electrode that receives a third scan signal, a first electrode that receives a second reset signal, and a second electrode that is connected to the first transistor. The eighth transistor includes a control electrode that receives a reset control signal, a first electrode that receives a third reset signal, and a second electrode that is connected to the anode of the light-emitting unit.
8. The pixel circuit according to claim 6, characterized in that, The reset unit further includes a ninth transistor; The ninth transistor includes a control electrode connected to a third scan signal, a first electrode connected to a second reset signal, and a second electrode connected to the first transistor.
9. The pixel circuit according to claim 5, characterized in that, It also includes a voltage regulator unit connected to the first capacitor, the voltage regulator unit including a second capacitor; The first end of the second capacitor is connected to the first power signal, and the second end is connected to the first end of the first capacitor.
10. A display panel, characterized in that, include: The pixel circuit as described in any one of claims 1 to 9.