Digital cross connection module for performing time slot separation on PCM (Pulse Code Modulation) voice signal

Abstract

The utility model discloses a digital cross connection module for time slot separation of PCM voice signals, which belongs to the technical field of telecommunication and comprises a power module, a PCM interface, a time slot multiplexing unit, an FPGA (field programmable gate array) controller, a USB (universal serial bus) module, an SATA (serial advanced technology attachment) module, a clock management chip, a digital signal processing chip, a high-broadband interface chip, a USB interface, an SATA interface, an I2S interface and a high-broadband interface. The technical problems of performing time slot multiplexing on four paths of I2S signals, providing multi-interface technologies such as a USB, an SATA and a high-bandwidth interface and being capable of being externally connected with an SATA interface storage device are solved, the system adapts to different application scenes, the audio processing capacity of the system is improved, the signal transmission efficiency is improved, the hardware cost is reduced, the compatibility and the stability of the system are enhanced, the independent module design is adopted, and the cost is reduced. Therefore, the system can be flexibly expanded, and more input channels are added or a data transmission mode is improved.

Description

Technical Field

[0001] This utility model belongs to the field of telecommunications technology, and in particular relates to a digital cross-connect module for time slot separation of PCM voice signals. Background Technology

[0002] PCM (Pulse Code Modulation) is a widely used technology for digitizing voice signals, primarily in areas such as telephone communication and audio sampling. Traditional PCM voice data processing methods typically rely on fixed hardware architectures, such as DSP chips or MCUs, for signal processing.

[0003] The shortcomings of existing technology:

[0004] Limited interface: Most traditional systems only support TDM interfaces, which restricts data storage and transmission methods and prevents direct interaction with modern storage devices (such as SATA hard drives) or computers (such as USB interfaces).

[0005] High hardware resource consumption: Traditional solutions often use dedicated TDM switching chips, which have low flexibility, are difficult to upgrade, and have a large hardware size.

[0006] Limited computing power: When using an MCU or a single DSP for processing, the computing power is insufficient and it is difficult to adapt to complex audio processing needs, such as advanced functions like noise reduction and echo cancellation. Utility Model Content

[0007] The purpose of this invention is to provide a digital cross-connect module that performs time-slot separation of PCM voice signals, solving the technical problem of time-slot multiplexing of 4 I2S signals, providing multiple interface technologies such as USB, SATA, and high-bandwidth interfaces, and enabling external connection of SATA interface storage devices.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] A digital cross-connect module for time-slot separation of PCM voice signals includes a power module, a PCM interface, a time-slot multiplexing unit, an FPGA controller, a USB module, a SATA module, a clock management chip, a digital signal processing chip, a high-bandwidth interface chip, a USB interface, a SATA interface, an I2S interface, and a high-bandwidth interface.

[0010] The PCM interface includes four I2S signal input interfaces, all of which are connected to a time slot multiplexing unit, which is connected to the FPGA controller.

[0011] The USB module, SATA module, clock management chip, digital signal processing chip, and high-bandwidth interface chip are all connected to the FPGA controller.

[0012] The USB interface connects to the USB module, the SATA interface connects to the SATA module, the I2S interface connects to the digital signal processing chip, and the high-bandwidth interface connects to the high-bandwidth interface chip.

[0013] The power module supplies power to the time slot multiplexing unit, FPGA controller, USB module, SATA module, clock management chip, digital signal processing chip and high-bandwidth interface chip.

[0014] Preferably, the FPGA controller is model XC7A100T-2FGG484I, the USB module is model USB2517, the SATA module is model 88SE9130, the clock management chip is model CDCE913, the digital signal processing chip is model TMS320C5517 DSP chip, and the high-bandwidth interface chip is model LAN8720.

[0015] Preferably, the power supply module includes a 5V regulator and a 3.3V regulator. The 5V power output from the 5V regulator powers the time slot multiplexing unit, and the 3.3V power output from the 3.3V regulator powers the FPGA controller, USB module, SATA module, clock management chip, digital signal processing chip, and high-bandwidth interface chip.

[0016] Preferably, the four I2S signal input interfaces are interface J1, interface J2, interface J3 and interface J4;

[0017] The time slot multiplexing unit includes digital multiplexer IC1, digital multiplexer IC2, digital multiplexer IC3, level converter U1, level converter U2 and level converter U3;

[0018] The input terminals of the digital multiplexer IC1 are connected to the BCLK terminals of interface J1, interface J2, interface J3, and interface J4. The output terminals and control terminals of the digital multiplexer IC1 are connected to different I / O ports of the FPGA controller through level converter U1.

[0019] The input terminals of the digital multiplexer IC2 are connected to the SD terminals of interface J1, interface J2, interface J3, and interface J4. The output terminals and control terminals of the digital multiplexer IC2 are connected to different I / O ports of the FPGA controller through level converter U2.

[0020] The input terminals of the digital multiplexer IC3 are connected to the LRCLK terminals of interface J1, interface J2, interface J3, and interface J4. The output terminals and control terminals of the digital multiplexer IC3 are connected to different I / O ports of the FPGA controller through level converter U3.

[0021] Preferably, the digital multiplexer IC1, digital multiplexer IC2 and digital multiplexer IC3 are all model 74LS153N, and all three are powered by a 5V power supply.

[0022] Level converters U1, U2, and U3 are all model number TXB0108PWR voltage level converters, and are used to convert 5V level signals to 3.3V level signals.

[0023] Preferably, pin 1 of interface J1, pin 1 of interface J2, pin 1 of interface J3 and pin 1 of interface J4 are all connected to the ground wire via ferrite bead R0.

[0024] This utility model discloses a digital cross-connect module for time-slot separation of PCM voice signals. It solves the technical problems of time-slot multiplexing of four I2S signals, providing multiple interface technologies such as USB, SATA, and high-bandwidth interfaces, and enabling connection to external SATA interface storage devices. Utilizing USB, SATA, and high-bandwidth interfaces, PCM data can be stored on a hard drive, transmitted to a computer via USB, or transmitted over long distances via a high-speed digital interface, adapting to different application scenarios. Through its hardware architecture, users can perform secondary development; for example, the FPGA can handle time-slot separation and data management, while the DSP can specifically process voice signals, such as noise reduction and echo cancellation, improving the system's audio processing capabilities. The CDCE913 clock management chip ensures clock synchronization of all modules, improving data processing stability. Time-slot multiplexing of four I2S signals via a MUX improves signal transmission efficiency and reduces hardware costs. The TXB0108PWR is used for level conversion, allowing the FPGA to directly control the MUX and I2S signals, enhancing system compatibility and stability. The independent module design allows for flexible system expansion, adding more input channels or improving data transmission methods. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the present invention.

[0026] Figure 2 This is a circuit diagram of the PCM interface of this utility model;

[0027] Figure 3 This is a circuit diagram of the time slot multiplexing unit of this utility model connected to the BCLK signal;

[0028] Figure 4 This is a circuit diagram of the time slot multiplexing unit of this utility model connected to the LRCLK signal;

[0029] Figure 5 This is a circuit diagram of the time slot multiplexing unit of this utility model connected to the SD signal. Detailed Implementation

[0030] Depend on Figures 1-5 The digital cross-connect module for time-slot separation of PCM voice signals shown includes a power module, a PCM interface, a time-slot multiplexing unit, an FPGA controller, a USB module, a SATA module, a clock management chip, a digital signal processing chip, a high-bandwidth interface chip, a USB interface, a SATA interface, an I2S interface, and a high-bandwidth interface.

[0031] The FPGA controller is model XC7A100T-2FGG484I, the USB module is model USB2517, the SATA module is model 88SE9130, the clock management chip is model CDCE913, the digital signal processing chip is model TMS320C5517 DSP chip, and the high-bandwidth interface chip is model LAN8720.

[0032] The PCM interface includes four I2S signal input interfaces, all of which are connected to a time slot multiplexing unit, which is connected to the FPGA controller.

[0033] The four I2S signal input interfaces are J1, J2, J3 and J4.

[0034] Pin 1 of interface J1, pin 1 of interface J2, pin 1 of interface J3, and pin 1 of interface J4 are all connected to the ground wire via ferrite bead R0.

[0035] In this embodiment, the signal output by the external PCM device is an I2S interface, specifically including the following signals:

[0036] SD (Serial Data): PCM data stream;

[0037] BCLK (Bit Clock): Data Clock;

[0038] LRCLK (Left-Right Clock): Frame synchronization signal;

[0039] Pin 4 of interface J1 is connected to the BCLK1 signal of the first PCM signal, pin 3 is connected to the SD1 signal of the first PCM signal, pin 2 is connected to the LRCLK1 signal of the first PCM signal, and pin 1 is connected to the GND signal of the first PCM signal.

[0040] Similarly, interface J2 connects to the second PCM signal, and its circuit connection network numbers are BCLK2, SD2, and LRCLK2, respectively;

[0041] Interface J3 connects to the third PCM signal, and its circuit connection network numbers are BCLK3, SD3, and LRCLK3 respectively;

[0042] Interface J4 connects to the fourth PCM signal, and its circuit connection network numbers are BCLK4, SD4, and LRCLK4 respectively.

[0043] In this embodiment, the four PCM signals constitute a modular design, which can be expanded modularly by adding interfaces, digital multiplexers, and level converters.

[0044] The time slot multiplexing unit includes digital multiplexer IC1, digital multiplexer IC2, digital multiplexer IC3, level converter U1, level converter U2 and level converter U3;

[0045] The input terminals of the digital multiplexer IC1 are connected to the BCLK terminals of interface J1, interface J2, interface J3, and interface J4. The output terminals and control terminals of the digital multiplexer IC1 are connected to different I / O ports of the FPGA controller through level converter U1.

[0046] In this embodiment, the circuit connection network of the digital multiplexer IC1 is as follows:

[0047] BCLK1 of interface J1 is connected to the MUX1-B1 input of digital multiplexer IC1;

[0048] The BCLK2 of interface J2 is connected to the MUX1-B2 input of digital multiplexer IC1;

[0049] The BCLK3 of interface J3 is connected to the MUX1-B3 input of digital multiplexer IC1;

[0050] BCLK4 of interface J1 is connected to the MUX1-B4 input of digital multiplexer IC1;

[0051] The control terminals of the digital multiplexer IC1 include MUX1-L1, MUX1-L2, MUX1-1G, and MUX1-2G. The output terminals of the digital multiplexer IC1 include MUX1-OUTB. MUX1-L1, MUX1-L2, MUX1-1G, MUX1-2G, and MUX1-OUTB are connected to pins A5, A6, A7, A8, and A1 of the level converter U1, respectively. Pins B5, B6, B7, B8, and B1 of the level converter U1 are connected to different I / O ports of the FPGA, with network numbers IO-PIN-MUX1-L1, IO-PIN-MUX1-L2, IO-PIN-MUX1-1G, IO-PIN-MUX1-2G, and IO-PIN-BCLK.

[0052] The digital multiplexer IC1 is mainly responsible for the time slot multiplexing of the BCLK signal of the I2S interface. It can select the channel from 4 to 1 through the control signal of the FPGA. The level converter U1 is used to convert the 5V level to the 3.3V level applicable to the FPGA.

[0053] The input terminals of the digital multiplexer IC2 are connected to the SD terminals of interface J1, interface J2, interface J3, and interface J4. The output terminals and control terminals of the digital multiplexer IC2 are connected to different I / O ports of the FPGA controller through level converter U2.

[0054] The circuit connection principle of digital multiplexer IC2 is similar to that of digital multiplexer IC1. Digital multiplexer IC1 is mainly responsible for the time slot multiplexing of the LRCLK signal of the I2S interface.

[0055] The input terminals of the digital multiplexer IC3 are connected to the LRCLK terminals of interface J1, interface J2, interface J3, and interface J4. The output terminals and control terminals of the digital multiplexer IC3 are connected to different I / O ports of the FPGA controller through level converter U3.

[0056] The circuit connection principle of digital multiplexer IC3 is similar to that of digital multiplexer IC1. Digital multiplexer IC3 is mainly responsible for the time slot multiplexing of SD signals of I2S interface.

[0057] By selecting the time slots of digital multiplexers IC1, IC2, and IC3, the three I2S signals can be turned on individually, greatly facilitating the development and writing of secondary programs. Furthermore, the circuit structure forms a modular design of 4 channels per group, which can be modularly expanded according to customer needs, thus facilitating the development and design of secondary circuits.

[0058] The digital multiplexer IC1, digital multiplexer IC2 and digital multiplexer IC3 are all model 74LS153N, and they are all powered by a 5V power supply.

[0059] Level converters U1, U2, and U3 are all model number TXB0108PWR voltage level converters, and are used to convert 5V level signals to 3.3V level signals.

[0060] The USB module, SATA module, clock management chip, digital signal processing chip, and high-bandwidth interface chip are all connected to the FPGA controller.

[0061] The USB interface connects to the USB module, the SATA interface connects to the SATA module, the I2S interface connects to the digital signal processing chip, and the high-bandwidth interface connects to the high-bandwidth interface chip.

[0062] The power module supplies power to the time slot multiplexing unit, FPGA controller, USB module, SATA module, clock management chip, digital signal processing chip and high-bandwidth interface chip.

[0063] The power module includes a 5V regulator and a 3.3V regulator. The 5V power output from the 5V regulator powers the time slot multiplexing unit, and the 3.3V power output from the 3.3V regulator powers the FPGA controller, USB module, SATA module, clock management chip, digital signal processing chip, and high-bandwidth interface chip.

[0064] In this embodiment, the 5V regulator is LM7805, and the 3.3V regulator is AM1117. The 5V regulator is powered by an external AC-DC-12V switching power supply, and the 3.3V regulator is powered by the 5V regulator.

[0065] During use, users can perform secondary program development based on the circuit principle in this embodiment:

[0066] Four I2S signals (SD, BCLK, LRCLK) are input to the time slot multiplexing unit MUX (74LS153N) through interface J1 to interface J4. The time slot multiplexing unit MUX can select different PCM data streams for multiplexing according to the control signals of the FPGA.

[0067] The FPGA (XC7A100T-2FGG484I) is mainly responsible for receiving multiplexed signals from the MUX. Users can perform time slot separation and data reassembly in the FPGA as needed, and allocate them to different data interfaces (USB, SATA, high bandwidth interface).

[0068] The FPGA uses a clock provided by the CDCE913 for synchronization control to ensure the stability of data processing.

[0069] The data processed by the FPGA can:

[0070] The signal is transmitted to the DSP (TMS320C5517) for further audio signal processing (such as noise reduction and echo cancellation) and then output via the I2S interface.

[0071] It transmits data to a USB module (USB2517) and provides a USB interface output.

[0072] The data is transferred to the SATA module (88SE9130) and stored on the hard drive.

[0073] Transmitted to the high-bandwidth interface (LAN8720) for high-speed data transmission.

[0074] This utility model discloses a digital cross-connect module for time-slot separation of PCM voice signals. It solves the technical problems of time-slot multiplexing of four I2S signals, providing multiple interface technologies such as USB, SATA, and high-bandwidth interfaces, and enabling connection to external SATA interface storage devices. Utilizing USB, SATA, and high-bandwidth interfaces, PCM data can be stored on a hard drive, transmitted to a computer via USB, or transmitted over long distances via a high-speed digital interface, adapting to different application scenarios. Through its hardware architecture, users can perform secondary development; for example, the FPGA can handle time-slot separation and data management, while the DSP can specifically process voice signals, such as noise reduction and echo cancellation, improving the system's audio processing capabilities. The CDCE913 clock management chip ensures clock synchronization of all modules, improving data processing stability. Time-slot multiplexing of four I2S signals via a MUX improves signal transmission efficiency and reduces hardware costs. The TXB0108PWR is used for level conversion, allowing the FPGA to directly control the MUX and I2S signals, enhancing system compatibility and stability. The independent module design allows for flexible system expansion, adding more input channels or improving data transmission methods.

Claims

1. A digital cross-connect module for time slot separation of PCM voice signals, characterized by: The power module, the PCM interface, the time slot multiplexing unit, the FPGA controller, the USB module, the SATA module, the clock management chip, the digital signal processing chip, the high bandwidth interface chip, the USB interface, the SATA interface, the I2S interface and the high bandwidth interface are included. The 4-way I2S signal input interface is connected with the time slot multiplexing unit. The USB module, the SATA module, the clock management chip, the digital signal processing chip and the high bandwidth interface chip are connected with the FPGA controller. The USB interface is connected with the USB module, the SATA interface is connected with the SATA module, the I2S interface is connected with the digital signal processing chip, and the high bandwidth interface is connected with the high bandwidth interface chip. The power module supplies power for the time slot multiplexing unit, the FPGA controller, the USB module, the SATA module, the clock management chip, the digital signal processing chip and the high bandwidth interface chip.

2. A digital cross-connect module for time-slotting PCM voice signals as set forth in claim 1, characterized in that: The model of the FPGA controller is XC7A100T-2FGG484I, the model of the USB module is USB2517, the model of the SATA module is 88SE9130, the model of the clock management chip is CDCE913, the model of the digital signal processing chip is TMS320C5517 type DSP chip, and the model of the high bandwidth interface chip is LAN8720.

3. A digital cross-connect module for time-slotting PCM voice signals as set forth in claim 1, characterized in that: The power module includes a 5V stabilizer and a 3.3V stabilizer, the 5V power supply output by the 5V stabilizer supplies power for the time slot multiplexing unit, and the 3.3V power supply output by the 3.3V stabilizer supplies power for the FPGA controller, the USB module, the SATA module, the clock management chip, the digital signal processing chip and the high bandwidth interface chip.

4. A digital cross-connect module for time-slotting PCM voice signals as set forth in claim 3, characterized in that: The 4-way I2S signal input interface is respectively interface J1, interface J2, interface J3 and interface J4. The time slot multiplexing unit includes digital multiplexer IC1, digital multiplexer IC2, digital multiplexer IC3, level converter U1, level converter U2 and level converter U3. The input end of the digital multiplexer IC1 is connected with the BCLK end of the interface J1, the BCLK end of the interface J2, the BCLK end of the interface J3 and the BCLK end of the interface J4, and the output end and the control end of the digital multiplexer IC1 are connected with different IO ports of the FPGA controller through the level converter U1. The input end of the digital multiplexer IC2 is connected with the SD end of the interface J1, the SD end of the interface J2, the SD end of the interface J3 and the SD end of the interface J4, and the output end and the control end of the digital multiplexer IC2 are connected with different IO ports of the FPGA controller through the level converter U2. The input end of the digital multiplexer IC3 is connected with the LRCLK end of the interface J1, the LRCLK end of the interface J2, the LRCLK end of the interface J3 and the LRCLK end of the interface J4, and the output end and the control end of the digital multiplexer IC3 are connected with different IO ports of the FPGA controller through the level converter U3.

5. A digital cross-connect module for time-slotting PCM voice signals as set forth in claim 4, characterized in that: The model of the digital multiplexer IC1, the digital multiplexer IC2 and the digital multiplexer IC3 is 74LS153N, and the digital multiplexer IC1, the digital multiplexer IC2 and the digital multiplexer IC3 are powered by a 5V power supply; The model of the level converter U1, the level converter U2 and the level converter U3 is voltage level converter TXB0108PWR, and the level converter U1, the level converter U2 and the level converter U3 are used to convert 5V level signals into 3.3V level signals.

6. A digital cross-connect module for time-slotting PCM voice signals as set forth in claim 4, characterized in that: The 1 pin of the interface J1, the 1 pin of the interface J2, the 1 pin of the interface J3 and the 1 pin of the interface J4 are connected to the ground wire through the magnetic bead R0.

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