Circuit board

Abstract

The utility model relates to a circuit board, which comprises a pair of first signal terminals, a pair of second signal terminals, a first wire and a second wire, and the first signal terminals comprise a first terminal and a second terminal. The second signal terminal comprises a third terminal and a fourth terminal, and the distance between the first terminal and the fourth terminal is not equal to the distance between the second terminal and the third terminal. The lengths of the first wire and the second wire are roughly equal, and the first wire and the second wire respectively extend to the second specific layer from the first specific layer of the circuit board through the filling hole, so that the first terminal is electrically connected with the third terminal, and the second terminal is electrically connected with the fourth terminal.

Description

Technical Field

[0001] This application relates to a circuit board, and more particularly to a side-mounted circuit board that can be connected to a connecting wire or connector. Background Technology

[0002] A side-out paddle card is primarily a circuit board 100 with a corner, and it is commonly used in the connector field, especially as an internal paddle structure for Type-C connectors. Therefore, side-out paddle cards are mainly used to connect MCIO (Mini Cool Edge I / O) cables (or their modular connectors) and adapt them to various port specifications, such as, but not limited to, Type-C. They are mainly used for high-speed signal transmission, and side-out paddle cards generally feature small size and high-density wiring.

[0003] However, please refer to the accompanying materials. Figure 1A Side-exit turntables, due to mechanical limitations, may have differential pairs (internal and external traces) of unequal length. This results in signal transmission delay (skew). Therefore, a common solution is to use... Figure 1B The design approach uses serpentine routing to address the issue of unequal differential pair lengths. However, for shorter traces (such as those near corners), it's impossible to use too much serpentine routing to maintain equal lengths. The main reason is that shorter traces have excessively short paths, making it difficult to create sufficient and compliant serpentine routing (e.g.,...). Figure 1B The leftmost half of the routing can only form two sets of serpentine routing to solve the problem of unequal differential pair lengths. Therefore, if enough serpentine routing cannot be formed, the unequal lengths of differential pairs (inner and outer traces) will still occur, causing signal transmission delay problems.

[0004] On the other hand, the serpentine routing structure can cause asymmetry in differential pairs, meaning the differential pairs (internal and external traces) are not parallel and equidistant. This can lead to issues such as... Figure 1C and Figure 1D This results in poor common-mode conversion (SCD21) and high attenuation (Insertion Loss; IL, or SDD21). Specifically, in Figure 1CThe test waveforms of SCD21 and SDD21 for the differential pairs Df1 and Df2 furthest from the corner are primarily shown. Since differential pairs Df1 and Df2 are far from the corner, there is sufficient distance to form a adequate serpentine routing pattern. Therefore, their test waveforms meet the specifications (i.e., the waveform of SCD21 is below the upper limit Vm, and the two lines of SDD21 do not intersect). However, for the differential pairs Df3 and Df4 closest to the corner, there is insufficient distance to form a sufficient serpentine routing pattern. Therefore, their test waveforms do not meet the specifications, leading to a risk of distortion in the transmission of the differential signals.

[0005] Therefore, how to design a circuit board that allows the traces of differential pairs to be of equal length at corners without using serpentine routing is a major research topic that the applicant intends to study. Utility Model Content

[0006] To address the aforementioned problems, this application provides a circuit board to overcome the limitations of the prior art. Therefore, the circuit board of this application includes a pair of first signal terminals, a pair of second signal terminals, and a first trace group, wherein the first trace group includes a first trace and a second trace. The first signal terminals include a first terminal and a second terminal arranged in a specific direction from the edge of the circuit board, and the first and second terminals are formed on a first side of the circuit board. The second signal terminals include a third terminal and a fourth terminal arranged in the specific direction, and a first shortest distance from the first terminal to the fourth terminal is different from a second shortest distance from the second terminal to the third terminal. The first trace is formed on a first specific layer of the circuit board and extends to a second specific layer through one of a plurality of first vias, and returns to the first specific layer through another of the plurality of first vias to electrically connect the first terminal and the third terminal. The second trace is formed on the first specific layer and extends to the second specific layer through one of a plurality of second vias, and returns to the first specific layer through another of the plurality of second vias to electrically connect the second terminal and the fourth terminal. The first trace has a first length, and the second trace has a second length; the first trace and the second trace are formed in an interlaced structure on different layers, and the first length is approximately equal to the second length.

[0007] In one embodiment, the third terminal and the fourth terminal are formed on the second side of the circuit board, and the first side is not parallel to the second side.

[0008] In one embodiment, the first side and the second side are adjacent sides, and the first side and the second side are approximately 90 degrees apart.

[0009] In one embodiment, the circuit board has a first surface layer and a second surface layer, and the circuit board further includes: a pair of third signal terminals, including a fifth terminal and a sixth terminal, wherein the fifth terminal and the sixth terminal are respectively formed in the second surface layer and are substantially at the same positions as the first terminal and the second terminal in the first surface layer; a pair of fourth signal terminals, including a seventh terminal and an eighth terminal, wherein the seventh terminal and the eighth terminal are respectively formed in the second surface layer and are substantially at the same positions as the third terminal and the fourth terminal in the first surface layer; a second trace group, including: a third trace formed in a third specific layer of the circuit board and extending to a fourth specific layer through one of a plurality of third vias and returning to the third specific layer through another of the plurality of third vias to electrically connect the fifth terminal and the seventh terminal; and a fourth trace formed in the third specific layer and extending to the fourth specific layer through one of a plurality of fourth vias and returning to the third specific layer through another of the plurality of fourth vias to electrically connect the sixth terminal and the eighth terminal; wherein the third trace has a third length, the fourth trace has a fourth length, and the third length is substantially equal to the fourth length.

[0010] In one embodiment, the system further includes: a first ground layer formed between a first surface layer and a second surface layer, wherein no first trace group and a second trace group are formed on the first ground layer; and a second ground layer formed on an adjacent layer of the first ground layer, wherein no first trace group and a second trace group are formed on the second ground layer.

[0011] In one embodiment, the first wiring group is formed on an adjacent layer of the first ground layer, the second wiring group is formed on an adjacent layer of the second ground layer, and the first wiring group and the second wiring group are not formed on the same layer.

[0012] In one embodiment, the first signal terminal is used to transmit a signal to the second signal terminal, and the fourth signal terminal is used to transmit a signal to the third signal terminal.

[0013] In one embodiment, the first trace and the second trace are generally parallel to each other, and the third trace and the fourth trace are generally parallel to each other.

[0014] In one implementation, the first wiring group and the second wiring group are used to transmit differential signals.

[0015] In one embodiment, the circuit board is a side-mounted turntable, and the turntable is used to connect a connector.

[0016] The main purpose and effect of this application is that, by utilizing the feature of the traces entering the inner layer of the circuit board through the vias, length compensation can be performed on traces in different layers, so that the first length of the first trace is approximately equal to the second length of the second trace, thereby achieving the effect of providing better common-mode conversion and lower attenuation.

[0017] To gain a deeper understanding of the techniques, means, and effects employed in achieving the intended purpose of this application, please refer to the following detailed description and accompanying drawings. It is believed that the purpose, features, and characteristics of this application can be understood in a more in-depth and concrete manner from these drawings. However, the accompanying drawings are provided for reference and illustration only and are not intended to limit this application. Attached Figure Description

[0018] Figure 1A This is a schematic diagram of a commonly known side-displaying turntable circuit structure;

[0019] Figure 1B A schematic diagram of the circuit structure of the turntable is shown from another known side.

[0020] Figure 1C for Figure 1B In the circuit structure, the test waveform of the differential pair furthest from the corner;

[0021] Figure 1D for Figure 1B In the circuit structure, the test waveform diagram of the differential pair closest to the corner;

[0022] Figure 2A This is a schematic diagram of the wiring configuration of the first embodiment of the side-exit circuit board in this application;

[0023] Figure 2B This is a schematic diagram of the wiring configuration of the second embodiment of the side-exit circuit board in this application;

[0024] Figure 2C This is a schematic diagram of the wiring configuration of the third embodiment of the side-exit circuit board in this application;

[0025] Figure 3A This is a schematic diagram of the routing configuration of one of the fourth embodiments of the side-exit circuit board of this application;

[0026] Figure 3B This is an intentional routing configuration for another embodiment of the side-exit circuit board of this application.

[0027] Figure 3C In the fourth embodiment of the side-mounted circuit board of this application, Figure 3A and Figure 3B The intention behind the wiring configuration where lines intersect;

[0028] Figure 4A This is a schematic diagram of the routing configuration of one of the fifth embodiments of the side-exit circuit board of this application;

[0029] Figure 4B This application presents another routing configuration intent for a fifth embodiment of a side-exposed circuit board; and

[0030] Figure 4C In the fifth embodiment of the side-mounted circuit board of this application, Figure 4A and Figure 4B The intention behind the wiring configuration where lines overlap.

[0031] Explanation of reference numerals in the attached figures:

[0032] Df1, Df2, Df3, Df4: Difference pairs;

[0033] 100: Circuit board;

[0034] S1: First side;

[0035] S2: Second side;

[0036] 12: First terminal;

[0037] 14: Second terminal;

[0038] 22: Third terminal;

[0039] 24: Fourth terminal;

[0040] 32: Fifth terminal;

[0041] 34: Sixth terminal;

[0042] 42: Seventh terminal;

[0043] 44: Eighth terminal;

[0044] G1: First wiring group;

[0045] T1: First routing line;

[0046] T2: Second routing line;

[0047] G2: Second wiring group;

[0048] T3: Third routing line;

[0049] T4: Fourth routing line;

[0050] L1~L6: Layers;

[0051] H, H1~H4: Filling holes;

[0052] GND: Access Block;

[0053] Vm: Upper limit value;

[0054] D1: Specific direction;

[0055] X1: First shortest distance;

[0056] X2: The second shortest distance. Detailed Implementation

[0057] The technical content and detailed description of this application are explained below with reference to the accompanying drawings:

[0058] Please see Figure 2A For the routing configuration of the first embodiment of the side-exposed circuit board of this application, please refer again to [reference needed]. Figures 1A-1D .exist Figure 2A In this illustration, to clearly demonstrate the characteristics of this application, the circuit board 100 is primarily shown as an illustrative example with a corner structure having approximately a 90-degree angle, but is not limited thereto. The circuit board 100 includes a pair of first signal terminals and a pair of second signal terminals, and the first signal terminals include a first terminal 12 and a second terminal 14 arranged from the edge of the circuit board 100 toward a specific direction D1. The specific direction D1 is merely an illustrative example and can also be... Figure 2A The directions shown are opposite. The first terminal 12 and the second terminal 14 are formed on the first side S1 of the circuit board 100, and the third terminal 22 and the fourth terminal 24 may be formed on the second side S2 of the circuit board 100, or as shown... Figure 1A , 1B The terminals in the middle of the circuit board are not formed on either side of the circuit board 100. Therefore, if the terminals are ordered in a specific direction D1, they are, in order, the first terminal 12, the second terminal 14, the third terminal 22, and the fourth terminal 24.

[0059] The connection formed by the first shortest distance X1 from the first terminal 12 to the fourth terminal 24 is different from the connection formed by the second shortest distance X2 from the second terminal 14 to the third terminal 22. This means that the first signal terminal and the second signal terminal are not formed on opposite sides of the circuit board 100 (this prerequisite is that the two opposite sides of the circuit board 100 are exactly parallel, and this does not apply if the two opposite sides of the circuit board 100 are not parallel), and there will be no situation where the third terminal 22 and the fourth terminal 24 are formed on the left and right sides of the circuit board 100 (the same applies to the first terminal 12 and the second terminal 14). Therefore, the connection formed by the first shortest distance X1 may be smaller or larger than the connection formed by the second shortest distance X2, mainly because the terminals closer to the corners of the circuit board 100 will inevitably have shorter distances (in order to...). Figure 2A The connection formed by the shortest distance from the second terminal 14 to the third terminal 22 is shown to be relatively short.

[0060] It is worth mentioning that, in one embodiment, the third terminal 22 and the fourth terminal 24 are formed on the second side S2 of the circuit board 100. Furthermore, the first side S1 is clearly not parallel to the second side S2, and the first side S1 and the second side S2 are adjacent sides. The first side S1 and the second side S2 are approximately 90 degrees apart, but this angle is not a limiting condition; as long as they are not parallel, they should be included within the scope of this embodiment.

[0061] See again Figure 2A The circuit board 100 also includes a first trace group G1, a plurality of first vias H1, and a plurality of second vias H2. The first trace group G1 includes a first trace T1 and a second trace T2. The first trace T1 is formed on a first specific layer of the circuit board 100 (here illustrated as first layer L1) and extends to a second specific layer (here illustrated as second layer L2) through one of the first vias H1. Regardless of how many first vias H1 the first trace T1 extends to different layers, it will eventually return to the first specific layer through another first via H1, allowing the first terminal 12 to be electrically connected to the third terminal 22 via the first trace T1. The first trace T1 has a first length, which refers to the total length of the first trace T1. Similarly, the second trace T2 is formed on the first specific layer (i.e., first layer L1) of the circuit board 100 and extends to the second specific layer (i.e., second layer L2) through one of the second vias H2. Furthermore, regardless of how many second vias H2 the second trace T2 extends to different layers, it will ultimately return to the first specific layer through another second via H2, allowing the second terminal 22 to be electrically connected to the fourth terminal 24 via the second trace T2. The second trace T2 has a second length, which refers to the total length of the second trace T2. On the other hand, vias H1 and H2 can be through-holes, blind vias, or buried vias, depending on actual needs, but blind vias are generally more common and are not limited here. In addition, conductive materials such as, but not limited to, tin and copper can be configured inside vias H1 and H2 to allow traces on different layers to be electrically connected vias H1 and H2.

[0062] exist Figure 2A In this diagram, L1:L2 represents the vias from the surface layer L1 of the circuit board 100 to the second layer L2, and L2:L3 represents the vias from the second layer L2 to the third layer L3 of the circuit board 100, and so on. Therefore, the first terminal 12 is coupled to the first trace T1 and extends from the surface layer L1 of the circuit board 100 through the first via H1 to the second layer L2. Furthermore, where the first trace T1 in the second layer L2 is to overlap with the second trace T2, the first trace T1 extends from the second layer L2 through the first via H1 to the third layer L2, creating a structure where traces overlap at different layers. Finally, the first trace T1 extends from the third layer L2 through the first via H1 back to the surface layer L1 to couple to the third terminal 22. Figure 2A As shown, the structure of the second trace T2 is similar to that of the first trace T1, and will not be described in detail here.

[0063] In this embodiment, the first trace T1 and the second trace T2 are of the same length, but the length of the first trace T1 on the surface layer L1 is shorter than that of the second trace T2. That is, at the intersection of the first trace T1 and the second trace T2, the first trace T1 first extends to the third layer L3 through the first injection hole H1, and the second trace T2, after crossing the first trace T1 on the surface layer L1 and the third layer L3, then extends to the third layer L3 through the second injection hole H2. It is worth noting that in one embodiment, the number of first injection holes H1 and second injection holes H2 are three each, but this is not a limitation. The main point is that after the design of the first trace T1 and the second trace T2 overlapping on different layers through the first injection holes H1 and the second injection holes H2, the lengths of the first trace T1 and the second trace T2 can be approximately equal. Furthermore, the first injection holes H1 and the second injection holes H2 have a corresponding relationship (i.e., equal number), therefore the total number of first injection holes H1 and second injection holes H2 is an even number. Therefore, those skilled in the art can increase or decrease the number of the first filling hole H1 and the second filling hole H2 according to the logic of this application, but basically, at least one filling hole needs to be configured at the intersection of the first routing T1 and the second routing T2 in order to implement this.

[0064] Therefore, the circuit board 100 of this application is characterized in that the traces can be formed in an interlaced structure design on different layers through vias. Specifically, when the first trace T1 extends to the third layer L3, it can be changed from a position far from the corner of the circuit board 100 to a position close to the corner of the circuit board 100, thereby reducing the length of the first trace T1 (compared to...). Figure 1A , 1B (Related technologies). Similarly, when extending to the third layer L3, the length of the second trace T2 can be increased by changing from a position close to the corner of the circuit board 100 to a position farther away from the corner of the circuit board 100 (compared to...). Figure 1A , 1B (Related technologies).

[0065] Therefore, by utilizing the feature of the traces in this application entering the inner layer of the circuit board 100 through the vias, length compensation can be performed on traces in different layers, making the first length of the first trace T1 approximately equal to the second length of the second trace T2. This structural feature is similar to... Figure 1A , 1B The biggest difference in the structure of the circuit board 100 is that Figure 1A , 1B In the circuit board 100, the first terminal 12 is electrically connected to the fourth terminal 24, and the second terminal 14 is electrically connected to the third terminal 22. However, in this application, the wiring enters the inner layer of the circuit board 100 through vias, which makes the first terminal 12 electrically connected to the third terminal 22, and the second terminal 14 electrically connected to the fourth terminal 24.

[0066] In addition, since the circuit board 100 is mainly for connecting MCIO (Mini Cool Edge I / O) cables (or their modular connectors) and converting them to various ports such as, but not limited to, Type-C, the first trace group G1 is mainly used to transmit differential signals. Because the first length of the first trace T1 is approximately equal to the second length of the second trace T2, the differential pairs (i.e., the inner and outer traces of the first trace group G1) can be made approximately equal in length, thus reducing the problem of signal transmission delay (skew). Furthermore, this application does not need to use a serpentine routing method to solve the problem of unequal lengths of the differential pairs (i.e., the first trace group G1) in order to make the two traces equal in length, thus simultaneously solving the asymmetry of the differential pairs (i.e., the first trace group G1). Therefore, it can achieve the effects of providing better common-mode conversion (SCD21) and lower attenuation (Insertion Loss; IL, or SDD2).

[0067] On the other hand, since the differential pair (i.e., the first trace group G1) mainly transmits high-speed differential signals, the preferred routing method is to arrange the two traces of the differential pair (i.e., the first trace group G1) as parallel and equidistant as possible to avoid the differential signal being affected by noise. Since the first trace group G1 of this application does not need to use serpentine routing, and the lengths of the first trace T1 and the second trace T2 are approximately equal, the first trace T1 and the second trace T2 of this application can have a substantially parallel and equidistant routing structure. That is, the first trace T1 and the second trace T2 of this application can form a parallel and equidistant routing structure on the straight extensions of the same layer.

[0068] In addition, Figure 2A The circuit board 100 may also include a ground layer (not shown in the figure), which may be formed on any layer other than the surface layer L1, and no traces forming the first trace group G1 are present on the ground layer. If... Figure 2A For example, if the circuit board 100 is a four-layer board, then the ground layer should be formed on another surface layer L4. The ground layer can be electrically connected to the grounding block GND of the surface layer L1 through vias H, and can also be coupled to a ground terminal (not shown in the figure) through the grounding block GND. Furthermore, the accuracy of the measured signal depends on the consistency of "grounding" in the system. Therefore, the circuit board 100 of this application is equipped with a ground layer so that the transmitted differential signals have the same and referable ground potential, thereby improving the quality of the transmitted signal. It is worth mentioning that in one embodiment, the number of vias H that can electrically connect the grounding block GND of the surface layer L1 to the ground layer is only schematically indicated as 3, but in practice it is not limited to 3, and can be increased or decreased according to actual needs.

[0069] Please see Figure 2BFor the routing configuration intent of the second embodiment of the side-exposed circuit board of this application, please refer again to [reference needed]. Figures 1A-2A . Figure 2B and Figure 2A The difference lies in the fact that the paths of the first trace T1 and the second trace T2 are different, and the positions of the first filling hole H1 and the second filling hole H2 are also different. However, the first trace T1 and the second trace T2 can still form an interlaced structure design in different layers through the filling holes H1 and H2, and the lengths of the first trace T1 and the second trace T2 are approximately equal to achieve the desired effect. Figure 2A The stated effects. Among them, Figure 2B The architecture and its characteristics are similar to Figure 2A This will not be elaborated upon further here.

[0070] Please see Figure 2C For the routing configuration intent of the third embodiment of the side-exposed circuit board of this application, please refer again to [reference needed]. Figures 1A-2B . Figure 2C and Figure 2A The difference lies in the fact that circuit board 100 is an irregularly shaped board, primarily showcasing more extreme cases. In Figure 2C In this circuit board, the angle between the first signal terminal and the second signal terminal is not a 90-degree angle. However, the first trace T1 and the second trace T2 can also be formed in an interlaced structure design on different layers through vias H1 and H2, and the lengths of the first trace T1 and the second trace T2 are approximately equal to achieve the desired effect. Figure 2A The stated effects. Among them, Figure 2C The architecture and its characteristics are similar to Figure 2A This will not be elaborated upon further here. Therefore, based on the above... Figures 2A-2C As shown, regardless of the shape of the side-exit circuit board 100, the routing configuration of this application can achieve the corresponding effect by compensating the length of the routing in different layers.

[0071] Please see Figure 3A This application presents a schematic diagram of the routing configuration for one of the fourth embodiments of the side-exposed circuit board. Figure 3B For another routing configuration of the fourth embodiment of the side-exposed circuit board of this application, please refer again to [the relevant documentation]. Figures 1A-2C .exist Figure 3A , 3BThe diagram primarily shows the signal terminals and their routing configurations on the upper and lower surfaces of a single circuit board 100. Specifically, the most common communication method between chips is the Universal Asynchronous Receiver / Transmitter (UART), whose main characteristic is that it only requires two lines to complete bidirectional communication. Therefore, UART mainly uses one line to receive signals and another line to transmit signals to achieve communication, and these two lines are generally referred to as Tx and Rx. Figure 3A , 3B The configuration method is mainly based on Tx and Rx.

[0072] Furthermore, Figure 3A Similar to Figure 2A It includes a pair of first signal terminals, a pair of second signal terminals, a first trace group G1, and vias H1 and H2. Furthermore, the first signal terminals and the second signal terminals are formed on the first surface layer L1 of the circuit board 100. Figure 3B It includes a pair of third signal terminals, a pair of fourth signal terminals, a second trace group G2, and vias H3 and H4, wherein the second trace group G2 includes a third trace T3 and a fourth trace T4. Furthermore, the third signal terminals and the fourth signal terminals are formed on the second surface layer L6 of the circuit board 100 (taking a six-layer board as an example), and the second surface layer L6 is different from the first surface layer L1.

[0073] Specifically, the third signal terminal includes a fifth terminal 32 and a sixth terminal 34, and the fourth signal terminal includes a seventh terminal 42 and an eighth terminal 44. The fifth terminal 32 and the sixth terminal 34 are respectively formed in the second surface layer L6, substantially at the same positions as the first terminal 12 and the second terminal 14 of the first surface layer L1. That is, the third signal terminal and the first signal terminal are substantially coincident in top view. Similarly, the fourth signal terminal and the second signal terminal are substantially coincident in top view.

[0074] The first trace T1 extends through the first via H1 in the following order: L1:L2, L2:L5, L5:L1, to couple the first terminal 12 to the third terminal 22 via the first trace T1. The second terminal 14 is coupled to the fourth terminal 24 in a similar manner to the first trace T1, which will not be described in detail here. The circuit board 100 also includes a plurality of third vias H3 and a plurality of fourth vias H4. The third trace T3 is similar to the first trace T1, and it is formed on the third specific layer of the circuit board 100 (here illustrated as the sixth layer L6), and extends to the fourth specific layer (here illustrated as the fifth layer L5) through one of the third vias H3. Furthermore, no matter how many third vias H3 the third trace T3 extends to different layers, it will eventually return to the third specific layer through another third via H3, so that the fifth terminal 32 can be electrically connected to the seventh terminal 42 through the third trace T3. The fourth trace T4 is similar to the second trace T2. It is also formed on the third specific layer (i.e., the sixth layer L6) and extends to the fourth specific layer (i.e., the fifth layer L5) through one of the fourth vias H4. Furthermore, no matter how many fourth vias H4 the fourth trace T4 extends to different layers, it will eventually return to the third specific layer through another fourth via H4, so that the sixth terminal 34 can be electrically connected to the eighth terminal 44 through the fourth trace T4.

[0075] More specifically, the third trace T3 extends through the third via H3 in the following order: L6:L5, L5:L2, L2:L6, to couple the fifth terminal 32 to the seventh terminal 42 via the third trace T3. The sixth terminal 34 is coupled to the eighth terminal 44 in a similar manner to the third trace T3, which will not be described in detail here. Therefore, the characteristics of the second trace group G2 are similar to those of the first trace group G1, that is, the third length of the third trace T3 is approximately equal to the fourth length of the fourth trace T4. It is worth mentioning that, in one embodiment, although the first trace T1 and the second trace T2 are shown above to extend from the surface layer (i.e., the first specific layer is the first layer L1) through vias H1 to H2 to other layers (i.e., the second specific layer) and finally return to the surface layer (i.e., the same first specific layer) through vias H1 to H2 to electrically connect the terminals 12, 14, 22, and 24 located on the surface layer, this is not a limitation. That is, the above-described surface layer is only a preferred embodiment. However, if terminals 12, 14, 22, and 24 are not located on the surface layer (i.e., the first specific layer is not the first layer L1), then the first trace T1 and the second trace T2 can be extended from the actual location of terminals 12 and 14 (e.g., but not limited to the second layer L2, the fifth layer L5, etc.) to other layers (i.e., the second specific layer), and finally electrically connected to the actual location of terminals 22 and 24 (e.g., but not limited to the third layer L3, the fourth layer L4, etc.) through vias H1 to H2. On the other hand, the configuration of the third specific layer and the fourth specific layer is similar to the above. That is, the above surface layer is only a preferred implementation. If the terminals 32, 34, 42, and 44 are not configured on the surface layer (i.e., the third specific layer is not the sixth layer L6), then the third trace T3 and the fourth trace T4 can be extended from the actual configuration position of the terminals 32 and 34 (e.g., but not limited to the third layer L3, the fourth layer L4, etc.) to other layers (i.e., the fourth specific layer), and finally electrically connected to the actual configuration position of the terminals 42 and 44 through the vias H3 to H4.

[0076] Similar to Figure 2A The third trace T3 and the fourth trace T4 can be arranged in a generally parallel and equidistant structure. That is, the third trace T3 and the fourth trace T4 can form a parallel and equidistant trace structure on the straight extensions of the same layer. Furthermore, due to the design of Tx and Rx, the first trace group G1 and the second trace group G2 are used to transmit differential signals. Moreover, the first signal terminal can be used to transmit signals to the second signal terminal, and the fourth signal terminal can be used to transmit signals to the third signal terminal, thereby achieving bidirectional communication.

[0077] Please see Figure 3C In the fourth embodiment of the side-mounted circuit board of this application, Figure 3A and Figure 3B The intention behind the wiring configuration where lines intersect is further illustrated in the reference section. Figures 1A-2C . Figure 3CThe circuit board 100 is similar to Figure 2A This includes a first ground layer and a second ground layer (not shown in the figure) to provide the differential signals Tx and Rx with the same and referable ground potential. Similar to... Figure 2A The first grounding layer and the second grounding layer can be formed on any layer other than the surface layers L1 and L6, and no traces of the first trace group G1 and the second trace group G2 are formed on either the first grounding layer or the second grounding layer. Furthermore, with Figure 3C For example, the first grounding layer and the second grounding layer should be formed on the third layer L3 and the fourth layer L4, and can be electrically connected to the grounding blocks GND of the surface layer L1 and L6 through the injection hole H, respectively.

[0078] Since the first trace T1 and the second trace T2 can pass through the first ground layer and the second ground layer respectively through the extension of the first filler hole H1 and the second filler hole H2 (i.e., the extension method of L2:L5), and the third trace T3 and the fourth trace T4 can pass through the first ground layer and the second ground layer respectively through the extension of the third filler hole H3 and the fourth filler hole H4 (i.e., the extension method of L5:L2), this means that although neither the first ground layer nor the second ground layer has any traces forming the first trace group G1 and the second trace group G2, the first ground layer and the second ground layer can still include filler holes H1 to H4 for the extension of traces T1 to T4. On the other hand, since the first trace group G1 and the second trace group G2 share the same layer (i.e., share the second layer L2 and the fifth layer L5), the traces of these two layers must be staggered, that is, the traces of the first trace group G1 and the second trace group G2 running on these two layers L2 and L5 do not overlap.

[0079] therefore, Figures 3A-3C Most of the traces are located in the inner layers (i.e., layers L2 to L5), and generally require more than 12 vias H1 to H4 to connect the first signal terminal and the second signal terminal. Furthermore, the circuit board 100 utilizes the staggered positions of vias H1 to H4 to ensure that the lengths of the first trace group G1 and the second trace group G2 are similar. Specifically, for the first and second signal terminals of Tx, the first trace T1 in layer L2 is shorter, and the second trace T2 is longer. Furthermore, the first trace T1 in layer L5 is longer, and the second trace T2 is shorter, thus making the total lengths of the first trace T1 and the second trace T2 similar. In contrast, the third and fourth signal terminals of Rx are the opposite of Tx, resulting in similar total lengths, which will not be elaborated further here.

[0080] Please see Figure 4A This application presents a schematic diagram of the routing configuration for one of the fifth embodiments of the side-exposed circuit board. Figure 4B This application presents another routing configuration intent for the fifth embodiment of the side-exposed circuit board. Figure 4CIn the fifth embodiment of the side-mounted circuit board of this application, Figure 4A and Figure 4B The intention behind the wiring configuration where lines intersect is further illustrated in the reference section. Figures 1A-3C . Figures 4A-4C and Figures 3A-3C The difference is that, Figures 4A-4C Most of the traces T1 to T4 are located on the first surface layer L1 and the second surface layer L6. Furthermore, the first trace group G1 is formed on the layer adjacent to the first ground layer, and the second trace group G2 is formed on the layer adjacent to the second ground layer. The first trace group G1 and the second trace group G2 are not formed on the same layer. Specifically, the first trace T1 and the second trace T2 extend through the first via H1 and the first via H2 in the order L1:L3 and L3:L1, respectively, and the first ground layer should be formed on the second layer L2. Conversely, the third trace T3 and the fourth trace T4 extend through the third via H3 and the fourth via H4 in the order L6:L4 and L4:L6, respectively, and the second ground layer should be formed on the fifth layer L5.

[0081] Since the first trace group G1 and the first ground plane are only formed on the first to third layers L1 to L3 of the circuit board 100, and the second trace group G2 and the second ground plane are only formed on the fourth to sixth layers L4 to L6 of the circuit board 100, the first trace group G1 and the second trace group G2 do not share the same layer. Therefore, the first trace group G1 and the second trace group G2 do not need to be specially routed to increase the number of vias, allowing more space next to the traces to form vias H, so that the first ground plane and the second ground plane can be electrically connected to the grounding blocks GND of the surface layers L1 and L6 respectively.

[0082] therefore, Figures 4A-4C Most of the traces are on the outer layers (i.e., the first layer L1 and the sixth layer L6), and approximately eight vias H1 to H4 are needed to connect the first signal terminal and the second signal terminal. There are advantages and disadvantages to routing on inner and outer layers. Routing on inner layers requires more vias H1 to H4 and results in better crosstalk. Conversely, routing on outer layers requires fewer vias H1 to H4 and results in lower signal attenuation. Furthermore, the circuit board 100 also utilizes the staggered positions of vias H1 to H4 to ensure that the lengths of the first trace group G1 and the second trace group G2 are similar. Specifically, for the first and second signal terminals of Tx, the first trace T1 on the surface layer L1 is shorter, and the second trace T2 is longer. Also, the first trace T1 on the third layer L3 is longer, and the second trace T2 is shorter, thus making the total lengths of the first trace T1 and the second trace T2 similar. In contrast, the third and fourth signal terminals for Rx are exactly the opposite of Tx, making their total length similar, and will not be elaborated further here.

[0083] However, the above description is only a detailed description and accompanying drawings of preferred embodiments of this application. The features of this application are not limited thereto and are not intended to limit this application. All scope of this application shall be determined by the following patent claims. All embodiments that conform to the spirit of the patent claims and similar variations thereof shall be included in the scope of this application. Any variations or modifications that can be easily conceived by those skilled in the art within the field of this application shall be covered by the following patent claims.

Claims

1. A circuit board, characterized by, The circuit board comprises: a pair of first signal terminals, including a first terminal and a second terminal arranged in a specific direction by an edge of the circuit board, and the first terminal and the second terminal are formed on a first side of the circuit board; a pair of second signal terminals, including a third terminal and a fourth terminal arranged in the specific direction, and a first shortest distance between the first terminal and the fourth terminal is different from a second shortest distance between the second terminal and the third terminal; and a first trace group, including: a first trace formed on a first specific layer of the circuit board, and extending to a second specific layer through one of a plurality of first vias and returning to the first specific layer through another of the plurality of first vias to electrically connect the first terminal and the third terminal; and a second trace formed on the first specific layer, and extending to the second specific layer through one of a plurality of second vias and returning to the first specific layer through another of the plurality of second vias to electrically connect the second terminal and the fourth terminal; wherein the first trace has a first length, and the second trace has a second length; the first trace and the second trace are formed in an interleaved structure of different layers, and the first length is substantially equal to the second length.

2. The circuit board of claim 1, wherein, The third terminal and the fourth terminal are formed on a second side of the circuit board, and the first side is not parallel to the second side.

3. The circuit board of claim 2, wherein, The first side and the second side are adjacent sides, and the first side and the second side are substantially 90 degrees.

4. The circuit board of claim 1, wherein, The circuit board has a first surface layer and a second surface layer, and the circuit board further comprises: a pair of third signal terminals, including a fifth terminal and a sixth terminal, and the fifth terminal and the sixth terminal are respectively formed in the second surface layer, substantially the same as the positions of the first terminal and the second terminal of the first surface layer; a pair of fourth signal terminals, including a seventh terminal and an eighth terminal, and the seventh terminal and the eighth terminal are respectively formed in the second surface layer, substantially the same as the positions of the third terminal and the fourth terminal of the first surface layer; a second trace group, including: a third trace formed on a third specific layer of the circuit board, and extending to a fourth specific layer through one of a plurality of third vias and returning to the third specific layer through another of the plurality of third vias to electrically connect the fifth terminal and the seventh terminal; and a fourth trace formed on the third specific layer, and extending to the fourth specific layer through one of a plurality of fourth vias and returning to the third specific layer through another of the plurality of fourth vias to electrically connect the sixth terminal and the eighth terminal; wherein the third trace has a third length, the fourth trace has a fourth length, and the third length is substantially equal to the fourth length.

5. The circuit board of claim 4, wherein, Further comprising: a first ground layer formed between the first surface layer and the second surface layer, and there is no first trace group and second trace group formed in the first ground layer; and A second ground layer is formed adjacent to the first ground layer, and the first trace group and the second trace group are not formed in the second ground layer.

6. The circuit board of claim 5, wherein, The first trace group is formed adjacent to the first ground layer, the second trace group is formed adjacent to the second ground layer, and the first trace group and the second trace group are not formed in the same layer.

7. The circuit board of claim 4, wherein, The pair of first signal terminals is used to transmit signals toward the pair of second signal terminals, and the pair of fourth signal terminals is used to transmit signals toward the pair of third signal terminals.

8. The circuit board of claim 4, wherein, The first trace and the second trace are substantially parallel trace structures, and the third trace and the fourth trace are substantially parallel trace structures.

9. The circuit board of claim 4, wherein, The first trace group and the second trace group are respectively used to transmit differential signals.

10. The circuit board of claim 1, wherein, The circuit board is a side-out type of turn board, and the turn board is used to connect a connector.

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