Semiconductor device structure

Abstract

A semiconductor device structure includes a substrate including a P-type region and an N-type region, the P-type region and the N-type region being spaced apart from each other; the semiconductor device structure includes a light absorption structure between a P-type region and an N-type region in a substrate; the semiconductor device structure includes a first P-type film between the light absorbing structure and the P-type region; the semiconductor device structure includes a second P-type film between the light absorbing structure and the N-type region, where a portion of the substrate separates the second P-type film from the N-type region.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to semiconductor device structures. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuits than the previous one. However, these advancements have increased the complexity of fabricating and manufacturing ICs.

[0003] Throughout the history of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) has increased, while geometric dimensions (i.e., the smallest components or lines produced during manufacturing) have shrunk.

[0004] However, due to the continuous increase in functional density, the number of signals that need to be transmitted continues to increase. Therefore, light is used to transmit signals. Consequently, it is challenging to fabricate a reliable semiconductor device to detect optical signals and convert them into electrical signals. Utility Model Content

[0005] In some embodiments, a semiconductor device structure is provided, the semiconductor device structure including a substrate including a P-type region and an N-type region, wherein the P-type region and the N-type region are spaced apart from each other; a light-absorbing structure located between the P-type region and the N-type region in the substrate; a first P-type film located between the light-absorbing structure and the P-type region; and a second P-type film located between the light-absorbing structure and the N-type region, wherein a portion of the substrate separates the second P-type film from the N-type region.

[0006] According to one embodiment of the present invention, it further includes: a first isolation structure passing through a first portion of the substrate above the P-type region; and a second isolation structure passing through a second portion of the substrate above the N-type region.

[0007] According to one embodiment of the present invention, the substrate further includes: a heavy P-type doped region located above and connected to the P-type region, wherein the first isolation structure is located between the heavy P-type doped region and the first P-type film; and a heavy N-type doped region located above and connected to the N-type region, wherein the second isolation structure is located between the heavy N-type doped region and the second P-type film.

[0008] According to one embodiment of the present invention, it further includes: an insulating layer located above the substrate, the first isolation structure and the second isolation structure.

[0009] According to one embodiment of the present invention, it further includes: a capping layer that conformally covers the light-absorbing structure.

[0010] According to one embodiment of the present invention, the cover layer is in direct contact with the insulating layer.

[0011] According to one embodiment of the present invention, in a cross-sectional view of the first P-type membrane, the first P-type membrane has an L-shape.

[0012] According to one embodiment of the present invention, the first P-type film extends into the P-type region.

[0013] In some embodiments, a semiconductor device structure is provided, the semiconductor device structure including a substrate including a P-type region and an N-type region, wherein the P-type region and the N-type region are spaced apart from each other; a first P-type film located in the substrate and connected to the P-type region; a second P-type film located in the substrate and between the first P-type film and the N-type region, wherein the second P-type film is spaced apart from the N-type region; and a light-absorbing structure located in the substrate and connected between the first P-type film and the second P-type film.

[0014] According to one embodiment of the present invention, a first insulating structure and a second insulating structure are located in the substrate, wherein a waveguide portion of the substrate is located between the first insulating structure and the second insulating structure, and the waveguide portion is in direct contact with the light-absorbing structure. Attached Figure Description

[0015] The embodiments of this utility model can be better understood from the following detailed description and the accompanying drawings. It should be noted that, according to standard industry practice, the various features shown in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0016] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E This is a cross-sectional schematic diagram of the various stages of the process for forming a semiconductor device structure, based on some embodiments.

[0017] Figure 1A-1 , Figure 1B-1 , Figure 1C-1 , Figure 1D-1 and Figure 1E-1 According to some embodiments, Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E A top view of the structure of a semiconductor device.

[0018] Figure 1A-2 According to some embodiments, the following is shown: Figure 1A-1A cross-sectional schematic diagram of the semiconductor device structure with section line II-II'.

[0019] Figure 1A-3 According to some other embodiments, the following is shown: Figure 1A-1 A cross-sectional schematic diagram of the semiconductor device structure with section line II-II'.

[0020] Figure 1E-2 According to some embodiments, the following is shown: Figure 1E-1 A cross-sectional schematic diagram of the semiconductor device structure with section line II-II'.

[0021] Figure 2 A cross-sectional schematic diagram of a semiconductor device structure is shown according to some embodiments.

[0022] The attached figures are labeled as follows:

[0023] 100, 200: Semiconductor device structure

[0024] 101: Absorption and Charge Multiplication Separation Avalanche Photodetector

[0025] 110: Base

[0026] 111, 152c, 154c: Top surface

[0027] 112, 116: Semiconductor layers

[0028] 114: Insulation layer

[0029] 116a, 116b, 116e, 116f: Partial

[0030] 116c, 160b: Bottom surface

[0031] 116m: Doubling portion

[0032] 116n1: N-type region

[0033] 116n2: Heavily N-type doped region

[0034] 116p1: P-type region

[0035] 116p2: Heavily P-type doped region

[0036] 116t, 116r1, 116r2, 150b: Grooves

[0037] 116t1, 116t2, 116t3, 116t4: Inner wall

[0038] 116wg: Waveguide section

[0039] 122, 124: Insulation structure

[0040] 132, 134: Isolation Structure

[0041] 140: Insulation layer

[0042] 142: Opening

[0043] 150: P-type layer

[0044] 150a: Notch

[0045] 152, 154: P-type membrane

[0046] 152a, 154a: Horizontal section

[0047] 152b, 154b: Vertical section

[0048] 160: Light absorption structure

[0049] 162, 172: Convex top surface

[0050] 164:lower part

[0051] 166: Middle section

[0052] 168: Top

[0053] 170: Cap layer

[0054] L: Light

[0055] L1, L2: Length

[0056] W1, W2, W168: Width

[0057] V1, V2: Vertical axis Detailed Implementation

[0058] It is important to understand that the following content provides many different embodiments or examples to implement different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the description. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, the dimensions of the components are not limited to the range or values ​​of one embodiment of this disclosure, but may depend on the processing conditions and / or required nature of the components. Furthermore, the embodiments in the following description where the first component is formed above or on the second component include those where the first and second components are formed in direct contact, and may also include embodiments where additional components may be formed between the first and second components, such that the first and second components are not in direct contact. In addition, different examples in the content may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0059] To facilitate the description of the relationship between one element or component and another (or multiple elements or multiple components) in the accompanying drawings, spatially related terms such as "below," "under," "lower part," "above," "upper part," and similar terms are used. In addition to the orientations shown in the drawings, spatially related terms also cover different orientations of the device during use or operation. The device may also be positioned otherwise (e.g., rotated 90 degrees or located in other orientations), and the descriptions using the spatially related terms will be interpreted accordingly.

[0060] This document describes some embodiments. Additional operations may be provided before, during, and / or after the stages described in these embodiments. In different embodiments, some of the described stages may be substituted or eliminated.

[0061] Additional components may be added to the semiconductor device structure. In different embodiments, some components described below may be replaced or eliminated. Although some embodiments discuss operations in a specific order, these operations may be performed in other logical orders.

[0062] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E This is a cross-sectional schematic diagram of the various stages of the process for forming a semiconductor device structure, based on some embodiments. Figure 1A-1 , Figure 1B-1 , Figure 1C-1 , Figure 1D-1 and Figure 1E-1 According to some embodiments, Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E A top view of the structure of a semiconductor device.

[0063] According to some embodiments, such as Figure 1A and Figure 1A-1 As shown, a substrate 110 is provided. The substrate 110 includes, for example, a wafer or a portion thereof. The substrate 110 includes, for example, a semiconductor-on-insulator (SOI) substrate, such as silicon-on-insulator or germanium-on-insulator.

[0064] According to some embodiments, substrate 110 has a semiconductor layer 112, an insulating layer 114, and a semiconductor layer 116. According to some embodiments, insulating layer 114 is above semiconductor layer 112. According to some embodiments, semiconductor layer 116 is above insulating layer 114.

[0065] In some embodiments, semiconductor layers 112 and 116 are made of elemental semiconductor materials, including silicon or germanium in single-crystal, polycrystalline, or amorphous structures. In some other embodiments, semiconductor layers 112 and 116 are made of compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide), alloy semiconductors (e.g., SiGe or GaAsP), or combinations thereof.

[0066] In some embodiments, the substrate 110 is a device wafer comprising various device elements. In some embodiments, the various device elements are formed in and / or on the substrate 110. For simplicity and clarity, these device elements are not shown in the drawings.

[0067] Examples of various device elements include active devices, passive devices, other suitable elements, or combinations thereof. Active devices may include transistors or diodes (not shown) formed on the surface of substrate 110. Passive devices include resistors, capacitors, or other suitable passive devices.

[0068] For example, transistors can be metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc.

[0069] Various processes (such as front-end-of-line (FEOL) semiconductor manufacturing processes) are performed to form various device components. Front-end semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or combinations thereof.

[0070] In some embodiments, an isolation member (not shown) is formed in the substrate 110. The isolation member is used to surround and electrically isolate various device elements formed in and / or above the active region in the substrate 110. In some embodiments, the isolation member includes a shallow trench isolation (STI) member, a local oxidation of silicon (LOCOS) member, other suitable isolation members, or a combination thereof.

[0071] Figure 1A-2 According to some embodiments, the following is shown: Figure 1A-1 A cross-sectional schematic diagram of the semiconductor device structure along section line II-II'. According to some embodiments, such as... Figure 1A-1 and Figure 1A-2 As shown, a portion of the semiconductor layer 116 is removed to form a trench 116r1 in the semiconductor layer 116.

[0072] According to some embodiments, trench 116r1 passes through semiconductor layer 116 and exposes insulating layer 114. According to some embodiments, the removal process includes photolithography and etching processes. According to some embodiments, such as Figure 1A-1 and Figure 1A-2 As shown, insulating structures 122 and 124 are formed in trench 116r1. According to some embodiments, such as... Figure 1A-1 and Figure 1A-2 As shown, the waveguide portion 116wg of the semiconductor layer 116 is located between the insulating structure 122 and the insulating structure 124.

[0073] According to some embodiments, insulating structures 122 and 124 are made of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, borosilicate glass (BSG), phosphorussilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG), low dielectric constant materials, porous dielectric materials, or combinations thereof. According to some embodiments, insulating structures 122 and 124 are formed using a deposition process and a chemical mechanical polishing process.

[0074] Figure 1A-3 According to some other embodiments, the following is shown: Figure 1A-1 A cross-sectional schematic diagram of the semiconductor device structure along section line II-II'. In some other embodiments, such as Figure 1A-3 As shown, insulating structures 122 and 124 do not pass through semiconductor layer 116.

[0075] According to some embodiments, a portion 116e of the semiconductor layer 116 is located between the insulating structure 122 and the insulating layer 114. According to some embodiments, a portion 116f of the semiconductor layer 116 is located between the insulating structure 124 and the insulating layer 114.

[0076] According to some embodiments, such as Figure 1A and Figure 1A-1 As shown, a portion of the semiconductor layer 116 is removed to form a trench 116r2 in the semiconductor layer 116. According to some embodiments, the removal process includes a photolithography process and an etching process.

[0077] Subsequently, based on some embodiments, such as Figure 1A and Figure 1A-1 As shown, isolation structures 132 and 134 are formed in trenches 116r2 in semiconductor layer 116. According to some embodiments, isolation structures 132 and 134 are made of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), or fluorinated silicate glass (FSG), low dielectric constant materials, porous dielectric materials, or combinations thereof. According to some embodiments, isolation structures 132 and 134 are formed using a deposition process and a chemical mechanical polishing process.

[0078] Subsequently, based on some embodiments, such as Figure 1A and Figure 1A-1 As shown, a P-type region 116p1 and an N-type region 116n1 are formed in the semiconductor layer 116. According to some embodiments, the P-type region 116p1 and the N-type region 116n1 are spaced apart from each other.

[0079] According to some embodiments, such as Figure 1A As shown, isolation structure 132 passes through a portion 116a of semiconductor layer 116 above P-type region 116p1, while isolation structure 134 passes through a portion 116b of semiconductor layer 116 above N-type region 116n1.

[0080] According to some embodiments, the P-type region 116p1 is doped with a P-type dopant, such as boron (B), aluminum (Al), indium (In), or gallium (Ga). According to some embodiments, the N-type region 116n1 is doped with an N-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). According to some embodiments, the P-type region 116p1 and the N-type region 116n1 are formed using an implantation process.

[0081] According to some embodiments, such as Figure 1A and Figure 1A-1As shown, a heavily p-type doped region 116p2 and a heavily n-type doped region 116n2 are formed in semiconductor layer 116. According to some embodiments, the heavily p-type doped region 116p2 is above and connected to the p-type region 116p1. According to some embodiments, the heavily n-type doped region 116n2 is above and connected to the n-type region 116n1.

[0082] According to some embodiments, the heavily p-type doped region 116p2 is doped with a p-type dopant, such as boron (B), aluminum (Al), indium (In), or gallium (Ga). According to some embodiments, the heavily n-type doped region 116n2 is doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb).

[0083] According to some embodiments, the P-type dopant concentration in the heavily P-type doped region 116p2 is greater than the P-type dopant concentration in the P-type region 116p1. According to some embodiments, the N-type dopant concentration in the heavily N-type doped region 116n2 is greater than the N-type dopant concentration in the N-type region 116n1. According to some embodiments, the heavily P-type doped region 116p2 and the heavily N-type doped region 116n2 are formed using an implantation process.

[0084] Subsequently, based on some embodiments, such as Figure 1A and Figure 1A-2 As shown, an insulating layer 140 is formed over the substrate 110, insulating structures 122 and 124, and insulating structures 132 and 134. It should be noted that, according to some embodiments, for the sake of simplicity, Figures 1A-1 to 1E-1 Insulation layer 140 is not shown.

[0085] According to some embodiments, the insulating layer 140 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), or fluorinated silicate glass (FSG), a low dielectric constant material, a porous dielectric material, or a combination thereof. According to some embodiments, the insulating layer 140 is formed using a deposition process.

[0086] According to some embodiments, such as Figure 1B and Figure 1B-1 As shown, the insulating layer 140 and the semiconductor layer 116 between the P-type region 116p1 and the N-type region 116n1 are partially removed to form an opening 142 in the insulating layer 140 and a trench 116t in the semiconductor layer 116.

[0087] According to some embodiments, the opening 142 is above the trench 116t. According to some embodiments, the trench 116t exposes the P-type region 116p1. According to some embodiments, the trench 116t extends into the P-type region 116p1. According to some embodiments, the removal process includes a photolithography process and an etching process.

[0088] According to some embodiments, such as Figure 1C and Figure 1C-1 As shown, a P-type layer 150 is formed in a trench 116t in the semiconductor layer 116. According to some embodiments, the P-type layer 150 is compliantly formed in the trench 116t. According to some embodiments, the P-type layer 150 compliantly covers the inner walls 116t1, 116t2, 116t3, and 116t4 of the trench 116t and the bottom surface 116c of the trench 116t. According to some embodiments, the P-type layer 150 has a notch 150a in the trench 116t.

[0089] According to some embodiments, such as Figure 1C and Figure 1C-1 As shown, the multiplication portion 116m of the semiconductor layer 116 is located between the P-type layer 150 and the N-type region 116n1, and between the P-type layer 150 and the isolation structure 134. According to some embodiments, the multiplication portion 116m separates the P-type layer 150 from the N-type region 116n1.

[0090] According to some embodiments, the P-type layer 150 is made of a P-type semiconductor material comprising a semiconductor material and a P-type dopant. According to some embodiments, the semiconductor material comprises silicon, germanium, or the like. According to some embodiments, the P-type dopant comprises boron (B), aluminum (Al), indium (In), or gallium (Ga). According to some embodiments, the P-type layer 150 is formed using an epitaxial process.

[0091] According to some embodiments, such as Figure 1C , Figure 1D and Figure 1D-1 As shown, a portion of the P-type layer 150 is removed to form a trench 150b in the P-type layer 150. According to some embodiments, the P-type layer 150 is divided into P-type films 152 and 154 by the trench 150b.

[0092] According to some embodiments, a P-type membrane 152 is located on a P-type region 116p1 exposed through a trench 116t. According to some embodiments, the P-type membrane 152 is connected to the P-type region 116p1.

[0093] According to some embodiments, the P-type film 154 is located between the P-type film 152 and the N-type region 116n1. According to some embodiments, the P-type films 152 and 154 are spaced apart from each other. According to some embodiments, the P-type film 154 and the N-type region 116n1 are spaced apart from each other by a multiplication portion 116m of the semiconductor layer 116.

[0094] According to some embodiments, the P-type membrane 152 has an L-shape. According to some embodiments, the P-type membrane 152 has a horizontal portion 152a and a vertical portion 152b. According to some embodiments, the P-type membrane 154 has an L-shape. According to some embodiments, the P-type membrane 154 has a horizontal portion 154a and a vertical portion 154b.

[0095] According to some embodiments, the P-type film 152 extends into the P-type region 116p1. According to some embodiments, the isolation structure 132 is located between the heavily P-type doped region 116p2 and the P-type film 152. According to some embodiments, the isolation structure 134 is located between the heavily N-type doped region 116n2 and the P-type film 154. According to some embodiments, the removal process includes a photolithography process and an etching process.

[0096] It should be noted that, according to some embodiments, for the sake of brevity, Figures 1A-1 to 1D-1 Only a portion of the 116WG waveguide section is shown. According to some embodiments, Figure 1E-1 The entire waveguide section is displayed as 116wg.

[0097] According to some embodiments, such as Figure 1E and Figure 1E-1 As shown, the light-absorbing structure 160 is formed in the trench 116t of the semiconductor layer 116. According to some embodiments, the light-absorbing structure 160 is located above the P-type films 152 and 154. According to some embodiments, the light-absorbing structure 160 directly contacts the P-type films 152 and 154.

[0098] According to some embodiments, the light-absorbing structure 160 is connected between the P-type film 152 and the P-type film 154. According to some embodiments, the light-absorbing structure 160 is located between the P-type region 116p1 and the N-type region 116n1.

[0099] According to some embodiments, a P-type film 152 is located between the light-absorbing structure 160 and the P-type region 116p1. According to some embodiments, a P-type film 154 is located between the light-absorbing structure 160 and the N-type region 116n1. According to some embodiments, the top surface 152c of the P-type film 152 is substantially flush with the top surface 111 of the substrate 110. According to some embodiments, the top surface 154c of the P-type film 154 is substantially flush with the top surface 111 of the substrate 110.

[0100] According to some embodiments, the light-absorbing structure 160 covers the top surface 152c of the P-type film 152 and the top surface 154c of the P-type film 154. According to some embodiments, the light-absorbing structure 160 has a convex top surface 162. According to some embodiments, the convex top surface 162 is a convex curved surface.

[0101] According to some embodiments, the light-absorbing structure 160 has a lower portion 164, a middle portion 166, and a top portion 168. According to some embodiments, the top portion 168 is wider than the middle portion 166. According to some embodiments, the middle portion 166 is wider than the lower portion 164.

[0102] According to some embodiments, the width W168 of the top 168 increases toward the base 110. According to some embodiments, the width W168 of the top 168 increases continuously toward the base 110.

[0103] Figure 1E-2 According to some embodiments, the following is shown: Figure 1E-1 A cross-sectional schematic diagram of the semiconductor device structure along section line II-II'. According to some embodiments, such as... Figure 1E-1 and Figure 1E-2 As shown, the waveguide portion 116wg is in direct contact with the light absorption structure 160, which improves the light absorption efficiency of the light absorption structure 160.

[0104] According to some embodiments, such as Figure 1E-1 As shown, the width W1 of the waveguide portion 116wg is less than the length L1 of the waveguide portion 116wg. According to some embodiments, the length L1 is measured along the longitudinal axis V1 of the waveguide portion 116wg.

[0105] According to some embodiments, the width W2 of the light-absorbing structure 160 is less than the length L2 of the light-absorbing structure 160. According to some embodiments, the length L2 is measured along the longitudinal axis V2 of the light-absorbing structure 160. According to some embodiments, the longitudinal axis V1 is substantially parallel to the longitudinal axis V2.

[0106] According to some embodiments, the P-type region 116p1, the N-type region 116n1, the heavily P-type doped region 116p2, the heavily N-type doped region 116n2, the P-type films 152 and 154, the light absorption structure 160, and the multiplication portion 116m of the semiconductor layer 116 together form an avalanche photodetector (APD) 101 with separation-absorption-charge-multiplication (SACM).

[0107] According to some embodiments, such as Figure 1E-2 As shown, a light-absorbing structure 160 is used to absorb light L from the waveguide portion 116 WG. According to some embodiments, the light can bombard the atoms of the light-absorbing structure 160 to generate electron-hole pairs.

[0108] According to some embodiments, electrons from electron-hole pairs are injected into the p-type film 154. According to some embodiments, the p-type film 154 serves as a (signal) charge accelerating layer. According to some embodiments, electrons in the p-type film 154 are accelerated.

[0109] According to some embodiments, since the P-type film 154 is formed by an epitaxial process (rather than an implantation process), the thickness of the P-type film 154 can be precisely controlled, which improves the performance of the absorption and charge multiplication separation avalanche photodetector 101.

[0110] Furthermore, according to some embodiments, since the P-type films 152 and 154 are spaced apart from the bottom surface 160b of the light absorption structure 160, this prevents dopants of the P-type films 152 and 154 from diffusing from the bottom surface 160b into the light absorption structure 160.

[0111] Therefore, according to some embodiments, the diffusion of dopants from the P-type films 152 and 154 into the light absorption structure 160 is reduced, which improves the performance of the light absorption structure 160.

[0112] Subsequently, according to some embodiments, (accelerated) electrons are injected into the multiplication portion 116m of the semiconductor layer 116. According to some embodiments, the multiplication portion 116m serves as a charge multiplication structure, which increases the (signal) charge and thus amplifies the electronic signal.

[0113] Since the multiplication section 116m is made of silicon, which has a very low impact ionization coefficient (approximately 0.01), the excessive noise generated by the multiplication section 116m is reduced, which improves the signal-to-noise ratio of the absorption and charge multiplication separation avalanche photodetector 101.

[0114] According to some embodiments, the light-absorbing structure 160 is made of a semiconductor material, such as germanium. According to some embodiments, the light-absorbing structure 160 is formed using an epitaxial process.

[0115] According to some embodiments, since the P-type films 152 and 154 are formed by an epitaxial process (rather than an implantation process), the P-type films 152 and 154 have a high-quality crystalline structure, which helps the light-absorbing structure 160 to have a high-quality crystalline structure. Therefore, according to some embodiments, the performance of the light-absorbing structure 160 is improved.

[0116] According to some embodiments, such as Figure 1E , Figure 1E-1 , Figure 1E-2 As shown, a capping layer 170 is formed above the light-absorbing structure 160. According to some embodiments, the capping layer 170 conformably covers the light-absorbing structure 160. According to some embodiments, the capping layer 170 directly contacts the light-absorbing structure 160.

[0117] According to some embodiments, the capping layer 170 directly contacts the insulating layer 140. According to some embodiments, the capping layer 170 has a convex top surface 172. According to some embodiments, the capping layer 170 has a convex curved surface. According to some embodiments, the capping layer 170 is used to protect the light-absorbing structure 160 from damage.

[0118] According to some embodiments, the capping layer 170 is made of a semiconductor material, such as silicon. According to some embodiments, the capping layer 170 is formed using an epitaxial process. In this step, according to some embodiments, a semiconductor device structure 100 is substantially formed.

[0119] Figure 2 A schematic cross-sectional view of a semiconductor device structure 200 is shown according to some embodiments. According to some embodiments, such as... Figure 2 As shown, the semiconductor device structure 200 is similar to Figure 1E The semiconductor device structure 100, except that the P-type film 152 of the semiconductor device structure 200 does not have a horizontal portion 152a, and the P-type film 154 of the semiconductor device structure 200 does not have a horizontal portion 154a.

[0120] According to some embodiments, the P-type membrane 152 is generally rectangular. According to some embodiments, the P-type membrane 154 is generally rectangular.

[0121] The processes and materials used to form the semiconductor device structure 200 may be similar to or the same as those used to form the semiconductor device structure 100. Figures 1A to 2 Elements marked with the same reference numerals have the same or similar structure and materials. Therefore, their detailed descriptions will not be repeated here.

[0122] According to some embodiments, a semiconductor device structure and a method for forming the same are provided. The method (for forming the semiconductor device structure) involves forming a P-type film between a light-absorbing structure and a P-type region, and between a light-absorbing structure and an N-type region, using an epitaxial process. Since the P-type film is formed via an epitaxial process (rather than an implantation process), the thickness of the P-type film can be precisely controlled, which improves the performance of the semiconductor device structure.

[0123] According to some embodiments, a semiconductor device structure is provided, the semiconductor device structure including a substrate including a P-type region and an N-type region, the P-type region and the N-type region being spaced apart from each other; the semiconductor device structure including a light-absorbing structure located between the P-type region and the N-type region in the substrate; the semiconductor device structure including a first P-type film located between the light-absorbing structure and the P-type region; the semiconductor device structure including a second P-type film located between the light-absorbing structure and the N-type region, wherein a portion of the substrate separates the second P-type film from the N-type region.

[0124] In some other embodiments, the above-described semiconductor device structure further includes a first isolation structure through a first portion of the substrate above the P-type region; and a second isolation structure through a second portion of the substrate above the N-type region.

[0125] In some other embodiments, the substrate further includes: a heavily p-type doped region located above and connected to the p-type region, wherein a first isolation structure is located between the heavily p-type doped region and the first p-type film; and a heavily n-type doped region located above and connected to the n-type region, wherein a second isolation structure is located between the heavily n-type doped region and the second p-type film.

[0126] In some other embodiments, the semiconductor device structure further includes an insulating layer located above the substrate, the first isolation structure, and the second isolation structure.

[0127] In some other embodiments, the above-described semiconductor device structure further includes a capping layer that compliantly covers the light-absorbing structure.

[0128] In some other embodiments, the capping layer directly contacts the insulating layer.

[0129] In some other embodiments, the first P-type membrane has an L-shape in a cross-sectional view.

[0130] In some other embodiments, the first P-type membrane extends into the P-type region.

[0131] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate, including a P-type region and an N-type region, the P-type region and the N-type region being spaced apart from each other; the semiconductor device structure includes a first P-type film located in the substrate and connected to the P-type region; the semiconductor device structure includes a second P-type film located in the substrate and between the first P-type film and the N-type region, the second P-type film being spaced apart from the N-type region; the semiconductor device structure includes a light-absorbing structure located in the substrate and connected between the first P-type film and the second P-type film.

[0132] In some other embodiments, the first P-type membrane and the second P-type membrane are made of the same material.

[0133] In some other embodiments, the semiconductor device structure further includes a first insulating structure and a second insulating structure located in a substrate, wherein a waveguide portion of the substrate is located between the first insulating structure and the second insulating structure, and the waveguide portion is in direct contact with the light-absorbing structure.

[0134] In some other embodiments, the first top surface of the first P-type film is substantially flush with the second top surface of the substrate.

[0135] In some other embodiments, the third top surface of the second P-type membrane is substantially flush with the second top surface of the substrate.

[0136] According to some embodiments, a method for forming a semiconductor device structure is provided. This method includes forming a P-type region and an N-type region in a substrate, the P-type region and the N-type region being spaced apart from each other; the method includes partially removing the substrate between the P-type region and the N-type region to form a first trench in the substrate, the first trench exposing the P-type region; the method includes forming a first P-type film and a second P-type film in the first trench, the first P-type film being located on the P-type region exposed through the first trench, the second P-type film being located between the first P-type film and the N-type region, the first P-type film and the second P-type film being spaced apart from each other, and the second P-type film and the N-type region being spaced apart from each other by a portion of the substrate; the method includes forming a light-absorbing structure in the first trench and above the first P-type film and the second P-type film.

[0137] In some other embodiments, the method further includes forming a first isolation structure and a second isolation structure in the substrate before forming the P-type region and the N-type region, wherein the first isolation structure passes through a first portion of the substrate above the P-type region and the second isolation structure passes through a second portion of the substrate above the N-type region.

[0138] In some other embodiments, the method further includes forming a heavily P-type doped region and a heavily N-type doped region in the substrate, wherein the heavily P-type doped region is located above and connected to the P-type region, a first isolation structure is located between the heavily P-type doped region and the first P-type film, the heavily N-type doped region is located above and connected to the N-type region, and a second isolation structure is located between the heavily N-type doped region and the second P-type film.

[0139] In some other embodiments, the method further includes forming an insulating layer over the substrate after forming the P-type and N-type regions and before partially removing the substrate between the P-type and N-type regions; and partially removing the insulating layer to form an opening in the insulating layer, wherein the opening is located over a first trench in the substrate.

[0140] In some other embodiments, the steps of forming the first P-type membrane and the second P-type membrane include forming a P-type layer in a first trench in the substrate; and partially removing the P-type layer to form a second trench in the P-type layer, wherein the P-type layer is divided into the first P-type membrane and the second P-type membrane by the second trench.

[0141] In some other embodiments, the P-type layer is formed using an epitaxial process.

[0142] In some other embodiments, the method further includes forming a capping layer over the light-absorbing structure, wherein the capping layer conformably covers the light-absorbing structure.

[0143] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various perspectives. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device structure, characterized by, Comprising: a substrate comprising a P-type region and an N-type region, wherein the P-type region and the N-type region are spaced apart from each other; a light absorption structure between the P-type region and the N-type region in the substrate; a first P-type film between the light absorption structure and the P-type region; and a second P-type film between the light absorption structure and the N-type region, wherein a portion of the substrate separates the second P-type film and the N-type region.

2. The semiconductor device structure of claim 1, wherein, Further comprising: a first isolation structure through a first portion of the substrate above the P-type region; and a second isolation structure through a second portion of the substrate above the N-type region.

3. The semiconductor device structure of claim 2, wherein, The substrate further comprises: a heavy P-type doped region above and connected to the P-type region, wherein the first isolation structure is between the heavy P-type doped region and the first P-type film; and a heavy N-type doped region above and connected to the N-type region, wherein the second isolation structure is between the heavy N-type doped region and the second P-type film.

4. The semiconductor device structure of claim 3, wherein, Further comprising: an insulating layer above the substrate, the first isolation structure, and the second isolation structure.

5. The semiconductor device structure of claim 4, wherein, Further comprising: a cap layer conformally covering the light absorption structure.

6. The semiconductor device structure of claim 5, wherein, The cap layer directly contacts the insulating layer.

7. The semiconductor device structure of any one of claims 1 to 6, wherein, In a cross-sectional view of the first P-type film, the first P-type film has an L-shape.

8. The semiconductor device structure of any one of claims 1 to 6, wherein, The first P-type film extends into the P-type region.

9. A semiconductor device structure, characterized by, Comprising: a substrate comprising a P-type region and an N-type region, wherein the P-type region and the N-type region are spaced apart from each other; a first P-type film in the substrate and connected to the P-type region; a second P-type film in the substrate and between the first P-type film and the N-type region, wherein the second P-type film is spaced apart from the N-type region; and a light absorption structure in the substrate and connected between the first P-type film and the second P-type film.

10. The semiconductor device structure of claim 9, wherein, Further comprising: a first insulating structure and a second insulating structure in the substrate, wherein a waveguide portion of the substrate is between the first insulating structure and the second insulating structure, and the waveguide portion directly contacts the light absorption structure.

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