Double-mainboard computer power supply control circuit

Abstract

The utility model provides a double-mainboard computer power supply control circuit which comprises a power supply, a first mainboard and a second mainboard. The first mainboard is connected to a first power supply module of a power supply and comprises a first power supply button and a first control unit connected to the first power supply button. The first control unit comprises a first GPIO interface and a second GPIO interface. The second mainboard is connected to a second power supply module of the power supply and comprises a second power supply button and a second control unit connected to the second power supply button. The second power button is electrically connected to the first GPIO interface. The second control unit includes a third GPIO interface electrically connected to the second GPIO interface. The first control unit controls the first mainboard to be powered on or powered off when receiving the power-on key signal or the system shutdown instruction, and transmits the power-on key signal or the power-off key signal to a second power supply key of the second mainboard at the same time, so that the second control unit synchronously controls the second mainboard to be powered on or powered off. According to the utility model, synchronous power-on and synchronous power-off of the two mainboards of the computer can be realized.

Description

TECHNICAL FIELD

[0001] The utility model relates to computer technical field especially relates to a double mainboard computer power control circuit. BACKGROUND

[0002] The mainboard is one of the most basic and important components of the computer, which connects all hardware devices of the computer to make them work cooperatively, thus playing an important role in the whole computer system.

[0003] With the popularity of computers in people's work and life, the use scenarios of computers are more and more diverse, and people have higher and higher requirements for the running ability of computers. In practical applications, in order to meet the special application requirements of users, some computers are provided with two mainboards, each of which has a separate use scenario, and thus each mainboard has its own processor (such as a central processing unit) and control unit (such as an embedded controller) and can run independently.

[0004] Although two mainboards can be provided in a computer, the computer usually has only one power-on button, and how to control the power-on and power-off of the two mainboards by one power-on button is a problem faced by such computers with two mainboards. On this basis, how to make the two mainboards of such computers be powered on and powered off synchronously to meet the use requirements of users in certain situations is also a difficult problem.

[0005] In particular, if the two mainboards of the computer can be powered by the same standard power supply, it will make the above-mentioned problem more difficult to solve. SUMMARY

[0006] The utility model aims at providing a double mainboard computer power control circuit, which can realize the synchronous power-on and power-off of the two mainboards of the computer.

[0007] The utility model aims at providing a double mainboard computer power control circuit, which can realize the synchronous power-on and power-off of the two mainboards of the computer.

[0008] To achieve the above-mentioned purpose, the utility model provides a double mainboard computer power control circuit, which comprises:

[0009] A power supply comprising a first power module and a second power module;

[0010] A first mainboard connected to the first power module and comprising a first power button and a first control unit connected to the first power button, the first control unit comprising a first GPIO interface and a second GPIO interface;

[0011] a second mainboard connected to the second power module and comprising a second power button and a second control unit connected to the second power button, the second power button being electrically connected to the first GPIO interface, and the second control unit comprising a third GPIO interface electrically connected to the second GPIO interface;

[0012] wherein the first control unit controls the first mainboard to power on when receiving a first power-on button signal transmitted by the first power button, and simultaneously transmits a second power-on button signal to the second power button through the first GPIO interface, and the second control unit controls the second mainboard to power on when the second power button receives the second power-on button signal;

[0013] the first control unit controls the first mainboard to power off when receiving a system shutdown instruction of the first mainboard, and simultaneously transmits a power-off button signal to the second power button through the first GPIO interface, the second control unit controls the second mainboard to power off when the second power button receives the power-off button signal, and transmits a power-off completion signal to the second GPIO interface through the third GPIO interface when the second mainboard powers off, and the first control unit closes the power supply when the second GPIO interface receives the power-off completion signal.

[0014] Preferably, the power supply is an ATX power supply, the first power module is a 24-pin power interface of the power supply, and the second power module is a 4-pin power interface of the power supply.

[0015] Preferably, the P3V3SB power supply of the first mainboard is obtained by power conversion from a P5VSB power supply provided by the first power module, and the P3V3SB power supply of the second mainboard is obtained by power conversion from a P12V power supply provided by the second power module.

[0016] Preferably, the dual-mainboard computer power supply control circuit further comprises a level isolation circuit between the first GPIO interface of the first control unit of the first mainboard, the second GPIO interface, and the second power button of the second mainboard and the third GPIO interface of the second control unit.

[0017] Preferably, the level isolation circuit comprises a first level isolation circuit connected between the first GPIO interface and the second GPIO interface, the first GPIO interface transmits the second power-on button signal and the power-off button signal through the first level isolation circuit, and the second GPIO interface receives the power-off completion signal through the first level isolation circuit.

[0018] Preferably, the level isolation circuit comprises a second level isolation circuit, the second level isolation circuit is connected to the second power button and the third GPIO interface, the second power button receives the second power-on button signal and the power-off button signal through the second level isolation circuit, and the third GPIO interface transmits the power-off completion signal through the second level isolation circuit.

[0019] Preferably, the level isolation circuit further comprises a second level isolation circuit and a connector, the second level isolation circuit is connected to the second power button and the third GPIO interface, and the connector connects the first level isolation circuit and the second level isolation circuit, wherein the first GPIO interface transmits the second power-on button signal and the power-off button signal to the second power button through the first level isolation circuit, the connector and the second level isolation circuit; and the third GPIO interface transmits the power-off completion signal to the second GPIO interface through the second level isolation circuit, the connector and the first level isolation circuit.

[0020] Preferably, the first level isolation circuit comprises a first NMOS tube and a second NMOS tube, the first GPIO interface transmits the second power-on button signal and the power-off button signal to the first input end of the connector through the first NMOS tube, wherein the source of the first NMOS tube is connected to the first GPIO interface and connected to the P3V3SB power supply of the first mainboard through a first resistor, the gate of the first NMOS tube is connected to the P3V3SB power supply of the first mainboard, and the drain of the first NMOS tube is connected to the first input end of the connector and connected to the P3V3SB power supply of the first mainboard through a second resistor; the second GPIO interface receives the power-off completion signal transmitted by the first output end of the connector through the second NMOS tube, wherein the source of the second NMOS tube is connected to the second GPIO interface and connected to the P3V3SB power supply of the first mainboard through a third resistor, the gate of the second NMOS tube is connected to the P3V3SB power supply of the first mainboard, the drain of the second NMOS tube is connected to the P3V3SB power supply of the first mainboard through a fourth resistor, and the drain of the second NMOS tube is also connected to the first output end of the connector.

[0021] Preferably, the second level isolation circuit comprises a third NMOS transistor and a fourth NMOS transistor, the second power button receives the second power-on button signal and the power-off button signal transmitted by the second output end of the connector through the third NMOS transistor, wherein the source of the third NMOS transistor is connected to the second power button, the gate of the third NMOS transistor is connected to the P3V3SB power supply of the second mainboard, and the drain of the third NMOS transistor is connected to the second output end of the connector; the third GPIO interface transmits the power-off completion signal to the second input end of the connector through the fourth NMOS transistor, wherein the source of the fourth NMOS transistor is connected to the third GPIO interface and connected to the P3V3SB power supply of the second mainboard through a fifth resistor, the gate of the fourth NMOS transistor is connected to the P3V3SB power supply of the second mainboard, the drain of the fourth NMOS transistor is connected to the P3V3SB power supply of the second mainboard through a sixth resistor, and the drain of the fourth NMOS transistor is also connected to the second input end of the connector.

[0022] Preferably, the control unit is an embedded controller.

[0023] The double-mainboard computer power control circuit of the utility model timely transmits the power-on button signal (second power-on button signal) or the power-off button signal to the second mainboard through the first control unit of the first mainboard, can make the first mainboard and the second mainboard synchronous power information, and then controls the power-on or power-off process of the mainboard where it is located through the first control unit of the first mainboard and the second control unit of the second mainboard, realizes the synchronous power-on or synchronous power-off of the first mainboard and the second mainboard. BRIEF DESCRIPTION OF DRAWINGS

[0024] For further understanding of the features and technical contents of the present application, please refer to the following detailed description and drawings of the present application. However, the drawings are provided for reference and illustration only, and are not intended to limit the present application. In the drawings,

[0025] Figure 1 The circuit structure block diagram of the dual-mainboard computer power control circuit of the embodiment of the present application.

[0026] Figure 2 The power supply circuit diagram of the first power module when the power supply is an ATX power supply in the embodiment of the present application.

[0027] Figure 3 The power supply circuit diagram of the second power module when the power supply is an ATX power supply in the embodiment of the present application.

[0028] Figure 4 The circuit structure block diagram when the dual-mainboard computer power control circuit of the embodiment of the present application is provided with a level isolation circuit.

[0029] Figure 5 The circuit wiring diagram of the level isolation circuit of the dual-mainboard computer power control circuit of the embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to further illustrate the technical means adopted by the present application and its effects, the following describes the preferred embodiments of the present application and its drawings in detail.

[0031] The present application provides a dual-mainboard computer power control circuit, which can synchronize power supply information of two mainboards, and realize synchronous power-on and synchronous power-off of two mainboards of a computer.

[0032] As shown in Figure 1 The present application provides a dual-mainboard computer power control circuit, which includes a power supply 10, a first mainboard 20 and a second mainboard 30. The power supply 10 includes a first power module 11 and a second power module 12. The first mainboard 20 is connected to the first power module 11 and includes a first power button 21 and a first control unit 22 connected to the first power button 21, and the first control unit 22 includes a first GPIO interface 221 and a second GPIO interface 222. The second mainboard 30 is connected to the second power module 12 and includes a second power button 31 and a second control unit 32 connected to the second power button 31, and the second power button 31 is electrically connected to the first GPIO interface 221, and the second control unit 32 includes a third GPIO interface 321, and the third GPIO interface 321 is electrically connected to the second GPIO interface 222.

[0033] The first control unit 22 controls the first mainboard 20 to power on when receiving the first power-on button signal transmitted by the first power button 21, and simultaneously transmits a second power-on button signal to the second power button 31 through the first GPIO interface 221; the second control unit 32 controls the second mainboard 30 to power on when the second power button 31 receives the second power-on button signal.

[0034] The first control unit 22 controls the first mainboard 20 to power off when receiving the system shutdown instruction of the first mainboard 20, and simultaneously transmits a power-off button signal to the second power button 31 through the first GPIO interface 221; the second control unit 32 controls the second mainboard 30 to power off when the second power button 31 receives the power-off button signal, and transmits a power-off completion signal to the second GPIO interface 222 through the third GPIO interface 321 when the second mainboard 30 is powered off; the first control unit 22 closes the power supply 10 when the second GPIO interface 222 receives the power-off completion signal.

[0035] Therefore, the dual-mainboard computer power supply control circuit of the utility model can make the first mainboard 20 and the second mainboard 30 synchronize power supply information by transmitting the power-on button signal (second power-on button signal) or power-off button signal to the second mainboard 30 in time through the first control unit 22 of the first mainboard 20, and can realize synchronous power-on or synchronous power-off by controlling the power-on and power-off processes of the mainboards where the first control unit 22 and the second control unit 32 are located. Moreover, in the power-off process, the first mainboard 20 closes the power supply 10 only after receiving the power-off completion signal transmitted by the second mainboard 30, which can ensure that the second mainboard 30 has been powered off before the power supply 10 is closed, thereby avoiding the damage of the hard disk, memory and other hardware on the second mainboard 30 caused by abnormal shutdown.

[0036] Specifically, in the dual-mainboard computer power supply control circuit of the utility model, the second mainboard 30 can be regarded as a slave board, and the first mainboard 20 controls the start of the power-on and power-off processes of the second mainboard 30, so as to realize the synchronous power-on and synchronous power-off of the second mainboard 30 and the first mainboard 20.

[0037] The first mainboard 20 and the second mainboard 30 are respectively connected to the first power module 11 and the second power module 12 of the power supply 10.

[0038] When the computer is powered on, when the first power button 21 of the first motherboard 20 is pressed, the first power button 21 generates the first power-on button signal, and the first control unit 22 controls the first motherboard 20 to start the power-on process based on the first power-on button signal. At the same time, the second power-on button signal is transmitted to the second power button 31 through the first GPIO interface 221, so that the second control unit 32 controls the second motherboard 30 to start the power-on process based on the second power-on button signal, thereby realizing the synchronous power-on of the first motherboard 20 and the second motherboard 30.

[0039] When the computer is powered off, when the first control unit 22 receives the system shutdown instruction of the first motherboard 20, the first control unit 22 controls the first motherboard 20 to start the power-off process, and at the same time, the power-off button signal is transmitted to the second power button 31 through the first GPIO interface 221, so that the second control unit 32 controls the second motherboard 30 to start the power-off process based on the power-off button signal, thereby realizing the synchronous power-off of the first motherboard 20 and the second motherboard 30. However, the first control unit 22 controls the first motherboard 20 to start the power-off process, but does not directly complete the power-off process of the first motherboard 20, but remains in the current state when the power-off process of the first motherboard 20 is pulled high PS-ON signal of the power supply 10 (turn off the power supply 10), until the second motherboard 30 is powered off. When the power-off completion signal is transmitted to the second GPIO interface 222 through the third GPIO interface 321, the PS-ON signal of the power supply 10 is pulled high, and the power supply 10 is turned off. In this way, it can avoid the situation that the second motherboard 30 has not completed the power-off process abnormally when the first motherboard 20 completes the power-off process alone, that is, the power supply 10 is turned off.

[0040] Further, in a preferred embodiment, the power supply 10 is an ATX power supply, specifically a standard ATX power supply (24+4PIN, 12V), the first power supply module 11 is a 24-pin power supply interface of the power supply, and the second power supply module 12 is a 4-pin power supply interface of the power supply. In this way, the first motherboard 20 receives power supply of the power supply 10 through the 24-pin power supply interface of the power supply 10, and the second motherboard 30 receives power supply of the power supply 10 through the 4-pin power supply interface of the power supply 10. The specific power supply mode of the first power supply module 11 and the second power supply module 12 can be seen in Figure 2 and Figure 3 The first control unit 22 of the first motherboard 20 can directly send PS-ON signal to the first power supply module 11 to control the opening and closing of the power supply 10.

[0041] Of course, the power supply 10 of the utility model also can not be limited to this, and other structure settings are adopted to realize the above functions.

[0042] Further, in the above preferred embodiment, the power supply 10 is realized by an ATX power supply, the second mainboard 30 is connected to the 4-pin power interface of the power supply 10, and only 12V power supply can be directly obtained, therefore, the utility model carries out power conversion on the P12V power supply provided by the second power module 12 (4-pin power interface) to obtain the P3V3SB power supply of the second mainboard 30; and the P3V3SB power supply of the first mainboard 20 is obtained by carrying out power conversion on the P5VSB power supply provided by the first power module 11. In this way, when the first mainboard 20 and the second mainboard 30 are connected to the 24-pin power interface and the 4-pin power interface of the ATX power supply 10 respectively, the first control unit 22 of the first mainboard 20 and the second control unit 32 of the second mainboard 30 can all obtain the P3V3SB power supply.

[0043] Specifically, the P3V3SB power supply of the second mainboard 30 can be obtained by carrying out power conversion on the P12V power supply provided by the second power module 12 through a first power conversion chip, and the P3V3SB power supply of the first mainboard 20 can be obtained by carrying out power conversion on the P5VSB power supply provided by the first power module 11 through a second power conversion chip. The specific conversion circuit is easy to be known by those skilled in the art, and will not be described here. The first power conversion chip can adopt a power conversion chip with a model number such as TMI3388A, and the second power conversion chip can adopt a power conversion chip with a model number such as WD1035DH-8 / TR, but is not limited to this.

[0044] Further, in an embodiment, as shown in the figure, Figure 4 The first GPIO interface 221 transmits the second power-on button signal and the power-off button signal to the second power button 31 through the level isolation circuit 40, and the third GPIO interface 321 transmits the power-off completion signal to the second GPIO interface 222 through the level isolation circuit 40.

[0045] Specifically, since the P3V3SB power supply of the first mainboard 20 and the second mainboard 30 can be provided by the first power module 11 and the second power module 12 connected to the first mainboard 20 and the second mainboard 30 respectively, that is, the P3V3SB power supply of the two is different sources, in order to prevent the first GPIO interface 221, the second GPIO interface 222 of the first control unit 22 and the second power button 31, the third GPIO interface 321 of the second control unit 32 of the second mainboard 30 from signal transmission when the leakage phenomenon occurs, the power control circuit of the double mainboard computer of the utility model sets the level isolation circuit 40 between the first GPIO interface 221, the second GPIO interface 222 and the second power button 31, the third GPIO interface 321.

[0046] In a preferred embodiment, the level isolation circuit 40 can include a first level isolation circuit, the first level isolation circuit is connected to the first GPIO interface 221 and the second GPIO interface 222, the first GPIO interface 221 transmits the second power-on button signal and the power-off button signal through the first level isolation circuit, and the second GPIO interface 222 receives the power-off completion signal through the first level isolation circuit. That is, the first level isolation circuit is arranged on the side of the first mainboard 20, and the signals output by the first GPIO interface 221 and the signals received by the second GPIO interface 222 of the first control unit 22 are level isolated.

[0047] Preferably, the first level isolation circuit can include a first field effect transistor and a second field effect transistor, the first GPIO interface 221 transmits the second power-on button signal and the power-off button signal through the first field effect transistor, and the second GPIO interface 222 receives the power-off completion signal through the second field effect transistor.

[0048] In a preferred embodiment, the level isolation circuit 40 can include a second level isolation circuit, the second level isolation circuit is connected to the second power button 31 and the third GPIO interface 321, the second power button 31 receives the second power-on button signal and the power-off button signal through the second level isolation circuit, and the third GPIO interface 321 transmits the power-off completion signal through the second level isolation circuit. That is, the second level isolation circuit is arranged on the side of the second mainboard 30, and the signals output by the third GPIO interface 321 of the second control unit 32 and the signals received by the second power button 31 are level isolated.

[0049] Preferably, the second level isolation circuit can include a third field effect transistor and a fourth field effect transistor, the second power button 31 receives the second power-on button signal and the power-off button signal through the third field effect transistor, and the third GPIO interface 321 transmits the power-off completion signal through the fourth field effect transistor.

[0050] In a preferred embodiment, the level isolation circuit 40 can include the first level isolation circuit, the second level isolation circuit, and a connector, wherein the connector connects the first level isolation circuit and the second level isolation circuit, and is used to transmit the second power-on button signal, the power-off button signal, and the power-off completion signal between the first level isolation circuit and the second level isolation circuit. Specifically, the first GPIO interface 221 transmits the second power-on button signal and the power-off button signal to the second power button 31 through the first level isolation circuit, the connector, and the second level isolation circuit; and the third GPIO interface 321 transmits the power-off completion signal to the second GPIO interface 222 through the second level isolation circuit, the connector, and the first level isolation circuit.

[0051] In a preferred embodiment, the level isolation circuit 40 can include the first level isolation circuit, the second level isolation circuit, and a connector, wherein the connector connects the first level isolation circuit and the second level isolation circuit, and is used to transmit the second power-on button signal, the power-off button signal, and the power-off completion signal between the first level isolation circuit and the second level isolation circuit. Specifically, the first GPIO interface 221 transmits the second power-on button signal and the power-off button signal to the second power button 31 through the first level isolation circuit, the connector, and the second level isolation circuit; and the third GPIO interface 321 transmits the power-off completion signal to the second GPIO interface 222 through the second level isolation circuit, the connector, and the first level isolation circuit. Figure 5 A specific embodiment of the level isolation circuit 40 is shown in FIG. 4. As shown in FIG. 4, the level isolation circuit 40 includes a first level isolation circuit 41, a second level isolation circuit 42, and a connector 43. Figure 5 The first level isolation circuit 41 includes a first field effect transistor 411 and a second field effect transistor 412. The second level isolation circuit 42 includes a third field effect transistor 421 and a fourth field effect transistor 422. The connector 43 connects the first level isolation circuit 41 and the second level isolation circuit 42.

[0052] The first level isolation circuit 41 comprises a first field effect tube and a second field effect tube, the first field effect tube is a first NMOS tube Q1, and the second field effect tube is a second NMOS tube Q2. The first GPIO interface 221 transmits the second power-on button signal and the power-off button signal (both represented by 58S_PWRBTN_IN# signal) to the first input end such as CC2 pin of the connector 43 via the first NMOS tube Q1, wherein the source of the first NMOS tube Q1 is connected to the first GPIO interface 221 and connected to the P3V3SB power supply of the first mainboard 20 via a first resistor R1, the gate of the first NMOS tube Q1 is connected to the P3V3SB power supply of the first mainboard 20, and the drain of the first NMOS tube Q1 is connected to the first input end of the connector 43 and connected to the P3V3SB power supply of the first mainboard 20 via a second resistor R2. The second GPIO interface 222 receives the power-off completion signal transmitted by the first output end such as SBU2 pin of the connector 43 via the second NMOS tube Q2, wherein the source of the second NMOS tube Q2 is connected to the second GPIO interface 222 and connected to the P3V3SB power supply of the first mainboard 20 via a third resistor R3, the gate of the second NMOS tube Q2 is connected to the P3V3SB power supply of the first mainboard 20, the drain of the second NMOS tube Q2 is connected to the P3V3SB power supply of the first mainboard 20 via a fourth resistor R4, and the drain of the second NMOS tube Q2 is also connected to the first output end of the connector 43.

[0053] The second level isolation circuit 42 comprises a third field effect tube and a fourth field effect tube, the third field effect tube is a third NMOS tube Q3, and the fourth field effect tube is a fourth NMOS tube Q4. The second power button 31 receives the second power-on button signal and the power-off button signal (both represented by 58S_PWRBTN_IN# signals) transmitted by the second output end such as a CC1 pin of the connector 43 through the third NMOS tube Q3, wherein the source of the third NMOS tube Q3 is connected to the second power button 31, the gate of the third NMOS tube Q3 is connected to the P3V3SB power supply of the second mainboard 30, and the drain of the third NMOS tube Q3 is connected to the second output end of the connector 43. The third GPIO interface 321 transmits the power-off completion signal (58S_GP90_EC) to the second input end such as an SBU1 pin of the connector 43 through the fourth NMOS tube Q4, wherein the source of the fourth NMOS tube Q4 is connected to the third GPIO interface 321 and the P3V3SB power supply of the second mainboard 30 through a fifth resistor R5, the gate of the fourth NMOS tube Q4 is connected to the P3V3SB power supply of the second mainboard 30, the drain of the fourth NMOS tube Q4 is connected to the P3V3SB power supply of the second mainboard 30 through a sixth resistor R6, and the drain of the fourth NMOS tube Q4 is also connected to the second input end of the connector 43.

[0054] Next, the working principle of the double-mainboard computer power supply control circuit of the utility model is described in combination with the embodiment of the level isolation circuit 40 shown in the figure. Figure 5

[0055] Under normal circumstances, the first GPIO interface 221 of the first control unit 22 keeps a high level state, the first NMOS tube Q1 is turned off, the drain of the first NMOS tube Q1 outputs a high level signal to the first input end of the connector 43, the second output end of the connector 43 outputs a high level signal to the drain of the third NMOS tube Q3, the third NMOS tube Q3 is turned off, and the source thereof keeps a high level state, that is, the second power button 31 keeps a high level state; the third GPIO interface 321 of the second control unit 32 keeps a high level state, the fourth NMOS tube Q4 is turned off, the drain of the fourth NMOS tube Q4 outputs a high level signal to the second input end of the connector 43, the first output end of the connector 43 outputs a high level signal to the drain of the second NMOS tube Q2, the second NMOS tube Q2 is turned off, and the source thereof keeps a high level state, that is, the second GPIO interface 222 keeps a high level state.

[0056] ​When the computer is powered on, the first power button 21 of the first mainboard 20 is pressed, the first power button 21 generates a low-level first power-on button signal, the first control unit 22 controls the first mainboard 20 to start the power-on process, and outputs a low-level second power-on button signal to the source electrode of the first NMOS tube Q1 through the first GPIO interface 221, the first NMOS tube Q1 is turned on, and the drain electrode of the first NMOS tube Q1 outputs a low-level second power-on button signal to the first input end of the connector 43, the second output end of the connector 43 outputs a low-level second power-on button signal to the drain electrode of the third NMOS tube Q3, the third NMOS tube Q3 is turned on, and the source electrode is in a low-level state, that is, the second power button 31 receives a low-level second power-on button signal, the second control unit 32 controls the second mainboard 30 to start the power-on process, thereby realizing the synchronous power-on of the first mainboard 20 and the second mainboard 30.

[0057] When the computer is powered off, the first control unit 22 generates a low-level power-off button signal when receiving the system shutdown instruction of the first mainboard 20, the first control unit 22 controls the first mainboard 20 to start the power-off process, and outputs a low-level power-off button signal to the source electrode of the first NMOS tube Q1 through the first GPIO interface 221, the first NMOS tube Q1 is turned on, and the drain electrode of the first NMOS tube Q1 outputs a low-level power-off button signal to the first input end of the connector 43, the second output end of the connector 43 outputs a low-level power-off button signal to the drain electrode of the third NMOS tube Q3, the third NMOS tube Q3 is turned on, and the source electrode is in a low-level state, that is, the second power button 31 receives a low-level power-off button signal, the second control unit 32 controls the second mainboard 30 to start the power-off process, thereby realizing the synchronous power-off of the first mainboard 20 and the second mainboard 30. When the second mainboard 30 is powered off, the second control unit 32 outputs a low-level power-off completion signal through the third GPIO interface 321, the fourth NMOS tube Q4 is turned on, the drain electrode of the fourth NMOS tube Q4 outputs a low-level power-off completion signal to the second input end of the connector 43, the first output end of the connector 43 outputs a low-level power-off completion signal to the drain electrode of the second NMOS tube Q2, the second NMOS tube Q2 is turned on, and the source electrode is in a low-level state, that is, the second GPIO interface 222 receives a low-level power-off completion signal, at this time, the first control unit 22 pulls up the PS-ON signal of the power supply 10, and the power supply 10 is turned off.

[0058] By setting the level isolation circuit 40, when the P3V3SB power supply of the first mainboard 20 and the second mainboard 30 are different sources, the first GPIO interface 221 and the second GPIO interface 222 of the first control unit 22 and the second power button 31 of the second mainboard 30 and the third GPIO interface 321 of the second control unit 32 can prevent the leakage phenomenon when signal transmission occurs. It is explained that the specific setting of the first level isolation circuit 41 and the second level isolation circuit 42 of the level isolation circuit 40 can be adjusted according to actual application, for example, the first, second, third and fourth field effect tubes are not limited to the NMOS tube described above, and the connection circuit can also be adjusted accordingly, as long as the same level isolation effect can be achieved.

[0059] In an embodiment, the first NMOS tube Q1 and the second NMOS tube Q2 can be realized by a field effect tube with a model of LBSS139DW1T1G, the third NMOS tube Q3 and the fourth NMOS tube Q4 can also be realized by a field effect tube with a model of LBSS139DW1T1G, and the connector 43 can be realized by a connector with a model of WLTE-001A, but is not limited to the above.

[0060] In an embodiment, the first control unit 20 and the second control unit 30 are both embedded controllers (EC), for example, both can be realized by an embedded controller with a model of IT8637E, but are not limited thereto.

[0061] In the utility model, the first mainboard 20 and the second mainboard 30 not only can have respective control units, but also can have respective processors (CPU), and can be independently used in the running process.

[0062] In summary, the double-mainboard computer power supply control circuit of the utility model can make the first mainboard and the second mainboard synchronize power supply information by timely transmitting the power-on button signal (the second power-on button signal) or the power-off button signal from the first control unit of the first mainboard to the second mainboard, and then controls the power-on or power-off process of the respective mainboard by the first control unit of the first mainboard and the second control unit of the second mainboard, realizes the synchronous power-on or synchronous power-off of the first mainboard and the second mainboard, and in the power-off process, the first mainboard is closed only after receiving the power-off completion signal sent by the second mainboard, which can ensure that the second mainboard has completed power-off before the power is turned off, avoids the situation that the second mainboard has not completed the power-off process abnormally when the first mainboard completes the power-off process alone.

[0063] Further, the dual-mainboard computer power control circuit can realize synchronous power-on and synchronous power-off of the two mainboards in the case that the first mainboard and the second mainboard are powered by the same standard power supply, and meanwhile, the power supply circuit of the first mainboard and the second mainboard is simplified. Moreover, the dual-mainboard computer power control circuit can also ensure that the second power-on button signal, the power-off button signal and the power-off completion signal can be safely transmitted between the first control unit and the second power button, the second control unit even if the P3V3SB power supply of the first control unit of the first mainboard and the second control unit of the second mainboard is different in origin in the case that the first mainboard and the second mainboard are powered by the same standard power supply, avoiding the situation of electric leakage.

[0064] The above description is for the ordinary skilled in the art to make other various corresponding changes and deformations according to the technical scheme and technical conception of the utility model, and all the changes and deformations shall belong to the protection scope of the utility model claim.

Claims

1. A power control circuit for a dual-motherboard computer, characterized in that, include: The power supply includes a first power module and a second power module; A first motherboard is connected to the first power module and includes a first power button and a first control unit connected to the first power button. The first control unit includes a first GPIO interface and a second GPIO interface. The second motherboard is connected to the second power module and includes a second power button and a second control unit connected to the second power button. The second power button is electrically connected to the first GPIO interface, and the second control unit includes a third GPIO interface, which is electrically connected to the second GPIO interface. Wherein, the first control unit controls the first motherboard to power on when it receives the first power button signal transmitted by the first power button, and at the same time transmits the second power button signal to the second power button through the first GPIO interface. The second control unit controls the second motherboard to power on when the second power button receives the second power button signal. When the first control unit receives the system shutdown command from the first motherboard, it controls the first motherboard to power down and simultaneously transmits a power-down button signal to the second power button via the first GPIO interface. When the second power button receives the power-down button signal, the second control unit controls the second motherboard to power down, and when the power-down of the second motherboard is completed, it transmits a power-down completion signal to the second GPIO interface via the third GPIO interface; when the first control unit receives the power-down completion signal at the second GPIO interface, it shuts down the power supply.

2. The dual-motherboard computer power control circuit according to claim 1, characterized in that, The power supply is an ATX power supply, the first power module is a 24-pin power interface of the power supply, and the second power module is a 4-pin power interface of the power supply.

3. The dual-motherboard computer power control circuit according to claim 2, characterized in that, The P3V3SB power supply of the first motherboard is obtained by power conversion of the P5VSB power supply provided by the first power module, and the P3V3SB power supply of the second motherboard is obtained by power conversion of the P12V power supply provided by the second power module.

4. The dual-motherboard computer power control circuit according to claim 1, 2, or 3, characterized in that, The dual-motherboard computer power control circuit also provides a level isolation circuit between the first GPIO interface and the second GPIO interface of the first control unit of the first motherboard and the second power button of the second motherboard and the third GPIO interface of the second control unit.

5. The dual-motherboard computer power control circuit according to claim 4, characterized in that, The level isolation circuit includes a first level isolation circuit, which is connected to the first GPIO interface and the second GPIO interface. The first GPIO interface transmits the second power-on button signal and the power-off button signal through the first level isolation circuit, and the second GPIO interface receives the power-off completion signal through the first level isolation circuit.

6. The dual-motherboard computer power control circuit according to claim 4, characterized in that, The level isolation circuit includes a second level isolation circuit, which is connected to the second power button and the third GPIO interface. The second power button receives the second power-on button signal and the power-off button signal through the second level isolation circuit, and the third GPIO interface transmits the power-off completion signal through the second level isolation circuit.

7. The dual-motherboard computer power control circuit according to claim 5, characterized in that, The level isolation circuit further includes a second level isolation circuit and a connector. The second level isolation circuit is connected to the second power button and the third GPIO interface. The connector is connected to the first level isolation circuit and the second level isolation circuit. The first GPIO interface transmits the second power-on button signal and the power-off button signal to the second power button via the first level isolation circuit, the connector, and the second level isolation circuit. The third GPIO interface transmits the power-off completion signal to the second GPIO interface via the second level isolation circuit, the connector, and the first level isolation circuit.

8. The dual-motherboard computer power control circuit according to claim 7, characterized in that, The first level isolation circuit includes a first NMOS transistor and a second NMOS transistor. The first GPIO interface transmits the second power-on button signal and the power-off button signal to the first input terminal of the connector via the first NMOS transistor. The source of the first NMOS transistor is connected to the first GPIO interface and connected to the P3V3SB power supply of the first motherboard via a first resistor. The gate of the first NMOS transistor is connected to the P3V3SB power supply of the first motherboard. The drain of the first NMOS transistor is connected to the first input terminal of the connector and connected to the P3V3SB power supply of the first motherboard via a second resistor. The second GPIO interface receives the power-off completion signal transmitted from the first output terminal of the connector via the second NMOS transistor. The source of the second NMOS transistor is connected to the second GPIO interface and connected to the P3V3SB power supply of the first motherboard via a third resistor. The gate of the second NMOS transistor is connected to the P3V3SB power supply of the first motherboard. The drain of the second NMOS transistor is connected to the P3V3SB power supply of the first motherboard via a fourth resistor. The drain of the second NMOS transistor is also connected to the first output terminal of the connector.

9. The dual-motherboard computer power control circuit according to claim 8, characterized in that, The second level isolation circuit includes a third NMOS transistor and a fourth NMOS transistor. The second power button receives the second power-on button signal and the power-off button signal transmitted from the second output terminal of the connector via the third NMOS transistor. The source of the third NMOS transistor is connected to the second power button, the gate of the third NMOS transistor is connected to the P3V3SB power supply of the second motherboard, and the drain of the third NMOS transistor is connected to the second output terminal of the connector. The third GPIO interface transmits the power-off completion signal to the second input terminal of the connector via the fourth NMOS transistor. The source of the fourth NMOS transistor is connected to the third GPIO interface and connected to the P3V3SB power supply of the second motherboard via a fifth resistor. The gate of the fourth NMOS transistor is connected to the P3V3SB power supply of the second motherboard, the drain of the fourth NMOS transistor is connected to the P3V3SB power supply of the second motherboard via a sixth resistor, and the drain of the fourth NMOS transistor is also connected to the second input terminal of the connector.

10. The dual-motherboard computer power control circuit according to claim 1, characterized in that, The control unit is an embedded controller.

Images