Analog cell structure and analog circuit device

Abstract

The utility model provides an analog unit structure and an analog circuit device. The analog circuit device includes a bottom metal wiring layer including a plurality of tracks and an analog cell including an n-type metal oxide semiconductor (NMOS) active region and a p-type metal oxide semiconductor (PMOS) active region, a plurality of polysilicon layers, and a plurality of metal diffusion layers. In the simulation device, an NMOS (N-channel Metal Oxide Semiconductor) active region, a PMOS (P-channel Metal Oxide Semiconductor) active region, a plurality of polycrystalline silicon layers and a plurality of metal diffusion layers form a CMOS (Complementary Metal Oxide Semiconductor) structure. The apparatus also includes a plurality of guard ring cells surrounding the analog cell and a power rail structure configured to provide a connection between the bottom metal wiring layer and the analog cell.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of analog unit structure and analog circuit device. BACKGROUND

[0002] Generally, analog design includes front-side routing for signal and power / ground (P / G) transmission. This can result in insufficient front-side routing area, leading to large IR drop. To alleviate this problem, backside signal and / or P / G routing can be provided. SUMMARY

[0003] The utility model provides a kind of analog circuit device, comprising: metal routing layer, including multiple tracks;Analog unit, including n-type metal oxide semiconductor active region and p-type metal oxide semiconductor active region, multiple polysilicon layers and multiple metal diffusion layers, wherein the n-type metal oxide semiconductor active region, the p-type metal oxide semiconductor active region, the multiple polysilicon layers and the multiple metal diffusion layers constitute CMOS structure;Multiple guard ring units, surround the analog unit;And power rail structure is configured to provide backside routing to the analog unit by providing connection between the metal routing layer and the analog unit.

[0004] In some embodiments, the utility model provides a kind of method for manufacturing integrated circuit, comprising: forming first active region and second active region in first region;Forming first multiple polysilicon layers in the first region, forming second multiple polysilicon layers in second region;Form multiple metal diffusion layers in the first region;And form backside routing structure, the backside routing structure is configured to be connected to at least one of the first active region, the second active region and the first metal diffusion layer of the multiple metal diffusion layers in the first region, wherein, the first region includes analog unit, and the second region includes guard ring unit.

[0005] In some embodiments, the utility model provides a kind of analog unit structure, comprising: first feedthrough via and second feedthrough via extend in first direction and are spaced apart first distance in second direction perpendicular to the first direction;Complementary metal oxide semiconductor structure, is arranged between the first feedthrough via and the second feedthrough via, and includes multiple polysilicon layers, p-type metal oxide semiconductor active region, n-type metal oxide semiconductor active region and first metal diffusion pattern;Metal routing layer;And multiple vias, wherein the first feedthrough via, the second feedthrough via and the first via of the multiple vias are configured to provide backside connection to the complementary metal oxide semiconductor structure.

[0006] In order to make the above features and advantages of the present application more obvious and easy to understand, the following embodiments are described in detail, and the drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the embodiments of the present application can be best understood by referring to the following detailed description in conjunction with the accompanying drawings in which like reference numerals indicate identical features. It is to be noted that each feature can not be drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0008] FIG. 1A and FIG. 1B is a schematic diagram depicting a cross-section of an integrated circuit device according to an embodiment.

[0009] FIG. 2 is a layout diagram depicting a cell structure of an analog circuit according to an embodiment.

[0010] FIG. 3A is a top view depicting an analog cell design according to an embodiment, FIG. 3B is a top view of an analog cell at a stage during fabrication of an integrated circuit, FIG. 3C is a cross-sectional view of the analog cell of FIG. 3B , FIG. 3D is another cross-sectional view of the analog cell of FIG. 3B .

[0011] FIG. 4 is a top view depicting an analog cell design according to another embodiment.

[0012] FIG. 5 is a top view of an analog cell and an adjacent vertical guard ring cell according to an embodiment.

[0013] FIG. 6 is a top view of an analog cell and an adjacent vertical guard ring cell according to an embodiment.

[0014] FIG. 7 is a layout diagram of an analog circuit design according to an embodiment.

[0015] FIG. 8A , FIG. 8B and FIG. 8C are block diagrams depicting example systems for implementing methods of designing integrated circuits described herein.

[0016] FIG. 9 is a flowchart depicting a method of designing an analog circuit according to an embodiment.

[0017] FIG. 10A to FIG. 10K a method of designing and fabricating an integrated circuit device according to an embodiment is depicted. FIG. 10Ais a flow diagram depicting a method of designing and fabricating an integrated circuit device in accordance with an embodiment. FIG. 10B to FIG. 10K is a schematic diagram of a cross-sectional view depicting a method of fabricating an integrated circuit device in accordance with an embodiment.

[0018] FIG. 11 is a flow diagram depicting a method of fabricating an integrated circuit in accordance with an embodiment.

[0019] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless context dictates otherwise. The drawings are not necessarily to scale, emphasis instead being placed on the relevant aspects of the embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Each example described below is provided as one possible implementation for the provided features. Other examples can be implemented using two or more of the described features. Some examples can be implemented in a different order than other examples and still accomplish the aspects described in the examples. Portions of various examples described herein can be used in combination with each other as well as in other examples to implement the features of the provided subject matter. Other steps that are addi tional to, or in place of, the described steps, are also possible and can be readily

[0021] In addition, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like can be used herein for describing the orientation of one component or feature with respect to another component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] Some embodiments of the disclosure are described. Additional operations can be provided before, during, and / or after the stages described in these embodiments. Some stages described can be replaced or eliminated for different embodiments. Additional features can be added to the circuit. Some features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed by way of example with respect to operations performed in a particular order, these operations can be performed in another logical order.

[0023] As noted above, analog circuits can include front-side P / G and signal routing, which can cause routing area shortages and large voltage drops. As a solution, feed-through vias (FTVs) can be inserted to allow backside routing of P / Gs or signal routing, such that the FTVs connect the backside routing to front-side interconnects. However, FTV insertion can create a large penalty area (i.e., an area near the FTV in which components cannot be placed without violating design rules or in other ways compromising performance). Additionally, the high cut metal gate (CMG) density associated with FTV designs can introduce process risks.

[0024] Embodiments described herein provide solutions for backside signal routing that can avoid these issues. In some embodiments, a super power rail (SPR) structure is provided for CMOS designs, which includes FTVs and backside P / G support. Additionally, embodiments described herein can employ a dual cut metal gate (CMG) process to avoid high cut poly (CPO) density.

[0025] By incorporating these features, the apparatuses and layouts described herein can incorporate inter-cell FTVs without incurring additional area loss. Additionally, the techniques described herein can result in more uniform parasitic resistance across the layout, improving mismatch characteristics. Furthermore, by employing backside routing of P / Gs or signal connections, and more specifically, exemplary SPR structures with feed-through vias and backside vias, embodiments described herein can result in lower voltage drops.

[0026] FIG. 1 is a schematic diagram depicting a cross-section of an integrated circuit apparatus, according to an embodiment. As noted above, in some integrated circuits, both P / G and signal connections are routed on the front side of the apparatus. However, this can result in large voltage drops and lower routing flexibility. By incorporating FTVs and backside via (VB) structures, these issues can be overcome. For example, as shown, the apparatus can include transistors with source / drain (S / D) components 112. The S / D components 112 can be connected to a series of conductive interconnects that provide signal and P / G routing. The interconnect structure can include a stack of metal routing layers and a series of vias that connect the metal routing layers vertically. FIG. 1A

[0027] ​In an embodiment, backside vias (VB) 120 can provide backside routing between the S / D assembly 112 and the bottom metal routing layer (BM0) 101 of the interconnect structure. The backside vias 120 can provide P / G or signal routing for the S / D assembly 112, freeing up routing area on the front side of the device. The bottom metal routing layer 101 can include a plurality of tracks spaced apart from one another. Backside vias and feedthrough vias can provide backside routing from the plurality of tracks to the structure of the device.

[0028] On the front side, the S / D assembly 112 can be connected to additional routing through a series of metal routing layers. For example, the interconnect structure can include an additional metal routing layer MD 103, a metal routing layer M0 105, and a metal routing layer Ml 107. Ml can be the top layer of the structure. In an embodiment, the metal routing layer MD can be a metal contact pattern of semiconductor material used to connect the S / D assembly. The metal routing layers can be connected through vias. For example, vias VD 121 can connect the metal routing layer MD to the metal routing layer M0.

[0029] FIG. 1B A cross-section of a device along a feedthrough via (FTV) 115 is depicted. The FTV 115 can provide a P / G or signal connection between the bottom metal routing layer 101 on the backside to another metal routing layer MD on the front side. In an embodiment, the FTV 115 and the backside vias 120 support a power rail structure for delivering backside power to the device, enabling lower voltage drops.

[0030] FIG. 2 A layout diagram of a cell structure for an analog circuit is depicted in accordance with an embodiment. The layouts described herein can allow the incorporation of the above-described P / G and / or signal connections into increasingly smaller device and node sizes, while passing design rule checks.

[0031] A design process for an analog circuit in accordance with an embodiment can use a basic building block called a cell to create complex circuits. A cell can include a pre-determined standard architecture selected to provide a particular function. These cells can include active analog cells 209 that provide functionality for the analog circuit. The cells can also include guard ring cells 203, 205, 207, and 211 that surround the analog cells to provide protection and isolation for the analog cells.

[0032] The analog cells and guard ring cells can be arranged in an array containing columns and rows. In a non-limiting example, the array can include five columns and five rows, as shown in FIG. 2

[0033] ​In one embodiment, the layout can include a plurality of analog cells 209. These cells include a particular arrangement of transistors, capacitors, or other structures sufficient to provide a specified analog function. For example, an analog cell can include an amplifier, a regulator, a comparator, a filter, or any other type of analog cell required by a particular design. The architecture of an analog cell can be stored in an analog cell library and called from the analog cell library, enabling a designer of an initial design to create complex and dense integrated circuits with less time and effort.

[0034] Each analog cell can be surrounded by a guard ring that includes a plurality of guard ring cells. For example, each analog cell 209 can be adjacent to eight guard ring cells so as to completely enclose each analog cell. Like the analog cells, the guard ring cells can include a particular arrangement of internal structures sufficient to act as a portion of a guard ring, and these structures can be stored in a database and called by a designer to produce an analog integrated circuit layout.

[0035] Depending on the location in the layout, the guard ring cells can be classified as corner guard ring cells 205, vertical guard ring cells 211, horizontal guard ring cells 203, and interior guard ring cells 207. The location of the guard ring cells can determine the structures or layout of structures within the cells. Completely enclosing each analog cell with guard ring cells can protect the analog cells from noise and can allow the circuit to meet latch-up requirements. The corner guard ring cells 205, horizontal guard ring cells 203, and vertical guard ring cells 211 can form the outer boundary of the array of cells.

[0036] FIG. 3A to FIG. 3D A view of an analog cell according to an embodiment is depicted. FIG. 3A A top view of an analog cell design according to an embodiment is depicted. The legend 399 provides guidance for understanding the structures in the design.

[0037] In one embodiment, the design can include power rail structures including FTVs 315 and backside vias (VBs) 320. The analog cell design can also include bottom metal wiring layer tracks (BM0) 301 extending in a first direction. The bottom tracks 301 can each include a first length Yl in a second direction, and the spacing between the tracks can include a second length Y2 in the second direction. In one embodiment, the second length can be greater than the first length. The spacing between the bottom tracks 301 can be set according to specific design rules. For example, in one embodiment, Yl can be 36 nm or less and Y2 can be 40 nm or less.

[0038] The FTV 315 and backside via 320 can provide P / G and signal connections to the components within the cell. For example, the analog cell can also include a plurality of poly-on (PO) layers 335, a plurality of active regions 322 / 324, a plurality of metal contact (MD) patterns 303. The PO layers 335 can extend above the active regions 322 / 324 to form a poly over diffusion edge (PODE) structure, which can allow for increased densification in the design.

[0039] The design layout of the analog cell can also include a cut poly region (CPO) 331. The MD patterns 303 can provide routing to and from the components of the analog cell. For example, the FTV 315 and backside via 320 can provide P / G and / or signal connections from the bottom metal routing layer to the components of the analog cell. In an embodiment, a process design kit used to generate the cell design can include a common description format (CDF) that allows a user to turn on and off the CPO region or change the CPO region to cut a metal diffusion (CMD) region.

[0040] The CPO and CMD regions can include areas within an IC design that remove poly-on (PO) and metal diffusion (MD) from areas of the design where the CPO and CMD layers are disposed, respectively. In an embodiment, an IC design tool (e.g., an electronic design automation (EDA) or computer-aided design (CAD) tool) can generate a design based on input instructions or desired structures. The designs generated by these tools can include CPO and CMD regions that intersect with PO and MD layers within the design. The CPO and CMD layers can cause the PO and MD layers to be removed from the intersecting regions during later stages of the process of fabricating an integrated circuit according to the design. The use of CPO and CMD regions can reduce spacing in the design without violating design rules.

[0041] In an embodiment, a method of designing and fabricating an integrated circuit can include forming a first poly-on (PO) pattern. The pattern can correspond, for example FIG. 3A to the pattern of the PO layers shown. The method can also include forming a cut poly-on (CPO) pattern that includes a plurality of CPO regions. The CPO pattern can be formed to create a plurality of overlaps between the first PO pattern and the CPO pattern. During fabrication, the poly-on can be removed from the overlapping regions, thereby forming a second PO pattern. The second PO pattern can enable the formation of CMOS structures, as will be described in greater detail below.

[0042] The analog cell can be bounded in the second direction by first and second FTVs 315A and 315B, respectively. When the analog cell design is fabricated, cutting the polysilicon regions 331 can cause the PO layers to be removed from these regions. Thus, the center cut polysilicon region can divide the analog cell into two sub- regions 350A, 350B. In addition, the center cut polysilicon region can bisect each of the plurality of PO layers into two PO segments, one in the first sub-region 350A and one in the second sub-region 350B. Each sub-region can include a third length Y3 in the second direction. In an embodiment, the third length Y3 can represent one-half of the total cell height. For example, the cell can include a total cell height of 260 nm, and the third length Y3 can include 130 nm.

[0043] In an embodiment, the analog cell can include a complementary metal-oxide-semiconductor (CMOS) layout, where the first sub-region 350A includes one of a p-type metal-oxide-semiconductor (PMOS) region and an n-type metal-oxide-semiconductor (NMOS) region, and the second sub-region 350B includes the other of the PMOS region and the NMOS region. The PMOS region and the NMOS region can include PMOS and NMOS transistors having source / drain structures.

[0044] Based on the design of FIG. 3A a device fabricated can include a CMOS device including a structure as shown, where the PO layers 335 are removed at locations corresponding to the CPO regions. In an example, the source / drain structures can be similar to the structures described above with reference to FIG. 1A The backside vias 320 can provide backside wiring between the source / drain structures located in the active regions 322 / 324 and the bottom metal. A portion of the MD pattern 303 can contact the source / drain structures on opposite sides of the backside vias, providing frontside wiring. By incorporating backside wiring through the FTV structures 315 and the backside vias 320, more area is available for frontside wiring to and from devices within the analog cell.

[0045] FIG. 3B is a top view of an analog cell depicting a stage during fabrication of an integrated circuit according to an embodiment. FIG. 3B may depict the analog cell after removal of polysilicon from regions overlapping the CPO regions. Reference number 361 can indicate regions where the PO layers have been removed. While FIG. 3B 361 is shown pointing to only two such regions, the figure outlines a number of additional boxes representing previously overlapping regions, indicating that removal can occur in any region where there is overlap between a PO and a CPO.

[0046] FIG. 3C is a top view of an analog cell depicting a stage during fabrication of an integrated circuit according to an embodiment. FIG. 3Bis shown in FIG. III-C. This cross-section can be taken along PO layer 335 of the plurality of PO layers. In an embodiment, bottom metal routing layer track (BM0) 301 can be separated from the structure of the analog cell by a base 390. For example, active regions 322 / 324 can include active fins and base 390 can be insulating. In another embodiment, base 390 can comprise a silicon-on-insulator (SOI) structure and can comprise a silicon base with a buried insulator layer between the silicon base and the active regions.

[0047] Active regions 322 / 324 can be formed over base 390. PO layer 335 can be formed to extend across both active region 322 and active region 324. In an embodiment, PO layer 335 as initially generated during the method of design simulation can extend completely across the cross-section of line III-C along FIG. 3B However, the area of PO layer 335 that intersects the designed CPO region can be removed, resulting in the arrangement of PO layer 335 as shown in FIG. 3C Removal area 361 represents the area of PO layer 335 that overlaps the designed CPO region.

[0048] In another embodiment, PO layer 335 can be an intermediate layer, described in more detail below with reference to FIG. 10B to FIG. 10K PO layer 335 can be one of a plurality of dummy electrodes, for example, which can be replaced by metal gates.

[0049] FIG. 3D is a cross-sectional view depicting a cross-section of line III-D shown in FIG. 3B Along this line, a single track of bottom metal routing layer (BM0) 301 can extend under active region 324. Active region 324 can be separated from bottom metal routing layer track 301 by a base 390. As described above, in an embodiment, active region 324 can include active fins and base 390 can comprise an insulator or SOI structure. Active region 324 can also include source / drain regions 324S / D and channel region 324C. As part of the backside metal routing provided by the embodiments described herein, backside via 320 can provide a connection between bottom metal routing layer 301 and source / drain regions 324S / D of active region 324. PO layer 335 can be formed over channel region 324C of the active region, thereby functioning as a gate in the CMOS structure of the analog cell. PO layer 335 and channel region 324C can be separated by a dielectric layer (not shown).

[0050] FIG. 4 depicts a top view of an analog cell design depicted in accordance with another embodiment. Legend 499 provides guidance in understanding the structures in the design. FIG. 4The components of the simulated unit design described above can be similar to those referenced above. FIG. 3A to FIG. 3D As described. Therefore, for clarity, some structural reference numerals may be omitted from the accompanying drawings.

[0051] In one embodiment, there may be interruptions in the CPO layer and the FTV layer to facilitate tie-off of the PO layer. For example, the interruption region 445 may include areas where the FTV structure is removed from the design and where the polysilicon is cut. This interruption region may include a horizontal width of X1 in the first direction.

[0052] Therefore, this provides space for multiple second vias (VG) 441 to provide secure connections to the PO layer. Additionally, the design may include multiple third vias (VD) 443 to provide connections to the MD pattern. In one example, vias VG are connected to the gate of the transistor in the design, and vias VD are connected to the drain of the transistor in the design. As above FIG. 1A The unit can have a total height of 260 nm. In such an embodiment, the horizontal width of the interrupted region can be 144 nm. This allows sufficient space for fastening without violating design rules.

[0053] like FIG. 1A As shown and as described above, the design may further include additional metal wiring layers M0. In one embodiment, the design may include a plurality of M0 layers 451, which extend in a first direction and are spaced apart, such as... FIG. 4 As shown. For example, multiple layers can include tags from M01 to M0. N There are N layers. To reduce resistance, an M0 layer (M01, M02, M0...) is placed at the edge of the cell. N-1 M0 N It can be used as a landing point for the second through-hole (VG) or the third through-hole (VD).

[0054] Reference above FIG. 3A to FIG. 3D The described embodiments are similar. FIG. 4 The analog cells can include a CMOS structure comprising NMOS and PMOS active regions. The active regions can contain a PODE arrangement such that the PO layer extends above the edge of the diffused region. FIG. 4 The designed and manufactured device may include a CMOS device comprising the structure shown in the figure, wherein the PO layer is removed at the location corresponding to the CPO region. By implementing an SPR structure including feedthrough vias and back-side vias, power and / or supply signals can be routed to the analog cell via the back-side, thereby preserving front-side routing space and improving voltage drop.

[0055] FIG. 5A top view of an analog cell and an adjacent vertical guard ring cell according to an embodiment is depicted. Legend 599 provides guidance in understanding the structures in the design. FIG. 5 The depicted cell can be similar to that described above with respect to FIG. 2 and FIG. 4 For clarity, the reference numerals and detailed description components already described above can be omitted, and the following description refers to additional structures.

[0056] In an embodiment, an analog cell 509 can be disposed adjacent to a vertical guard ring cell 511. In particular, the vertical guard ring cell 511 can be disposed along the left border of the layout. Notably, while FIG. 5 The vertical guard ring cell 511 along the left border of the layout is depicted, but the vertical guard ring cell along the right border of the layout includes a similar but flipped design. In FIG. 5 the cells are shown separated by blank space, but note that this space is provided for clarity and the cells can directly abut such that the features to the left of the cell 509 directly match the features to the right of the vertical guard ring cell 511.

[0057] In addition to the layers already described, an embodiment of FIG. 5 may also include a tie-PO structure 520 and an upper metal routing layer 526 (M1). The metal routing layer M0 551 of the design can include tracks that alternate between a first track M0A and a second track M0B in the second direction. The design can also include a cut metal layer 530 configured to act as a marker to cut the second track M0B (CM0B) within the design. Additionally, a plurality of VIA0 vias 528 can be provided to provide routing to the M1 layer. The design can also include a bottom metal layer BM0 (not shown) similar to those described above. Connections from the BM0 layer to the analog circuit structure can be made via backside connections through the SPR structure containing the FTV and VB.

[0058] The analog cell 509 can include an inverter structure including PMOS and NMOS devices. For example, the analog cell 509 can include a PMOS active region 522 and an NMOS active region 524. The active regions 522 and 524 can extend beyond the borders of the analog cell 509 and into the guard ring cell 511, forming a continuous oxide diffusion (CNOD) region. Based on FIG. 5 devices manufactured based on the design can include CMOS devices including structures as shown, where the PO layer is removed at locations corresponding to the CPO region and the M0B layer is removed at locations corresponding to the CM0B region.

[0059] The analog unit 509 can include a cell height Y4 in the second direction, and structures therein can define a cut poly pitch (CPP) having a width X2 in the first direction. In an embodiment, the cell height can be 260 nm.

[0060] As described above, the guard ring unit 511 can include a vertical guard ring unit disposed along the left side of the analog circuit layout. The guard ring unit 511 can directly abut an analog unit, such as the unit 509, such that the guard ring unit 511 includes structures from the analog unit (e.g., active regions 522, 524) that extend across the cell boundary. The guard ring unit 511 can also include an MD region 533 that extends from the bottom of the cell to the top of the cell in the second direction. The guard ring unit 511 can include a width in the first direction that is four times the pitch width X2 described above with respect to the analog unit 509.

[0061] The guard ring unit 511 can also include a cut metal diffusion (CMD) region 537 and a plurality of cut poly (CPO) regions 531A, 531B, 531C. The CMD and CPO regions can be configured to remove designed PO regions and MD regions from a particular region in order to provide protection and isolation for an abutting analog unit. In an embodiment, the CMD region 537 can provide an interruption in the MD region 533 during fabrication.

[0062] The guard ring unit 511 can also include a PO guard ring structure 545. In an embodiment, the PO guard ring structure 545 can include a bounded shape and can include additional extensions inside. For example, the PO guard ring structure 545 can include a rectangle with a central interior extension that spans the vertical length of the rectangle. The PO guard ring structure 545 can connect with the PO guard ring structure of an adjacent guard ring unit in order to form a continuous boundary structure along the boundary of the layout. In an embodiment, the PO guard ring structure 545 can be configured to provide protection and isolation for an adjacent analog unit.

[0063] In another embodiment, the PO guard ring structure 545 can undergo a high pressure oxidation (HPO) process to create a boundary region guard ring structure that provides protection and isolation for surrounding analog units. Thus, the guard ring structure can be insulating.

[0064] FIG. 6 is a top view of a horizontal guard ring unit 603 and an adjacent corner guard ring unit 605 according to an embodiment. The legend 699 provides guidance for understanding the structures in the design. FIG. 6 The depicted units can be similar to those described above with respect to FIG. 2 the corner guard ring unit 605 can include a cell height Y5 in the second direction, and structures therein can define a cut poly pitch (CPP) having a width X3 in the first direction. In an embodiment, the cell height Y5 can be 260 nm.FIG. 6 The top-left corner cell of the layout of FIG. 2 For clarity, the reference numbers and detailed description components already described above can be omitted, and the following description refers to additional structures.

[0065] In an embodiment, the horizontal guard ring cell 603 disposed in the top column of the analog circuit layout can be disposed adjacent to a corner guard ring cell 605 disposed in the top-left corner of the analog circuit layout. Note that while FIG. 6 The top and top-left cells are depicted, but the bottom cell can include a similar but flipped design cell 603, and the other corner cell can include a similar but flipped design to cell 605. In FIG. 6 In the embodiment, the cells are shown separated by blank space, but note that this space is provided for clarity and the cells can directly abut such that the features to the left of cell 603 directly match the features to the right of cell 605.

[0066] The horizontal guard ring cell 603 can abut the analog cell located directly below it, and thus the bottom of the horizontal guard ring cell 603 can be connected to the FTV of the analog cell. In an embodiment, the horizontal guard ring cell can include structures similar to those of the analog cell described above with reference to FIG. 6, including a PO layer, pick up active regions 622 and 624, MD regions, and M0 tracks M0A and M0B 651. The design can also include a bottom metal layer BM0 (not shown) similar to those described above. FIG. 5

[0067] Additionally, the horizontal guard ring cell 603 can include a plurality of cut poly silicon (CPO) regions 631A, 631B and cut metal diffusion (CMD) regions 661A. As described above, the CPO regions and CMD regions can indicate to the design and manufacturing tools to remove the PO regions and MD regions, respectively, from these regions. This technique can allow the design to reduce pitch without violating design rules. In an embodiment, the two CPO regions 631A, 631B can provide a double cut metal gate (CMG) structure during manufacturing. For example, during manufacturing, the poly silicon layer of the analog cell can be replaced with a metal gate structure, which can then undergo a metal gate cut process along the CPO regions. This double structure can reduce the density of CPO regions in the cell, and accordingly, the density of regions where the metal gate cut process occurs, reducing the process risk associated with CMG density. In an embodiment, these manufacturing techniques can reduce the pitch between the OD regions. For example, the spacing Y4 between adjacent OD regions can include a width of 46 nm or less.

[0068] ​In one embodiment, the corner protection ring cell 605 can include similar features as the vertical protection ring cells described above with reference to FIG. 5 For example, the corner protection ring cell 605 can abut adjacent cells 603 and can include CPO regions 631C, 631D and a CMD region 661B that connects with the cell edges. The CMD region 661B can be continuous with the CMD region 661A. The CPO region 631C can be continuous with the CPO region 631A and the CPO region 631D can be continuous with the CPO region 631B.

[0069] The corner protection ring cell 605 can also include a PO protection ring structure 645. In one embodiment, the PO protection ring structure 645 can include similar shapes as the PO protection ring structures described above with reference to FIG. 5 The PO protection ring structure 645 can terminate along the upper edge of the corner protection ring cell 605 and can connect with the PO protection ring structure of the vertical protection ring cell located below the corner protection ring cell 605. Thus, the protection ring cells can create a continuous boundary region structure along the sides of the analog circuit design. In one embodiment, the PO protection ring structure 645 can be configured to provide adjacent analog cell protection and isolation.

[0070] In another embodiment, the PO protection ring structure 645 can be an intermediate structure that is formed during the design of the analog circuit that is removed or changed during subsequent fabrication of the circuit. For example, the PO protection ring structure 645 can undergo a high pressure oxidation process (HPO) to form an insulating protection ring structure.

[0071] FIG. 7 is a layout diagram of an analog circuit design according to an embodiment. All edges of the analog CMOS cell 705 can be bounded by protection ring cells. The analog CMOS cell 705 can include SPR structures that include FTVs and backside vias to provide backside delivery of P / G and / or signal connections to the cell.

[0072] The protection ring cells can include four corner protection ring cells, two vertical protection ring cells and two horizontal protection ring cells to surround the analog CMOS cell 705. In one embodiment, the corner protection ring cells and the vertical protection ring cells can include protection ring structures similar to the PO protection ring structures described above that interface with each other to form continuous boundary region structures 710 and 712. The corner protection ring cells and the horizontal protection ring cells can include cut metal diffusion (CMD) regions 714 and 716 that extend horizontally along the top and bottom edges of the layout to remove any unwanted metal diffusion material from those regions.

[0073] According to FIG. 7An integrated circuit device designed and manufactured in accordance with the present disclosure can include the structures shown, where the CMD regions are configured to indicate removal of material from these regions. The guard ring structures 710, 712 can include PO guard rings, which can be subsequently removed and replaced, or otherwise altered to form insulating boundary region structures.

[0074] FIG. 8A 、 FIG. 8B and FIG. 8C An example system for implementing the methods described herein for designing integrated circuits is depicted. For example, FIG. 8A An example system 800 including a standalone computer architecture is depicted, where a processing system 802 (e.g., located in a given computer or located in one or more computer processors that can be separate and distinct from one another) includes a computer-implemented electronic circuit design engine 804 executing on the processing system 802. The processing system 802 can access a computer-readable memory 807 in addition to one or more data stores 808. One or more processors in the processing system 802 can be in communication with the computer-readable memory 807 that can store instructions that when executed command the one or more processors to perform operations of the methods described herein. The one or more data stores 808 can include a cell library database 810 and a circuit design database 812. In an embodiment, the cell library database 810 can contain an analog cell library. The processing system 802 can be a distributed parallel computing environment that can be used to process very large scale datasets.

[0075] FIG. 8B A system 820 including a client-server architecture is depicted. One or more user PCs 822 access one or more servers 824 running an electronic circuit design engine 837 on a processing system 827 via one or more networks 828. The one or more servers 824 can access a computer-readable memory 830 and one or more data stores 832. The one or more data stores 832 can include a cell library database 834 and a circuit design database 838.

[0076] FIG. 8C A block diagram showing example hardware for a standalone computer architecture 850, such as can be used to execute program instructions for system embodiments including and / or implementing embodiments of the present application is shown. FIG. 8AThe architecture depicted in FIG. 8 is illustrative. Bus 825 can serve as an information highway interconnecting the other illustrated components of the hardware. Processing system 854, which can be marked as CPU (Central Processing Unit) (e.g., one or more computer processors of a given computer or multiple computers), can perform computations and logical operations required for execution of programs. Non-transitory processor-readable storage media (e.g., read only memory (ROM) 858 and random access memory (RAM) 859) can be in communication with processing system 854 and can contain one or more programmatic instructions for performing a method of designing an integrated circuit. Program instructions can be stored on non-transitory computer-readable storage media, such as magnetic disks, optical disks, recordable memory devices, flash memory, or other physical storage media.

[0077] In FIG. 8A , FIG. 8B and FIG. 8C , computer-readable memory 807, 830, 858, 859 or data storage 808, 832, 883, 884, 885 can include one or more data structures for storing and associating various data used in the example system to design an integrated circuit. For example, a data structure stored in any of the foregoing locations can be used to store data from an XML file, initial parameters, and / or data for other variables described herein. Disk controller 890 connects one or more optional disk drives to system bus 825. These disk drives can be external or internal hard disk drives (e.g., 883), external or internal CD-ROM, CD-R, CD-RW or DVD drives (e.g., 884), or external or internal hard disk machines 885. In addition to physical drives, system bus 825 can also communicate with cloud-based virtual drives. As previously noted, these various disk drives and disk controllers are optional devices.

[0078] Each of the component manager, real-time data buffer, transmitter, file input processor, database index shared access memory loader, reference data buffer, and data manager can include a software application stored in one or more of the disk drives connected to disk controller 890, ROM 858, and / or RAM 859. Processor 854 can access one or more of the components as needed. Display interface 887 can allow information from bus 825 to be displayed in audio, graphic or alphanumeric format on display 880. Communication with external devices can optionally be accomplished using various communication ports 882. In addition to these computer-type components, the hardware can also include data input devices (e.g., keyboard 879) or other input devices such as microphone 881, remote control, pointing device, mouse, and / or joystick.

[0079] Additionally, the methods and systems described herein can be implemented on many different types of processing devices by program code comprising program instructions executable by a device processing subsystem for performing the methods and operations described herein. The software program instructions can include source code, object code, machine code, or any other stored data that is operable to cause a processing system to perform the methods and operations described herein, and can be in any suitable language, such as C, C++, JAVA, or any other suitable program language. However, firmware, or even appropriately designed hardware configured to perform the methods and systems described herein can also be used.

[0080] Data of the systems and methods (e.g., associations, mappings, data inputs, data outputs, intermediate data results, final data results, etc.) can be stored and executed in one or more different types of computer-executed data stores such as different types of storage devices and program constructs (e.g., RAM, ROM, flash memory, flat files, databases, program data structures, program variables, IF-THEN (or similar type) statement constructs, etc.). Note that data structures describe a format for use in organizing and storing data in a database, program, memory, or other computer-readable medium for use by a computer program.

[0081] The computer elements, software modules, functions, data stores, and data structures described herein can be directly or indirectly connected to one another in order to allow the flow of data required for their operations. It is also noted that a module or processor includes, but is not limited to, a program code element, and can be implemented as a subprogram element or as a software function element, or as an object (as in an object-oriented paradigm), or as an applet, or in a computer script language, or as another type of computer program code. The software elements and / or functions can be located on a single computer or distributed among a number of computers depending upon the circumstances.

[0082] FIG. 9 is a flowchart depicting a method of designing an analog circuit according to an embodiment. The method can begin at step 901, where an IC design tool generates an analog cell. In an embodiment, the analog cell can be a cell as described above with reference to FIG. 3A to FIG. 5 For example, and as shown at step 903, generating the analog cell can include generating a CMOS structure including a plurality of polysilicon layers, PMOS active regions, NMOS active regions, and a first metal diffusion pattern. Additionally, as shown at step 905, generating the analog cell can include generating a first plurality of cut polysilicon (CPO) regions within the device, where the CPO regions are configured to remove polysilicon from areas where the CPO regions intersect with the polysilicon layers.

[0083] The method can also include generating a plurality of vias configured to provide backside routing to the analog cell, as shown at step 907. The plurality of vias can include feedthrough vias and backside vias configured to provide P / G and / or signal connections to components of the analog cell through the backside.

[0084] At step 909, the method can also include generating a plurality of guard ring cells, wherein the analog cell is surrounded by the plurality of guard ring cells. For example, as shown in FIG. 2 Each analog cell in the analog circuit design can be surrounded by eight guard ring cells, as shown in FIG. 5 to FIG. 7 and described above. The method can also include continuing to tapeout at step 911.

[0085] FIG. 10A is a flowchart depicting a method of fabricating an integrated circuit device according to an embodiment.

[0086] The method can begin at step 1001 by generating an analog circuit design. The analog circuit design can be similar to those shown in FIG. 2 to FIG. 7 and described above. For example, the design can include a bottom metal routing layer including a plurality of tracks, an analog circuit including NMOS active regions and PMOS active regions, a plurality of polysilicon layers, a plurality of metal diffusion layers, and a plurality of cut polysilicon (CPO) regions. The NMOS active regions, the PMOS active regions, the plurality of polysilicon layers, and the plurality of metal diffusion layers form a CMOS structure. In an embodiment, a first CPO region of the plurality of CPO regions and a first polysilicon layer of the plurality of polysilicon layers include a first overlap.

[0087] The analog circuit design can also include a plurality of guard ring cells surrounding the analog cell, and a power rail structure configured to provide a connection between the bottom metal routing layer and the analog cell.

[0088] Optionally, the method can also include performing a design rule check, as shown at step 1003. By incorporating the features described above (e.g., CPO / CMD design, PO DE and CNOD diffusion regions, etc.), devices fabricated according to the embodiments described herein can include reduced sizes without violating any design rules.

[0089] At step 1005, the method can continue by initiating fabrication of a device based on the analog circuit design. Fabricating the device can include forming an analog cell including a CMOS structure and forming a polysilicon guard ring structure in a region corresponding to at least one of the guard ring cells. Forming the CMOS structure of the analog cell can include depositing a plurality of polysilicon layers corresponding to the designed PO layers. In an embodiment, the layers can be subjected to the following with respect to FIG. 10B to FIG. 10KThe further processing described.

[0090] At step 1007, the method of fabricating a device can also include replacing the polysilicon layer in the analog cell with a metal gate structure. The replacement process can include an etch process that removes the polysilicon layer without damaging other structures in the device. The space left by the removal can then be filled by depositing a metal material. The metal material can form a metal gate for one or more transistors.

[0091] At step 1009, the method can also include performing a cut metal gate (CMG) process. The cut metal gate process can remove the metal deposited at predetermined locations. In an embodiment, the predetermined locations correspond to the locations of the CPO regions in the design. The cut metal gate process can allow the metal gate to be divided into individual components and provide a smaller pitch compared to other processes.

[0092] At step 1011, the method can also include forming a backside wiring structure to provide connections to the device. For example, the backside wiring structure can include a bottom metal wiring layer and backside vias to route signals to the transistors in the analog cell.

[0093] FIG. 10B to FIG. 10K is a schematic diagram depicting a cross-sectional view of a method of fabricating an integrated circuit device in accordance with an embodiment. FIG. 10B 、 FIG. 10D 、 FIG. 10F 、 FIG. 10H and FIG. 10J depicts a first cross-section along the PO layer of the cell as described above. FIG. 10C 、 FIG. 10E 、 FIG. 10G and FIG. 10I depicts a second cross-section perpendicular to the first cross-section.

[0094] FIG. 10B to FIG. 10K Similar structures to those described above with reference to FIG. 3C to FIG. 3D may be depicted. For example, as shown in FIG. 10B to FIG. 10C , the fabrication of the analog cell can include depositing a polysilicon layer 1035 over the plurality of fins 1022, 1024, which extend from the dielectric layer 1090. In an embodiment, the polysilicon layer 1035 can be a dummy electrode layer and can be separated from the fins and the underlying substrate by a gate dielectric layer 1060. The gate dielectric layer can be a high-k dielectric material. A gate spacer 1062 can also be formed on either side of the polysilicon layer 1035.

[0095] FIG. 10D to FIG. 10E Step 1007 of FIG. 10A may be depicted. As FIG. 10D and 10EAs shown, the polysilicon layer 1035 can be removed. This removal can be selective with respect to the material of the deposited dummy electrode layer. For example, the removal process can selectively remove the polysilicon 1035 relative to the gate dielectric layer 1060 and the gate spacer 1062. In other embodiments, the gate dielectric 1060 can also be removed and replaced by a replacement gate dielectric layer. Although the embodiments described herein refer to polysilicon, other dummy materials can be used. Removal of the polysilicon layer 1035 can include one or more etching processes, such as dry etching, wet etching, reactive ion etching, or other suitable etching methods.

[0096] FIG. 10F to FIG. 10G Can depict FIG. 10A Another aspect of step 1007. For example... FIG. 10F to FIG. 10G As shown, an alternative metal gate 1068 can be formed to replace the polysilicon layer 1035. The alternative metal gate 1068 may include one or more seed layers, barrier layers and / or work function metal layers, and metal fill layers, and can be deposited using methods such as CVD, PVD, electroplating, and / or other suitable deposition processes. Forming the alternative metal gate 1068 may also include planarization processes, such as chemical mechanical polishing (CMP) and / or other suitable processes, to form the alternative gate 1068 to a desired height.

[0097] FIG. 10H to FIG. 10I Can depict FIG. 10A Step 1009, in which a metal gate dicing process may be performed. In one embodiment, the process may include forming a mask 1066 over an alternative gate 1068. The mask 1066 may include a patterned mask including gaps 1061 corresponding to the locations of CPO regions in the design. For example, the mask 1066 may be a patterned hard mask.

[0098] like FIG. 10J to FIG. 10K As shown, the metal gate dicing process may further include performing etching through the hard mask to remove a portion of the replacement gate 1068 below the gap 1061. The etching process may include wet etching, dry etching, reactive ion etching, or other suitable etching methods. This gate dicing process, removing the replacement gate 1068, can divide the deposited metal gate structure into separate portions to form a desired transistor structure within the device. For example, gate dicing can allow the formation of a CMOS structure in the analog cell region of the fabricated device. Subsequently, and as described above regarding... FIG. 10A As described in step 1011, a back-side wiring structure can be applied to route signals to and from the analog unit.

[0099] FIG. 11is a flowchart depicting a method of fabricating an integrated device. At step 1101, a first active region and a second active region can be formed in a first region of an integrated circuit device. For example, the first region can correspond to an analog cell region of the integrated circuit device, such as described above with reference to FIG. 2 The first active region and the second active region can include doped regions corresponding to source, drain, and channel regions of transistors, such as described above with reference to FIG. 3A to FIG. 3D

[0100] At step 1103, a first plurality of polysilicon layers can be formed in the first region of the integrated circuit device and a second plurality of polysilicon layers can be formed in a second region of the integrated circuit device. The second region can correspond to a guard ring cell region of the integrated circuit device. In an embodiment, each analog cell region can be surrounded by a plurality of guard ring cell regions. For example, the first plurality of polysilicon layers can include gate layers or dummy gate layers of transistors formed within the analog cells of the first region, and / or the second plurality of polysilicon layers can include polysilicon guard rings formed in the guard ring cells of the second region, as described above with reference to FIG. 3A to FIG. 3D and / or FIG. 10B to FIG. 10K

[0101] At step 1105, a first plurality of metal diffusion layers can be formed in the first region. The metal diffusion layers can provide wiring for structures within the analog cells of the first region. For example, the metal diffusion layers can include source / drain metallization structures, such as shown in FIG. 2, and can be configured to connect the analog cells to upper level wiring. FIG. 2

[0102] In an embodiment, forming the plurality of polysilicon layers and the plurality of metal diffusion layers includes generating cut polysilicon (CPO) regions and cut metal diffusion (CMD) regions. The CPO and CMD regions are generated to overlap with a pattern of the polysilicon layers and a pattern of the metal diffusion layers, respectively. During fabrication, these overlapping regions can be removed from the polysilicon pattern and the metal diffusion layer pattern to yield the final arrangement of polysilicon layers and metal diffusion layers. This process can be performed as described above with reference to FIG. 10B to FIG. 10K Alternatively or additionally, the polysilicon layers in the first region can be removed and replaced with metal gates to form metal gates.

[0103] ​​​Through these processes, an analog cell can be formed in the first region. In an embodiment, the analog cell can include a CMOS structure including NMOS active regions and PMOS active regions corresponding to the first active regions and the second active regions. In an embodiment, forming the analog cell can include forming n-type metal-oxide-semiconductor (NMOS) active regions and p-type metal-oxide-semiconductor (PMOS) active regions, forming a plurality of polysilicon layers, and forming a plurality of metal diffusion layers. The NMOS active regions, the PMOS active regions, the polysilicon layers, and the metal diffusion layers together can form the CMOS structure of the cell. The active regions can include source / drain regions and channel layers. For example, referring to FIG. 1A to FIG. 1B , forming the NMOS active regions and the PMOS active regions can include forming the source / drain components 112.

[0104] At step 1107, a backside wiring structure can be formed. The backside wiring structure can be configured to connect to at least one of the first active regions, the second active regions, and the first metal diffusion layer of the plurality of metal diffusion layers in the first region. In an embodiment, the backside wiring structure includes a power rail structure configured to provide a connection between a rail of a bottom metal wiring layer and a structure within the analog cell. In an embodiment, the power rail structure wiring can include a plurality of feedthrough vias and a plurality of backside vias. For example, referring to FIG. 1A to FIG. 1B , the backside wiring can include the feedthrough vias 115 and the backside vias 120. The backside wiring can carry signals between the first metal wiring layer BM0 and a component within the analog cell, such as the source / drain regions 112 or the metal diffusion layers 103.

[0105] In the second region, a plurality of guard ring cells can be formed. In an embodiment, the plurality of guard ring cells can be formed such that the analog cell is surrounded by the guard ring cells. For example, referring to FIG. 2 , the integrated circuit can include a plurality of analog cells, and each analog cell can be surrounded on all sides by guard ring cells of the plurality of guard ring cells. Thus, the guard ring cells can provide protection and isolation for the analog cells. For example, as described with respect to FIG. 5 and FIG. 6 , forming the plurality of guard ring cells can include generating CPO regions and CMD regions within the guard ring cells and removing polysilicon patterns and metal diffusion patterns in regions overlapping the CPO regions and the CMD regions. Thus, according to the above-described methods, an integrated circuit device including an analog cell with backside wiring surrounded by guard ring cells can be formed.

[0106] Devices and methods are described herein. In an example device, an analog circuit device includes a bottom metal routing layer including a plurality of tracks, an analog cell including n-type metal oxide semiconductor (NMOS) active regions and p-type metal oxide semiconductor (PMOS) active regions, a plurality of polysilicon layers, and a plurality of metal diffusion layers, wherein the NMOS active regions, the PMOS active regions, the plurality of polysilicon layers, and the plurality of metal diffusion layers form a CMOS structure. The active regions can include source / drain regions and / or channel regions and the active regions can include diffused dopants. The analog circuit device further includes a plurality of guard ring cells surrounding the analog cell, and a power rail structure configured to provide a connection between the bottom metal routing layer and the analog cell.

[0107] In some embodiments, the power rail structure includes at least one feedthrough via and at least one backside via. In some embodiments, the at least one feedthrough via includes a first feedthrough via and a second feedthrough via extending in a first direction and separated in a second direction, and an analog cell disposed between the first feedthrough via and the second feedthrough via. In some embodiments, the analog circuit device further includes a first break region in the first feedthrough via and a second break region in the second feedthrough via, at least one polysilicon layer of the plurality of polysilicon layers tethered in the first break region and the second break region. In some embodiments, the analog cell includes one of a plurality of analog cells. The plurality of analog cells and the plurality of guard ring cells are arranged in an array including rows and columns, and the analog cell is arranged such that each analog cell of the plurality of analog cells is surrounded by a guard ring cell of the plurality of guard ring cells. In some embodiments, the plurality of guard ring cells includes an outer boundary of guard ring cells. The outer boundary of guard ring cells includes: four corner guard ring cells; at least one horizontal guard ring cell; and at least one vertical guard ring cell. The first corner guard ring cell of the four corner guard ring cells includes a first guard ring structure; the at least one vertical guard ring cell is adjacent to the first corner guard ring cell and includes a second guard ring structure; and the first guard ring structure is connected to the second guard ring structure. In some embodiments, the analog circuit device further includes a third guard ring structure within a second corner guard ring cell, wherein the at least one vertical guard ring cell is disposed between the first corner guard ring cell and the second corner guard ring cell. In some embodiments, the n-type metal oxide semiconductor active region and the p-type metal oxide semiconductor active region of the analog cell extend outside the cell boundary. In some embodiments, the first guard ring cell of the plurality of guard ring cells includes a guard ring structure; and the guard ring structure includes a dummy structure. In some embodiments, the first guard ring cell of the plurality of guard ring cells includes a guard ring structure; and the guard ring structure includes an oxide structure. In some embodiments, the power rail structure includes a feedthrough via disposed between a first rail of the plurality of rails and a portion of a first metal diffusion layer of the plurality of metal diffusion layers and a backside via disposed between a second rail of the plurality of rails and one of the p-type metal oxide semiconductor active region and the n-type metal oxide semiconductor active region.

[0108] In an example method of fabricating an analog circuit, a first active region and a second active region are formed in a first region. A first plurality of polysilicon layers are formed in the first region, and a second plurality of polysilicon layers are formed in a second region. A plurality of metal diffusion layers are also formed in the first region. A backside routing structure is formed configured to connect to at least one of the first active region, the second active region, and a first metal diffusion layer of the plurality of metal diffusion layers in the first region. In the method, the first region includes an analog cell, and the second region includes a guard ring cell.

[0109] In some embodiments, the method further includes removing the first plurality of polysilicon layers and forming a plurality of replacement metal gate structures. In some embodiments, the dummy cell is a first dummy cell of a plurality of dummy cells and the analog cell is surrounded by the plurality of dummy cells. In some embodiments, the second plurality of polysilicon layers includes a polysilicon guard ring. In some embodiments, the polysilicon guard ring includes a rectangular shape with an interior extension. In some embodiments, forming the backside wiring structure includes forming a plurality of feedthrough vias extending in a first direction and separated in a second direction, and forming a plurality of backside vias extending in a third direction. In some embodiments, the analog cell is formed to extend between the first feedthrough via and the second feedthrough via.

[0110] In an example structure, an analog cell structure is provided. The analog cell structure includes a first feedthrough via and a second feedthrough via extending along a first direction and spaced a first distance apart in a second direction perpendicular to the first direction, and a CMOS structure disposed between the first feedthrough via and the second feedthrough via, the CMOS structure including a plurality of polysilicon layers, a PMOS active region, an NMOS active region, and a first metal diffusion pattern. The structure further includes a metal wiring layer and a plurality of vias. The first feedthrough via, the second feedthrough via, and a first via of the plurality of vias are configured to provide a backside connection to the CMOS structure. In some embodiments, the analog cell structure is disposed adjacent to a dummy cell including a guard ring structure.

[0111] The foregoing summary, as well as the following detailed description of the application, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the application, there is shown in the drawings embodiments which are presently preferred. It should be understood, however, that the application is not limited to the embodiments shown in the drawings, but is capable of carrying out the application in various ways.

Claims

1. An analog circuit device, characterized in that, include: Metal wiring layer, comprising multiple tracks; The simulation unit includes an n-type metal-oxide-semiconductor active region and a p-type metal-oxide-semiconductor active region, multiple polysilicon layers, and multiple metal diffusion layers, wherein the n-type metal-oxide-semiconductor active region, the p-type metal-oxide-semiconductor active region, the multiple polysilicon layers, and the multiple metal diffusion layers constitute a complementary metal-oxide-semiconductor structure. Multiple protection ring units surround the simulation unit; as well as The power rail structure is configured to provide back-side wiring to the analog unit by providing a connection between the metal wiring layer and the analog unit.

2. The analog circuit device according to claim 1, characterized in that, The power rail structure includes at least one feedthrough hole and at least one backside through hole.

3. The analog circuit device according to claim 2, characterized in that, The at least one feedthrough hole includes a first feedthrough hole and a second feedthrough hole extending in a first direction and separated in a second direction, and The simulation unit is disposed between the first feedthrough hole and the second feedthrough hole.

4. The analog circuit device according to claim 3, characterized in that, It also includes a first interruption region in the first feedthrough hole and a second interruption region in the second feedthrough hole. At least one of the plurality of polysilicon layers is attached to the first interruption region and the second interruption region.

5. The analog circuit device according to claim 1, characterized in that, The simulation unit includes one of multiple simulation units; The plurality of simulation units and the plurality of protection ring units are arranged into an array containing rows and columns; and The simulation units are arranged such that each of the plurality of simulation units is surrounded by the guard ring units of the plurality of guard ring units.

6. The analog circuit device according to claim 5, characterized in that, The plurality of protection ring units include an outer boundary of the protection ring unit, and the outer boundary of the protection ring unit includes: Four corner protection ring units; At least one horizontal protection ring unit; and At least one vertical protection ring unit, The first corner protection ring unit of the four corner protection ring units includes a first protection ring structure; The at least one vertical protection ring unit is adjacent to the first corner protection ring unit and includes a second protection ring structure; and The first protective ring structure is connected to the second protective ring structure.

7. The analog circuit device according to claim 6, characterized in that, It also includes a third protective ring structure within the second corner protective ring unit, wherein at least one vertical protective ring unit is disposed between the first corner protective ring unit and the second corner protective ring unit.

8. The analog circuit device according to claim 1, characterized in that, The n-type metal-oxide-semiconductor active region and the p-type metal-oxide-semiconductor active region of the simulation unit extend beyond the unit boundary.

9. The analog circuit device according to claim 1, characterized in that, The power rail structure includes a feedthrough via disposed between a first rail in the plurality of rails and a portion of the first metal diffusion layer of the plurality of metal diffusion layers, and a back-side via disposed between a second rail in the plurality of rails and one of the p-type metal oxide semiconductor active region and the n-type metal oxide semiconductor active region.

10. A simulation unit structure, characterized in that, include: The first feedthrough hole and the second feedthrough hole extend in a first direction and are spaced apart by a first distance in a second direction perpendicular to the first direction; A complementary metal-oxide-semiconductor structure is disposed between the first feedthrough and the second feedthrough, and includes multiple polysilicon layers, a p-type metal-oxide-semiconductor active region, an n-type metal-oxide-semiconductor active region, and a first metal diffusion pattern. Metal wiring layer; as well as Multiple through holes, The first feedthrough via, the second feedthrough via, and the first via of the plurality of vias are configured to provide a back-side connection to the complementary metal-oxide-semiconductor structure.

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