Solar cell
By setting different textured surfaces and impurity diffusion layers in the grid lines and non-grid line regions of the solar cell, a local emitter is formed, which solves the problem of insufficient front recombination loss in the prior art, improves cell efficiency and reduces cost.
Patent Information
- Application Number
- CN202422818602.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2026-01-20
- Estimated Expiration
- 2034-11-18
AI Technical Summary
Existing technologies have limited effectiveness in reducing front recombination losses while improving the conversion efficiency of solar cells.
Different textured surfaces are set in the grid line region and non-grid line region of the solar cell, and an impurity diffusion layer is set in the grid line region to form a local emitter. By forming a height difference in the non-grid line region, the overall doping concentration is reduced, the light trapping ability of the cell is improved and the front recombination current density is reduced.
It effectively reduces front-side recombination losses, improves battery opening voltage and conversion efficiency, and reduces battery costs without increasing existing SE equipment.
Smart Images
Figure CN223816372U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to battery technical field, especially a solar cell. BACKGROUND
[0002] As a kind of green new energy, solar energy has the advantage of inexhaustible, clean and environmental protection etc. Further reduce the manufacturing cost of solar cell and improve the conversion efficiency of solar cell is the prerequisite for ensuring the stable development of solar energy. In order to improve the conversion efficiency of solar cell, the prior art will usually adopt selective emitter (SelectiveEmitter, SE) structure design. Selective emitter technology is to carry out heavy doping in the grid line area of battery to reduce connection resistance, and to carry out light doping in the non-grid line area to reduce front surface recombination loss, so as to improve the conversion efficiency of solar cell. But this technology has limited effect on reducing front surface recombination loss. Therefore, how to improve the effect of reducing front surface recombination loss is a technical problem to be solved by the skilled in the art at present. SUMMARY
[0003] Therefore, the utility model discloses a solar cell for improving the effect of reducing front surface recombination loss.
[0004] To solve the above technical problems, the utility model provides a solar cell, comprising: substrate;The substrate includes grid line area and non-grid line area;
[0005] The front surface of the grid line area has first surface texture, and the front surface of the grid line area is provided with impurity diffusion layer, and the impurity diffusion layer and the front surface grid line are electrically connected;
[0006] The front surface of the non-grid line area has second surface texture, the non-grid line area is lower than the grid line area, and the front surface of the non-grid line area is not provided with impurity diffusion layer.
[0007] Optionally, the ratio of the non-grid line area to the grid line area is less than or equal to 14:1.
[0008] Optionally, the distance from the front surface of the grid line area to the front surface of the non-grid line area is 2 μm-3 μm, and the value including both ends.
[0009] Optionally, the front surface grid line includes front surface main grid line and front surface fine grid line;The front surface main grid line extends along the first direction;The front surface fine grid line continues along the second direction, and is electrically connected with the front surface main grid line.
[0010] Optionally, the surface of the impurity diffusion layer is sequentially provided with passivation layer and anti-reflection film along the thickness direction of the substrate;The front surface grid line penetrates the anti-reflection film and the passivation layer, and is electrically connected with the impurity diffusion layer.
[0011] Optionally, the passivation layer comprises an aluminum oxide layer.
[0012] The anti-reflective film comprises, in sequence along the thickness direction of the substrate, a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer.
[0013] Optionally, the back surface of the substrate is provided, in sequence along the thickness direction of the substrate, with a tunneling layer, a doped polysilicon layer and a back gate line.
[0014] Optionally, the doped polysilicon layer is provided, away from the surface of the substrate, with a passivation film; the back gate line penetrates through the passivation film and is electrically connected with the doped polysilicon layer.
[0015] Optionally, the passivation film comprises, in sequence along the thickness direction of the substrate, a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer.
[0016] Optionally, the back surface of the substrate has a third texturing.
[0017] It can be seen that the utility model discloses: substrate, the substrate includes the gate line area and the non gate line area, the front surface of the gate line area has the first texturing, and the front surface of the gate line area is provided with the impurity diffusion layer, and the impurity diffusion layer and the front surface gate line are electrically connected, the front surface of the non gate line area has the second texturing, and the non gate line area is lower than the gate line area, and the front surface of the non gate line area is not provided with the impurity diffusion layer, the utility model discloses through setting up the first texturing and the second texturing at the front surface of the gate line area and the front surface of the non gate line area respectively, can improve the light trapping capacity of battery, and at the same time, setting up the impurity diffusion layer at the front surface of the gate line area forms the local emitter, and the front surface of the non gate line area is not provided with the impurity diffusion layer, makes local emitter and the non gate line area form the height difference, on one hand, effectively reduced the doping concentration of the whole substrate, thereby can reduce the front surface recombination current density, improves the battery open pressure, and compared with the traditional selective doping solar cell, improves the effect of reducing the front surface recombination loss, on the other hand, this structure can improve the front surface recombination and improve the battery efficiency without increasing the existing SE machine, so also can reduce the battery cost. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or the prior art, below will to the drawing needed to use in the embodiment or prior art description simple introduction, obviously, the drawing in the following description only is the embodiment of the utility model, for the ordinary skilled person in the art comes, under the premise of not paying the creative labor, also can obtain other drawings according to the provided drawing.
[0019] Figure 1A structure diagram of a solar cell is provided in the utility model embodiment.
[0020] The reference signs are explained as follows:
[0021] 1-substrate; 11-first rough surface; 12-second rough surface; 2-impurity diffusion layer; 3-passivation layer; 4-anti-reflection film; 5-front grid line; 6-tunneling layer; 7-doped polysilicon layer; 8-passivation film; 9-back grid line. DETAILED DESCRIPTION
[0022] In order to make the purpose, technical scheme and advantages of the utility model embodiments clearer, the technical scheme in the utility model embodiments will be described clearly and completely in combination with the drawings in the utility model embodiments. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.
[0023] Please refer to Figure 1 , Figure 1 A structure diagram of a solar cell is provided in the utility model embodiment. The solar cell can include: a substrate 1; the substrate 1 includes a grid line area and a non-grid line area;
[0024] The front of the grid line area has a first rough surface 11, and the front of the grid line area is provided with an impurity diffusion layer 2, and the impurity diffusion layer 2 and the front grid line 5 are electrically connected.
[0025] The front of the non-grid line area has a second rough surface 12, and the non-grid line area is lower than the grid line area, and the non-grid line area is not provided with the impurity diffusion layer 2.
[0026] The embodiment is not limited to the specific type of the substrate 1, for example, the substrate 1 can be an N-type substrate; or a P-type substrate. The embodiment is not limited to the specific type of the substrate 1, and the substrate 1 can be but is not limited to a single crystal silicon wafer. It should be noted that silicon is a common material in the prior art, and the embodiment is not limited to the internal components of the substrate 1, but directly uses a single crystal silicon wafer made of the existing material. The embodiment is not limited to the specific type of the single crystal silicon wafer, for example, the resistivity of the single crystal silicon wafer can be 0.6Ω·cm -1.4Ω·cm, and the values at both ends are included; the thickness of the single crystal silicon wafer can be 150μm±20μm.
[0027] It should be noted that the impurity diffusion layer 2 in the embodiment is formed by diffusing impurities into the first textured surface 11 after forming the first textured surface 11 on the front surface of the substrate 1 (for details, refer to the prior art), that is, the impurity diffusion layer 2 is a substrate 1 doped with impurities. It should be noted that the substrate 1 doped with impurities is a common material in the prior art, and the embodiment does not limit the internal components of the impurity diffusion layer 2, but directly uses the substrate 1 doped with impurities made of existing materials.
[0028] It should be noted that during the diffusion of impurities into the substrate 1, additional products will be formed on the surface of the impurity diffusion layer 2. For example, when the impurity is boron, a layer of borosilicate glass (BSG) will be formed on the surface of the impurity diffusion layer 2. The second textured surface 12 of the non-grid line area in the embodiment can be formed by the following method: after forming the first textured surface 11, the boron diffusion layer and the BSG layer on the entire front surface of the substrate 1, the BSG layer in the non-grid line area is modified by laser patterning using a laser device, and after modification, the second texturing is performed. The BSG layer and the impurity diffusion layer 2 in the above laser area are removed, and only the local emitter corresponding to the grid line area is left, and the non-grid line area forms a recessed structure. This method does not need to increase the existing SE machine, and can reduce the cost of the battery.
[0029] The embodiment does not limit the specific type of the impurity diffusion layer 2, and the specific type of the impurity diffusion layer 2 can be determined according to the specific type of the substrate 1. For example, when the substrate 1 is an N-type substrate, the impurity diffusion layer 2 can be a P-type impurity diffusion layer, and when the substrate 1 is a P-type substrate, the impurity diffusion layer 2 can be an N-type impurity diffusion layer. The embodiment does not limit the specific type of the impurity, and the specific type of the impurity can be determined according to the specific type of the impurity diffusion layer 2. For example, when the impurity diffusion layer 2 is a P-type impurity diffusion layer, the impurity can be boron; and when the impurity diffusion layer 2 is an N-type impurity diffusion layer, the impurity can be phosphorus. It should be noted that boron and phosphorus are common impurity materials in the prior art, and the embodiment does not limit the internal components of the impurity diffusion layer 2, but directly uses the substrate 1 doped with boron and the substrate 1 doped with phosphorus made of existing materials.
[0030] The embodiment does not limit the specific size of the non-grid line area and the grid line area, for example, the ratio of the non-grid line area to the grid line area can be less than or equal to 14:1. The size of the grid line area is greater than that of the grid line area of the conventional selectively doped solar cell (including a lightly doped non-grid line area and a heavily doped grid line area).
[0031] The embodiment does not limit the specific height difference between the non-grid line area and the grid line area, for example, the distance from the front surface of the grid line area to the front surface of the non-grid line area can be 2-3 μm, and the values at both ends are included.
[0032] The embodiment is not limited to the specific structure of the front side grid line 5. In order to improve the battery efficiency, the front side grid line 5 in the embodiment can include a front side main grid line and a front side fine grid line. The front side main grid line extends along a first direction. The front side fine grid line extends along a second direction and is electrically connected with the front side main grid line. The first direction can be, but is not limited to, parallel to the extension direction of the grid line area. The second direction can be, but is not limited to, perpendicular to the first direction.
[0033] Further, the surface of the impurity diffusion layer 2 in the embodiment can be sequentially provided with a passivation layer 3 and an anti-reflection film 4 along the thickness direction of the substrate 1. The front side grid line 5 penetrates the anti-reflection film 4 and the passivation layer 3 and is electrically connected with the impurity diffusion layer 2. It should be noted that the passivation layer 3 provided on the front side of the substrate 1 in the embodiment can improve the passivation effect of the front side of the substrate 1. The anti-reflection film 4 provided on the front side of the substrate 1 can reduce the reflection of the front side of the substrate 1, thereby improving the battery efficiency.
[0034] The embodiment is not limited to the specific type of the passivation layer 3, as long as it can provide a passivation effect. For example, the passivation layer 3 can include an aluminum oxide layer. It should be noted that aluminum oxide (Al2O3) is a common material in the prior art. The embodiment is not limited to the internal components of the passivation layer 3, but directly uses a film layer made of an existing material.
[0035] The embodiment is not limited to the specific type of the anti-reflection film 4, as long as it can reduce the reflection of the front side of the substrate 1. For example, the anti-reflection film 4 can include a silicon nitride (SiN x ) layer, a silicon oxynitride (SiON x ) layer and a silicon oxide (SiO x ) layer sequentially arranged along the thickness direction of the substrate 1. It should be noted that silicon nitride (SiN x ), silicon oxynitride (SiON x ) and silicon oxide (SiO x ) are common materials in the prior art. The embodiment is not limited to the internal components of the anti-reflection film 4, but directly uses a film layer made of an existing material.
[0036] The embodiment is not limited to the specific structure of the back side of the substrate 1. The specific structure of the back side of the substrate 1 can be determined according to the specific type of the solar cell. For example, when the solar cell is a TOPCon battery, the back side of the substrate 1 can be sequentially provided with a tunneling layer 6, a doped polysilicon layer 7 and a back side grid line 9 along the thickness direction of the substrate 1.
[0037] The embodiment is not limited to the specific type of the tunneling layer 6, as long as it can form chemical passivation on the back of the substrate 1. For example, the tunneling layer 6 is a tunneling oxide layer. It should be noted that the oxide is a common material in the prior art, and the embodiment is not limited to the internal components of the tunneling layer 6, but directly uses the film layer made of the existing material.
[0038] It should be noted that the doped polysilicon layer 7 in the embodiment is formed by impurity diffusion into the polysilicon layer (for details, refer to the prior art), that is, the doped polysilicon layer 7 is a polysilicon layer doped with impurities. It should be noted that the polysilicon layer doped with impurities is a common material in the prior art, and the embodiment is not limited to the internal components of the doped polysilicon layer 7, but directly uses the polysilicon layer doped with impurities made of the existing material.
[0039] The embodiment is not limited to the specific type of the doped polysilicon layer 7, and the specific type of the doped polysilicon layer 7 can be determined according to the specific type of the substrate 1. For example, when the substrate 1 is an N-type substrate, the doped polysilicon layer 7 can be an N-type doped polysilicon layer, and when the substrate 1 is a P-type substrate, the doped polysilicon layer 7 can be a P-type doped polysilicon layer. The embodiment is not limited to the specific type of the impurity, and the specific type of the impurity can be determined according to the specific type of the doped polysilicon layer 7. For example, when the doped polysilicon layer 7 is an N-type doped polysilicon layer, the impurity can be phosphorus; and when the doped polysilicon layer 7 is a P-type doped polysilicon layer, the impurity can be boron. It should be noted that boron and phosphorus are common impurity materials in the prior art, and the embodiment is not limited to the internal components of the doped polysilicon layer 7, but directly uses the polysilicon layer doped with phosphorus and the polysilicon layer doped with boron made of the existing material.
[0040] The embodiment is not limited to the specific structure of the back gate line 9. In order to improve the cell efficiency, the back gate line 9 in the embodiment can include a back main gate line and a back fine gate line. The back main gate line extends along a first direction. The back fine gate line extends along a second direction and is electrically connected with the back main gate line. The first direction can be, but is not limited to, parallel to the extension direction of the area of the back gate line 9. The second direction can be, but is not limited to, perpendicular to the first direction.
[0041] Further, the surface of the doped polysilicon layer 7 away from the substrate 1 in the embodiment can be provided with a passivation film 8. The back gate line 9 penetrates the passivation film 8 and is electrically connected with the doped polysilicon layer 7. It should be noted that the embodiment can improve the passivation effect on the back of the substrate 1 by providing the passivation film 8 on the back of the substrate 1.
[0042] The embodiment is not limited to the specific type of the passivation film 8, as long as it can provide passivation effect. For example, the passivation film 8 can include a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer arranged in the thickness direction of the substrate 1 in sequence. It should be noted that the silicon nitride (SiNx silicon nitride (SiN x ) and silicon oxide (SiO x ) are common materials in the prior art, and the present embodiment is not limited to the internal components of the passivation film 8, but directly uses a film layer made of existing materials.
[0043] Further, in order to improve the light trapping capability of the battery, the third texture is provided on the back surface of the substrate 1.
[0044] Based on the above embodiment, by respectively providing the first texture 11 and the second texture 12 on the front surface of the gate line area and the front surface of the non-gate line area, the light trapping capability of the battery can be improved; at the same time, the impurity diffusion layer 2 is provided on the front surface of the gate line area to form a local emitter, and the impurity diffusion layer 2 is not provided on the front surface of the non-gate line area, so that the local emitter and the non-gate line area form a height difference, which on the one hand effectively reduces the overall doping concentration of the substrate 1, so as to reduce the front surface recombination current density and improve the open voltage of the battery, compared with the conventional selectively doped solar cell, the effect of reducing the front surface recombination loss is improved; on the other hand, the structure can improve the front surface recombination without increasing the existing SE machine, thereby improving the battery efficiency and reducing the battery cost.
[0045] In order to make the utility model more convenient for understanding, one of the preparation processes of the above-mentioned solar cell is also provided below. Specifically, it includes the following steps:
[0046] Step 1: The substrate 1 is selected as an N-type monocrystalline silicon wafer, the resistivity of the N-type monocrystalline silicon wafer is 0.6Ω·cm -1.4Ω·cm, and the thickness is 150μm±20μm; after pre-cleaning the surface of the N-type monocrystalline silicon wafer, double-sided texturing is performed to form a texture on the front surface and the back surface of the N-type monocrystalline silicon wafer;
[0047] Step 2: Take the N-type monocrystalline silicon wafer after texturing, and perform boron diffusion on the N-type monocrystalline silicon wafer (the boron diffusion process specifically includes steps such as deposition, diffusion, advancement and oxidation), to form an impurity diffusion layer 2 (this embodiment is a boron diffusion layer) and a BSG layer on the front surface of the texture of the N-type monocrystalline silicon wafer, so as to form a boron emitter;
[0048] Step 3: The BSG layer in the non-gate line area is modified by laser patterning by using a laser equipment, and the doped area is divided into a separated long strip matrix structure; the proportion of the laser modification area to the non-modification area is less than or equal to 14:1;
[0049] Process 4: Etching the laser modified region on the front surface of the N-type monocrystalline silicon wafer using NaOH and additive 1, removing the BSG layer of the laser opening region on the front surface of the N-type monocrystalline silicon wafer, and simultaneously re-texturing the region, the etching depth of the front surface of the N-type monocrystalline silicon wafer is about 2-3 μm; re-texturing the opening region to realize local emitter;
[0050] Process 5: Growing an oxidation mask on the front surface of the N-type monocrystalline silicon wafer using a PECVD (Plasma Enhanced Chemical Vapor Deposition) machine;
[0051] Process 6: Polishing the back surface of the N-type monocrystalline silicon wafer using a tank-type device with NaOH and additive 2;
[0052] Process 7: Depositing a tunnel layer 6 and an amorphous silicon layer on the back surface of the N-type monocrystalline silicon wafer at 580-620 degrees Celsius using an LPCVD (Low Pressure Chemical Vapor Deposition) device;
[0053] Process 8: Phosphorus doping on the back surface of the N-type monocrystalline silicon wafer at 800-920 degrees Celsius using a phosphorus diffusion device to form a doped polysilicon layer 7 and grow a 15-35 nm thick phosphorosilicate glass (PSG) layer;
[0054] Process 9: Removing the PSG layer and oxidation mask on the front surface of the N-type monocrystalline silicon wafer using a chain-type device with HF acid, and subsequently removing the amorphous silicon layer, BSG layer on the front surface of the N-type monocrystalline silicon wafer, and the PSG layer on the back surface of the N-type monocrystalline silicon wafer using a tank-type device;
[0055] Process 10: Depositing an Al2O3 passivation layer 3 on the front surface of the N-type monocrystalline silicon wafer using a plate-type or tube-type ALD (Atomic Layer Deposition) or PECVD device with TMA (trimethylaluminum) and an oxidizing agent;
[0056] Process 11: Depositing SiN x / SiON x / SiO x / SiO x / SiON x / SiO x passivation film 8 on the back surface of the N-type monocrystalline silicon wafer using a PECVD device with SiH4 / NH3 / N2O;
[0057] Process 12: printing main grid lines and fine grid lines on the front surface of the N-type monocrystalline silicon wafer by screen printing, and printing main grid lines and fine grid lines on the back surface of the N-type monocrystalline silicon wafer by screen printing to coincide with the previous patterned emitter;
[0058] Process 13: H passivation by using a photo injection furnace;
[0059] Process 14: processing the front surface of the cell wafer by using LECO (Low Energy Consumption) laser processing;
[0060] Process 15: I-V curve testing by using a testing machine.
[0061] The solar cell provided by the utility model is described in detail above, and for the general technical personnel in the field, the specific implementation mode and application range will be changed according to the thought of the utility model embodiment, and in conclusion, the content of the specification should not be understood as the limitation of the utility model.
Claims
1. A solar cell, characterized by, The application relates to a substrate, which comprises a gate line area and a non-gate line area. The front surface of the gate line area is provided with a first rough surface and an impurity diffusion layer, and the impurity diffusion layer and the front surface gate line are electrically connected. The front surface of the non-gate line area is provided with a second rough surface, the non-gate line area is lower than the gate line area, and the front surface of the non-gate line area is not provided with an impurity diffusion layer. The ratio of the non-gate line area to the gate line area is less than or equal to 14:
1.
2. The solar cell according to claim 1, characterized in that, The distance from the front surface of the gate line area to the front surface of the non-gate line area is 2-3 mu m, and the value at both ends is included.
3. The solar cell according to claim 1, characterized in that, The front surface gate line comprises a front surface main gate line and a front surface fine gate line; the front surface main gate line extends along a first direction; and the front surface fine gate line extends along a second direction and is electrically connected with the front surface main gate line.
4. The solar cell of claim 1, wherein The surface of the impurity diffusion layer is sequentially provided with a passivation layer and an anti-reflection film along the thickness direction of the substrate; the front surface gate line penetrates the anti-reflection film and the passivation layer and is electrically connected with the impurity diffusion layer.
5. The solar cell of claim 1, wherein The passivation layer comprises an aluminum oxide layer.
6. The solar cell according to claim 5, characterized in that, The anti-reflection film comprises a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer which are sequentially arranged along the thickness direction of the substrate. The back surface of the substrate is sequentially provided with a tunneling layer, a doped polysilicon layer and a back surface gate line along the thickness direction of the substrate.
7. The solar cell of claim 1, wherein The surface of the doped polysilicon layer away from the substrate is provided with a passivation film; the back surface gate line penetrates the passivation film and is electrically connected with the doped polysilicon layer.
8. The solar cell of claim 7, wherein, The passivation film comprises a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer which are sequentially arranged along the thickness direction of the substrate.
9. The solar cell of claim 8, wherein, The back surface of the substrate has a third rough surface.
10. The solar cell of claim 1, wherein,