Imaging device

Abstract

This prevents a decrease in the saturation electron count. [Solution] The device comprises a photoelectric conversion unit and electrodes on at least a portion of the surface surrounding the photoelectric conversion unit through which either holes or electrons flow. The electrodes include an insulating film and an impurity diffusion region in which a predetermined impurity is diffused. The insulating film has a contact on the side wall facing the photoelectric conversion unit that connects the photoelectric conversion unit and the impurity diffusion region, and the insulating film has a connecting region that connects the contact and the impurity diffusion region. This technology can be applied, for example, to imaging devices, and is applicable to imaging devices having miniaturized pixels.

Description

Technical Field

[0001] The present technology relates to an imaging device, for example, an imaging device that suppresses the generation of random noise and can further improve imaging characteristics.

Background Art

[0002] In recent years, imaging devices having front full trench isolation (FFTI) have been used. In an imaging device having FFTI, pixels are separated by an insulator, and each pixel is electrically separated. Therefore, each separated pixel needs to include a contact electrode for setting the semiconductor substrate to, for example, a ground potential. In order to reduce the area of the contact electrode in plan view, an imaging device has been proposed in which a part of the FFTI is used as an active region to form a contact electrode (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] As the imaging device is miniaturized, the areas for arranging transistors and contact electrodes become smaller. For example, the area of an amplification transistor becomes smaller, and there is a possibility that random noise may occur. It is desired to be able to further miniaturize without degrading the characteristics of the imaging device.

[0005] The present technology has been made in view of such a situation, and enables further miniaturization without degrading the characteristics of the imaging device.

Means for Solving the Problems

[0006] One aspect of this technology is a first imaging device comprising a photoelectric conversion unit and an electrode on at least a portion of the surface surrounding the photoelectric conversion unit through which either holes or electrons flow, wherein the electrode includes an insulating film and an impurity diffusion region in which a predetermined impurity is diffused, and the insulating film is provided with a contact on the side wall of the insulating film on the photoelectric conversion unit side for connecting the photoelectric conversion unit and the impurity diffusion region, and the insulating film is provided with a connecting region for connecting the contact and the impurity diffusion region.

[0007] A second imaging device, representing one aspect of this technology, comprises a first substrate including a photoelectric conversion unit, a second substrate laminated on the first substrate and provided with pixel transistors for processing signals from the photoelectric conversion unit, and an electrode connected to a supply source that supplies a predetermined potential to the pixel transistors, the electrode being located in the layer on the second substrate where the pixel transistors are arranged, wherein the electrode is an electrode through which either holes or electrons flow, and includes an insulating film and an impurity diffusion region in which a predetermined impurity is diffused, the insulating film having a contact on the side wall on the photoelectric conversion unit side connecting the photoelectric conversion unit and the impurity diffusion region, and the insulating film having a connecting region connecting the contact and the impurity diffusion region.

[0008] In a first imaging device representing one aspect of this technology, a photoelectric conversion unit and an electrode through which either holes or electrons flow are provided on at least a portion of the surface surrounding the photoelectric conversion unit, the electrode includes an insulating film and an impurity diffusion region in which a predetermined impurity is diffused, a contact is provided on the side wall of the insulating film on the photoelectric conversion unit side for connecting the photoelectric conversion unit and the impurity diffusion region, and the insulating film is provided with a connection region for connecting the contact and the impurity diffusion region.

[0009] In a second imaging device, which is one aspect of this technology, the device comprises a first substrate including a photoelectric conversion unit, a second substrate laminated on the first substrate and provided with a pixel transistor that processes signals from the photoelectric conversion unit, and an electrode connected to a supply source that supplies a predetermined potential to the pixel transistor, the electrode being located on the layer of the second substrate on which the pixel transistor is arranged, the electrode being an electrode through which either holes or electrons flow, and comprising an insulating film and an impurity diffusion region in which a predetermined impurity is diffused, the side wall of the insulating film on the photoelectric conversion unit side is provided with a contact connecting the photoelectric conversion unit and the impurity diffusion region, and the insulating film is provided with a connecting region connecting the contact and the impurity diffusion region.

[0010] The imaging device may be a standalone device or an internal block that makes up a single device. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows an example of the configuration of an imaging device. [Figure 2] This figure shows an example of the configuration of the pixel array section. [Figure 3] This figure shows the configuration of one embodiment of an imaging device to which this technology is applied. [Figure 4] This figure shows an example of the pixel configuration in the first embodiment. [Figure 5] This figure shows an example of the pixel configuration in the second embodiment. [Figure 6] This is a diagram illustrating the manufacturing process of effective pixels. [Figure 7] This is a diagram illustrating the manufacturing process of effective pixels. [Figure 8] This figure shows an example of the pixel configuration in the third embodiment. [Figure 9] This figure shows an example of the pixel configuration in the third embodiment. [Figure 10] This is a diagram illustrating the configuration for connecting to the power source. [Figure 11] This is a diagram for explaining the configuration regarding the connection to a supply source. [Figure 12] This is a diagram showing an example of the arrangement of transistors. [Figure 13] This is a diagram showing an example of the arrangement of transistors. [Figure 14] This is a diagram showing an example of the pixel configuration in the fourth embodiment. [Figure 15] This is a diagram showing an example of the pixel configuration in the fifth embodiment. [Figure 16] This is a diagram showing an example of the pixel configuration in the sixth embodiment. [Figure 17] This is a diagram showing an example of the pixel configuration in the seventh embodiment. [Figure 18] This is a diagram showing an example of the pixel configuration in the eighth embodiment. [Figure 19] This is a diagram showing an example of the pixel configuration in the eighth embodiment. [Figure 20] This is a diagram showing an example of the pixel configuration in the ninth embodiment. [Figure 21] This is a diagram showing an example of the pixel configuration in the tenth embodiment. [Figure 22] This is a diagram showing an example of the pixel configuration in the tenth embodiment. [Figure 23] This is a diagram showing an example of the pixel configuration in the eleventh embodiment. [Figure 24] This is a diagram showing an example of the pixel configuration in the eleventh embodiment. [Figure 25] This is a diagram showing an example of the pixel configuration in the twelfth embodiment. [Figure 26] This is a diagram showing an example of the pixel configuration in the twelfth embodiment. [Figure 27] This is a diagram showing an example of the pixel configuration in the thirteenth embodiment. [Figure 28] This is a diagram showing an example of the pixel configuration in the fourteenth embodiment. [Figure 29] This is a diagram showing an example of the pixel configuration in the fifteenth embodiment. [Figure 30]This figure shows an example of the pixel configuration in the 16th embodiment. [Figure 31] This figure shows an example of the pixel configuration in the 16th embodiment. [Figure 32] This figure shows an example of the pixel configuration in the 17th embodiment. [Figure 33] This figure shows an example of the pixel configuration in the 17th embodiment. [Figure 34] This figure shows an example of the pixel configuration in the 18th embodiment. [Figure 35] This figure shows an example of the pixel configuration in the 19th embodiment. [Figure 36] This figure shows an example of the pixel configuration in the 20th embodiment. [Figure 37] This figure shows an example of the pixel configuration in the 21st embodiment. [Figure 38] This figure shows an example of the pixel configuration in the 22nd embodiment. [Figure 39] This figure shows an example of the pixel configuration in the 23rd embodiment. [Figure 40] This figure shows an example of the pixel configuration in the 24th embodiment. [Figure 41] This figure shows an example of the pixel configuration in the 25th embodiment. [Figure 42] This figure shows an example of a planar configuration of pixels. [Figure 43] This is a diagram showing an example of the configuration of an electronic device. [Figure 44] This figure shows an example of a schematic configuration of an endoscopic surgical system. [Figure 45] This block diagram shows an example of the functional configuration of a camera head and CCU. [Figure 46] This block diagram shows an example of a schematic configuration of a vehicle control system. [Figure 47] This is an explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit. [Modes for carrying out the invention]

[0012] The following describes the embodiments for implementing this technology.

[0013] <Example of a schematic configuration of an imaging device> Figure 1 shows a schematic configuration of an imaging device including an image sensor according to this disclosure.

[0014] The imaging device 1 shown in Figure 1 is configured with a pixel array section 3 in which pixels 2 are arranged in a two-dimensional array on a semiconductor substrate 12 using silicon (Si) as the semiconductor, and a peripheral circuit section surrounding it. The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0015] Pixel 2 is configured to have a photodiode as a photoelectric conversion element and multiple pixel transistors. The multiple pixel transistors consist of, for example, four MOS transistors: a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor.

[0016] Pixel 2 can also be a shared pixel structure. This shared pixel structure consists of multiple photodiodes, multiple transfer transistors, one shared floating diffusion region, and one shared pixel transistor from each of the other pixels. In other words, in a shared pixel, the photodiodes and transfer transistors that make up multiple unit pixels share one pixel transistor from each of the other pixels.

[0017] The control circuit 8 receives the input clock and data that commands the operating mode, and outputs data such as internal information of the imaging device 1. Specifically, the control circuit 8 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc.

[0018] The vertical drive circuit 4 is composed of, for example, a shift register, and selects a pixel drive wiring 10, supplies pulses to the selected pixel drive wiring 10 to drive the pixel 2, and drives the pixel 2 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 2 of the pixel array 3 row by row in the vertical direction, and supplies a pixel signal based on the signal charge generated in the photoelectric conversion unit of each pixel 2 according to the amount of light received to the column signal processing circuit 5 through the vertical signal line 9.

[0019] The column signal processing circuit 5 is located for each column of pixels 2 and performs signal processing such as noise reduction on the signals output from each row of pixels 2 for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD conversion to remove pixel-specific fixed pattern noise.

[0020] The horizontal drive circuit 6 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0021] The output circuit 7 processes the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11 and outputs them. The output circuit 7 may, for example, only perform buffering, or it may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 13 exchanges signals with the outside.

[0022] The imaging device 1 configured as described above is a CMOS image sensor called a column AD type, in which a column signal processing circuit 5 that performs CDS processing and AD conversion processing is arranged for each pixel row.

[0023] Furthermore, the imaging device 1 is a back-illuminated MOS type imaging device in which light is incident from the back side opposite to the front side of the semiconductor substrate 12 on which the pixel transistors are formed.

[0024] <Example of the configuration of the pixel array section 3> Figure 2 shows an example of the configuration of the pixel array section 3 of the imaging device 1.

[0025] The pixel array section 3 shown in Figure 2 includes an effective pixel area 31 where effective pixels are arranged and a light-shielding pixel area 32 where OPB (optical black) pixels are arranged. The light-shielding pixel area 32, located at the top of the pixel array section 3 in the figure, is a light-shielding area that is shielded to prevent light from entering. The effective pixel area 31 is an open area that is not shielded to light.

[0026] The effective pixel region 31 located within the aperture region contains effective pixels (hereinafter referred to as effective pixels 31 as appropriate) from which pixel signals are read out when generating an image.

[0027] The light-shielding pixel area 32, located within the upper light-shielding area, contains light-shielding pixels (hereinafter referred to as light-shielding pixels 32 as appropriate) used for reading out the black level signal, which is a pixel signal indicating the black level of the image.

[0028] Note that this technology can be applied to arrangements other than those shown in Figure 2 for the pixel array section 3. For example, although the example shown illustrates that the light-shielding pixel area 32 is formed on one side of the effective pixel 31, it can also be provided on two to four sides. Alternatively, a pad area can be provided, each containing multiple pads with openings for exposing bonding pads.

[0029] <First Embodiment> Figure 3 shows an example of a cross-sectional configuration of effective pixels 31 arranged in a matrix within the effective pixel region 31. Figure 4A shows an example of a planar configuration of effective pixels 31 along the line segment A-A' in Figure 3, and Figure 4B shows an example of a planar configuration of effective pixels 31 along the line segment B-B' in Figure 3.

[0030] The effective pixels 31 described below will be explained using the back-illuminated type as an example, but this technology can also be applied to front-illuminated types.

[0031] The effective pixel 31 shown in Figure 3 has a photodiode (PD) 71, which is a photoelectric conversion element (photoelectric conversion unit) for each pixel, formed inside the Si substrate 70 (corresponding to the semiconductor substrate 12 in Figure 1). The PD 71 has an n-type polarity, and the n-type impurity region (hereinafter appropriately referred to as the n-type impurity diffusion region 71a) is contained within the p-type impurity region (hereinafter appropriately referred to as the p-type impurity diffusion region 71b), and the electrons generated by photoelectric conversion are read out.

[0032] An insulating sealing film 72 is formed on the upper part of PD71 in the diagram. Here, we will explain using the case where an insulating sealing film 72 is formed as an example, but it is also possible to have a configuration in which an anti-reflective film or a fixed charge film is formed (laminated). For example, a laminated structure may be formed in which a fixed charge film is formed on the upper layer of PD71, an anti-reflective film is formed on the upper layer of the fixed charge film, and an insulating sealing film 72 is formed on the upper layer of the anti-reflective film.

[0033] When a fixed charge film is constructed in a stacked configuration, the material of the fixed charge film can be an insulating material containing at least one of the following: Si (silicon), N (nitrogen), Al (aluminum), Hf (hafnium), Ta (tantalum), Ti (titanium), O (oxygen), Ca (calcium), Mg (magnesium), Li (lithium), Sr (strontium), Sc (scandium), Ba (barium), Nb (niobium), W (tungsten), Mo (molybdenum), Zr (zirconium), La (lanthanum), Gd (gadolinium), and Y (yttrium). Alternatively, the fixed charge film may have a stacked configuration of films containing these materials.

[0034] The material for the fixed charge film may be, for example, a silicon nitride film, an aluminum oxide film, a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, a silicon aluminum nitride film, magnesium oxide, a silicon aluminum oxide film, a hafnium oxide film, a hafnium aluminum oxide film, a tantalum oxide film, a titanium oxide film, a scandium oxide film, a zirconium oxide film, a gadolinium oxide film, a lanthanum oxide film or a yttrium oxide film, a niobium pentoxide film, a calcium oxide film, a lithium oxide film, a strontium oxide film, a barium oxide film, a tungsten oxide film or a molybdenum oxide film, and may also be a laminated structure of these insulating films.

[0035] When an anti-reflective coating is laminated, the anti-reflective coating material can be an insulating material containing at least one of the following: Si (silicon), N (nitrogen), Al (aluminum), Hf (hafnium), Ta (tantalum), Ti (titanium), O (oxygen), Mg (magnesium), Sc (scandium), Zr (zirconium), La (lanthanum), Gd (gadolinium), and Y (yttrium). Alternatively, the anti-reflective coating may have a laminated structure containing these materials.

[0036] For example, the anti-reflective coating may be composed of silicon nitride film, aluminum oxide film, silicon oxide film, silicon oxynitride film, aluminum oxynitride film, aluminum silicon nitride film, magnesium oxide, magnesium fluoride, aluminum silicon oxide film, hafnium oxide film, aluminum hafnium oxide film, tantalum oxide film, titanium oxide film, scandium oxide film, zirconium oxide film, gadolinium oxide film, lanthanum oxide film, or yttrium oxide, and may also be a laminated structure of these insulating films.

[0037] A color filter (CF) 73 is provided in the upper layer of the insulating sealing film 72 in the figure. The color filter 73 is a filter that transmits a specific color, for example, a filter that transmits light of colors such as R (red), G (green), and B (blue). A narrow-band filter such as a plasmon filter may be used as the color filter 73. A light-shielding wall (not shown) may be provided in the portion of the color filter 73 corresponding to the pixels.

[0038] The light-shielding wall is provided, for example, in the area where the color of the color filter 73 changes, in other words, between the effective pixels 31, and has the function of preventing light leakage to adjacent pixels and also functions as a waveguide to guide incident light towards the PD 71. The light-shielding wall is formed using a metal such as Al (aluminum), W (tungsten), or Cu (copper). Alternatively, it may be formed using a material with a lower refractive index than the material that makes up the color filter 73.

[0039] In the upper layer of the color filter 73, an OCL (on-chip lens) 74 is formed to focus the incident light onto the PD 71. Although not shown in Figure 3, a configuration in which a cover glass or a transparent plate made of resin is bonded to the OCL 76 is also possible.

[0040] On the side of PD71 opposite to the light incidence side (the bottom side in the figure, which is the surface side), a wiring layer 75 is formed. Multiple transistors are formed on this wiring layer 75. Figure 3 shows an example in which a transfer transistor 76 and a reset transistor 77 are formed.

[0041] Referring to Figure 4A, transfer transistors 76-1 to 76-4, reset transistor 77, amplification transistors 78-1, 78-2, and selection transistor 79 are arranged in a 2x2 array of four pixels. The configuration shown in Figure 4A shows four 2x2 effective pixels 31 of the effective pixels 31 arranged in the pixel array section 3, and represents the configuration when these four effective pixels 31 share an FD (Floating Diffusion) 91.

[0042] In Figure 4A, effective pixel 31-1 is located in the upper left, effective pixel 31-2 in the lower left, effective pixel 31-3 in the upper right, and effective pixel 31-4 in the lower right. FD91 is located in the center between effective pixels 31-1 to 31-4, and transfer transistors 76-1 to 76-4 are configured to be in contact with the diffusion region 92 connected to FD91.

[0043] An amplification transistor 78-1 is located in effective pixel 31-1, a reset transistor 77 is located in effective pixel 31-2, an amplification transistor 78-2 is located in effective pixel 31-3, and a selection transistor 79 is located in effective pixel 31-4. Note that this is just one example of transistor placement and is not limited to this example.

[0044] An element separation section 81 is provided so as to surround the effective pixels 31-1 to 31-4. An element separation section 81 is also provided in the region between the effective pixels 31-1 to 31-4, excluding the region where the FD91 is provided.

[0045] The cross-sectional configuration example of the effective pixel 31 shown in Figure 3 is an example of the cross-sectional configuration of effective pixel 31-1 and effective pixel 31-2, and an element isolation section 81 is provided between the gate electrode of transfer transistor 76-1 and the gate electrode of transfer transistor 76-2. The gate electrode of the transfer transistor 76 shown in Figure 3 is a vertical gate electrode that extends to the region of PD71, but this technology can also be applied to gate electrodes of other shapes.

[0046] Trenches 82 are formed between the effective pixels 31. These trenches 82 are formed between adjacent effective pixels 31, penetrating the Si substrate 70 in the depth direction (vertical direction in the figure, from the front surface to the back surface). Here, we will continue the explanation assuming that the trenches penetrate the Si substrate 70 and extend to the element isolation section 81, but as will be described later, they may also be trenches that do not penetrate all the way through.

[0047] A sidewall film 83 made of silica is formed on the inner wall of the trench 82, and an impurity region 84 is formed inside it by the injection of a predetermined impurity. The sidewall film 83 is made of an insulator and functions as an insulating film. The impurity region 84 is a region where impurities that form an n-type region are diffused when the polarity of PD71 is n-type.

[0048] The impurity region 84 is a region filled within the trench 82, which is polysilicon into which impurities such as B (boron), Al (aluminum), Ga (gallium), and In (indium) have been implanted. The impurity region 84 is connected to the p-type impurity diffusion region 71b via a pinhole 85 and a contact 86. In the following explanation, we will continue the explanation using the case where the impurity is B (boron) as an example.

[0049] The pinhole 85 is a region where a part of the impurity region 84 penetrates the sidewall film 83, and a contact 86 is formed at its tip. The contact 86 is a region formed on the sidewall of the sidewall film 83, in other words, on the sidewall of the trench 82. The contact 86 can also be described as a region in the p-type impurity diffusion region 71b where a part of the impurity region 84 is formed via the pinhole 85. Furthermore, the pinhole 85 is a connecting region that connects the impurity region 84 and the contact 86, and can also be described as a connecting region provided within the sidewall film 83.

[0050] The impurities contained in the impurity region 84 are also present in the pinholes 85 and contacts 86. If the impurity in the impurity region 84 is B (boron), then boron is also present in the pinholes 85 and contacts 86. Although the manufacturing process will be described later, during manufacturing, a sidewall film 83 made of silica, for example, is deposited on the inner wall of the trench 82. After deposition, an impurity region 84 made of boron-doped polysilicon, for example, is deposited, and the pinholes 85 and contacts 86 are formed by performing annealing at a predetermined temperature for a predetermined time.

[0051] The density of the pinholes 85 and contacts 86 formed differs depending on the concentration of the impurity (e.g., boron) doped into the impurity region 84, the thickness of the sidewall film 83, the temperature during annealing, and the annealing time. In other words, the density of the pinholes 85 and contacts 86 formed in the sidewall film 83 can be adjusted to a desired density (or a density close to a desired density) by adjusting the concentration of the impurity (e.g., boron) doped into the impurity region 84, the thickness of the sidewall film 83, the temperature during annealing, and the annealing time.

[0052] The positions where the pinholes 85 and contacts 86 are formed are random and not regularly arranged with predetermined intervals. Therefore, there may be areas where, for example, pinholes 85 or contacts 86 are located close together, or areas where pinholes 85 or contacts 86 are located far apart.

[0053] In areas where pinholes 85 or contacts 86 are located in close proximity, there may be places where contacts 86 formed at the ends of multiple pinholes 85 come into contact, forming a single contact 86. The thickness of the pinholes 85 themselves may not be uniform, but may vary.

[0054] The pinhole 85 and contact 86 are regions doped with the same impurities as those contained in the impurity region 84, such as boron, at a high concentration, thus becoming regions that allow only holes to pass through and not electrons. Hereafter, the sidewall film 83, impurity region 84, pinhole 85, and contact 86 will be referred to as the charge polarity selective electrode 87 as appropriate. The charge polarity selective electrode 87 can function as an electrode through which only hole current selectively flows.

[0055] By providing a charge polarity-selective electrode 87, the decrease in the saturated electron quantity can be suppressed. Let me explain this further. If a ground electrode is not provided to supply a ground potential to the p-type impurity diffusion region 71b, holes from the electron-hole pairs generated by photoelectric conversion may accumulate in the p-type impurity diffusion region 71b, and the potential of the p-type impurity diffusion region 71b may shift in the negative voltage direction depending on the amount of accumulated hole charge. This potential shift in the p-type impurity diffusion region 71b may reduce the capacitance of PD71 and decrease the saturated electron quantity.

[0056] By providing a charge polarity-selective electrode 87 on at least a portion of the surface of PD71, holes generated by photoelectric conversion flow into the impurity region 84 via the contact 86 and pinhole 85. This makes it possible to suppress the potential shift in the p-type impurity diffusion region 71b and reduce the decrease in the saturation electron number.

[0057] As will be described later, the charge polarity selective electrode 87 can be connected to ground or configured to be negatively biased, and such configurations can further reduce the decrease in the saturation electron number and increase the saturation electron amount.

[0058] In the effective pixel 31 shown in Figure 3, an example is shown in which charge polarity selective electrodes 87 are provided between the pixels. When such an effective pixel 31 is viewed in a planar configuration example along the line segment B-B' in Figure 3, it takes the configuration shown in Figure 4B. Since the charge polarity selective electrodes 87 are located at the same position as the element isolation section 81 (the trench 82 located at the same position as the element isolation section 81), the charge polarity selective electrodes 87 are provided so as to surround the effective pixels 31-1 to 31-4. The charge polarity selective electrodes 87 are also provided in the region between the effective pixels 31-1 to 31-4, excluding the region in which the FD91 is provided.

[0059] In the example shown in Figure 4B, PD71-1 to 71-4 are provided in the center of each of the effective pixels 31-1 to 31-4, and charge polarity selective electrodes 87 are formed to surround each of the PD71-1 to 71-4. The above-mentioned effect can be obtained by providing the charge polarity selective electrodes 87 on a part of the side surface of the PD71. In addition to the configuration in which charge polarity selective electrodes 87 are provided on all four sides of the PD71, it is also possible to provide the charge polarity selective electrodes 87 on one, two, or three sides. Furthermore, it is also possible to provide the charge polarity selective electrodes 87 on a part of the side surface of the PD71.

[0060] <Second Embodiment> Figure 5 shows an example of the cross-sectional configuration of the effective pixel 31 in the second embodiment.

[0061] In the first embodiment, the effective pixel 31 is described using as an example a case in which the polarity of the PD 71 is n-type, and the n-type impurity diffusion region 71a is contained within the p-type impurity diffusion region 71b, and electrons generated by photoelectric conversion are read out.

[0062] In the second embodiment, the effective pixel 31 has a p-type polarity of PD71, and the p-type impurity diffusion region 71b is contained within the n-type impurity diffusion region 71a, and the hole generated by photoelectric conversion is read out.

[0063] The charge polarity-selective electrode 87' (described with a dash to indicate that it differs from the charge polarity-selective electrode 87 in the first embodiment) consists of a sidewall film 83, an impurity region 84', a pinhole 85', and a contact 86'. The charge polarity-selective electrode 87' functions as an electrode through which only electron current selectively flows.

[0064] In this case, the sidewall film 83 is formed of silica, for example. The impurities doped into the impurity region 84' are impurities that make the impurity region 84' a p-type region, such as P (phosphorus), As (arsenic), Sb (antimony), etc. The impurity region 84' is defined as a region containing, for example, 1e18 cm⁻³ or more of the impurity.

[0065] This technology can be applied regardless of the polarity of PD71 by selecting appropriate impurities for doping the impurity region 84 that constitutes the charge polarity-selective electrode 87, based on the polarity of PD71.

[0066] In the second embodiment, as in the first embodiment, a charge polarity-selective electrode 87' is provided on at least a portion of the surface of PD71. This configuration allows electrons generated by photoelectric conversion to flow into the impurity region 84' via the contact 86' and pinhole 85', thereby suppressing the potential shift in the n-type impurity diffusion region 71a and reducing the decrease in the saturated hole number.

[0067] In the following embodiments, we will continue the explanation using the case where the polarity of PD71 is n-type, as shown in the first embodiment, as an example. In the following embodiments, it is of course possible to apply the case where the polarity of PD71 is p-type, as described in the second embodiment.

[0068] <Regarding the manufacturing of an effective pixel 31 having a charge polarity-selective electrode 87> The manufacturing of the effective pixel 31 having the charge polarity selective electrode 87 shown in Figure 3 will be explained with reference to Figures 6 and 7.

[0069] In step S11, a mask is formed on the Si substrate 70, and trenches that will become the element isolation area 81 (STI) are formed by dry etching. After the trenches are formed, an oxide film is embedded, and the surface is planarized by CMP processing. The trenches formed in step S11 are the size of the portion that will become the element isolation area 81, and their depth is formed to a depth of, for example, about 150 nm, and within the range of 50 to 1000 nm.

[0070] In step S12, a mask 101 is formed on the Si substrate 70, and trenches 82 are formed by dry etching. The trenches 82 are formed between pixels and are regions where charge polarity selective electrodes 87 are formed. The depth of the trenches 82 is formed to a depth of, for example, about 5 μm, and is formed in a depth range of 500 to 10 μm.

[0071] In step S13, after the mask 101 is removed, a thin film of silica, for example, is deposited to form the sidewall film 83. The silica thin film is formed to a thickness of, for example, about 1.5 nm, and is formed to a thickness in the range of 0.5 to 10 nm. The silica thin film is formed on the sidewall of the trench 82, becoming the sidewall film 83. Inside the sidewall film 83, a polysilicon doped with, for example, boron (B) is deposited. The density of the dopant impurity is, for example, about 1e20 cm⁻³, and is set to a concentration in the range of 1e18 to 1e21 cm⁻³. The inside of the trench 82 becomes filled with polysilicon. The polysilicon filled in the trench 82 is the region that becomes the impurity region 84 that constitutes the charge polarity selective electrode 87.

[0072] In step S14, the polysilicon film deposited in step S13 is etched back. The depth of the etched polysilicon on the surface of the Si substrate 70 is, for example, about 150 nm, and is within the range of 50 to 1000 nm.

[0073] In step S15, an insulating film is formed. The insulating film is formed on the side of the Si substrate 70 where the element isolation portion 81 is formed, and the material is also filled into the portion that will become the element isolation portion 81. The material of the insulating film (element isolation portion 81) is an insulating material containing at least one of Si (silicon), N (nitrogen), Al (aluminum), and Hf (hafnium).

[0074] For example, the insulating film (element isolation portion 81) may be composed of a silicon nitride film, an aluminum oxide film, a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, a silicon aluminum nitride film, a silicon aluminum oxide film, a hafnium oxide film, a hafnium aluminum oxide film, etc., and may also be a laminated structure of these insulating films.

[0075] In step S15, annealing is performed to form pinholes 85 and contacts 86. After the insulating film is filled, for example, annealing is performed at a temperature of 800-850 degrees Celsius for about 30 minutes, thereby forming pinholes 85 in the sidewall film 83 and contacts 86 on the sidewall of the sidewall film 83.

[0076] In process S16 (Figure 7), ion implantation, etching, insulating film deposition, metal deposition, CMP process, etc., are used to form transistors such as PD71 and transfer transistor 76, FD91, etc., on the wiring layer 75.

[0077] In step S17, the Si substrate 70 is turned over and thinned to a thickness of, for example, 10 μm or less. The thickness of the Si substrate 70 after thinning is shorter than the depth of the trench 82. As a result, the polysilicon (impurity region 84) embedded in the trench 82 is exposed.

[0078] In step S18, an insulating sealing film 72 is formed. If the configuration includes a fixed charge film and an anti-reflective film, for example, the fixed charge film is formed using the Atomic Layer Deposition (ALD) process, the anti-reflective film is formed using the Chemical Vapor Deposition (CVD) process, and then the insulating sealing film 72 is formed.

[0079] In step S19, a color filter 73 and an on-chip lens 74 are formed on the insulating sealing film 72. If a light-shielding wall (spacer) is provided at a position corresponding to the pixels of the color filter, it is formed in step S19. Also, if a light-shielding wall is provided, a liner insulating film is formed as well, and this is also formed in step S19.

[0080] An effective pixel 31 equipped with a charge polarity-selective electrode 87 is manufactured through this process.

[0081] <Third Embodiment> Figure 8 shows an example of the cross-sectional configuration of the effective pixel 31 in the third embodiment, and Figure 9 shows an example of the planar configuration of the effective pixel 31 along the line segment A-A' in Figure 8.

[0082] The configuration of the effective pixel 31 shown in Figure 8 is the same as that of the effective pixel 31 shown in Figure 3, except that the charge polarity selective electrode 87 is connected to a source that supplies ground potential or a predetermined potential.

[0083] Conventionally, the effective pixel 31 was provided with a well contact connected to a supply source that supplied a ground potential or a predetermined potential. The contact region where this well contact is provided is a region to which a predetermined impurity is added at a high concentration, and is formed by ion implantation, thermal diffusion (solid-phase diffusion, liquid-phase diffusion, or gas-phase diffusion), plasma doping, or epitaxial growth.

[0084] By connecting the charge polarity-selective electrode 87 to a source that supplies a ground potential or a predetermined potential, it becomes unnecessary to form a well contact, and a transistor, for example, can be placed in the region where the well contact was formed.

[0085] Referring to the planar configuration example shown in Figure 9, the amplification transistor 78 (AMP) is formed in an L-shape, and the transfer transistors 76 and FD91 are also formed. If a well contact were to be formed, the amplification transistor 78, which is formed in an L-shape, would need to be made smaller to secure the area for forming the well contact. By creating a structure that does not require a well contact, the amplification transistor 78 can be extended to the area where the well contact was previously located, thereby increasing the LW area of ​​the amplification transistor 78. As a result, random noise can be reduced.

[0086] The charge polarity-selective electrode 87 can also be configured to have a voltage of 0V or less (negative bias) applied as a predetermined potential. By applying a negative bias, the electric field in the vertical direction (direction from the light incident surface toward the wiring layer) can be strengthened, improving the efficiency of electron extraction from PD71. Furthermore, pinning at the sidewall of PD71 can be strengthened, improving the dark characteristics.

[0087] When well contacts are formed, as described above, ion implantation is performed or metal contacts are formed, but noise may be generated due to leakage current caused by the diffusion of metal impurities or ion implantation damage. In this technology, well contacts are not formed, and a charge polarity selective electrode 87 is provided, so there is no contamination by metal impurities, no ion implantation damage, and no electron inflow from the electrode, thus the generation of leakage current can be greatly suppressed.

[0088] Furthermore, as described above, by providing the charge polarity-selective electrode 87 on the side of the PD71 and using it as a ground electrode, the ground electrode is eliminated from the planar portion, allowing for the placement of more pixel transistors or a larger arrangement. For example, the area of ​​the gate electrode of the amplification transistor 78 can be increased, or the number of amplification transistors 78 can be increased to effectively increase the area of ​​the gate electrode, thereby enabling a configuration that reduces random noise.

[0089] If well contacts are not formed, for example, an FD91 can be placed in each effective pixel 31, or the number of pixels sharing an FD91 can be reduced, which can increase the conversion efficiency or increase the frame rate, thereby improving the characteristics of the imaging device 1.

[0090] If the charge polarity-selective electrode 87 is configured to be connected to a power source that supplies a predetermined potential (for example, 0 or a negative potential), the connection can be made, for example, by referring to the configuration described in Figures 10 and 11.

[0091] Figure 10 shows an example of the cross-sectional configuration of the effective pixel region 31 and the light-shielding pixel region 32. The effective pixels 31 located in the effective pixel region 31 have a configuration similar to, for example, the effective pixels 31 shown in Figure 3.

[0092] The light-shielding pixel region 32 is a region located adjacent to the effective pixel region 31 and has a cross-sectional configuration as shown in Figure 10. The basic configuration of the light-shielding pixel 32 can be essentially the same as that of the effective pixel 31, except that it is light-shielded. A light-shielding film 121 is formed in the light-shielding pixel region 32 and placed on the light-shielding pixel 32, so that incident light is blocked.

[0093] An insulating sealing film 72 is formed on the upper surface of the PD 71 of the light-shielding pixel 32, a barrier metal 122 is formed on the insulating sealing film 72, and a light-shielding film 121 is formed on the barrier metal 122. The light-shielding film 121 can be made of, for example, W (tungsten). The barrier metal 122 can be made of, for example, titanium nitride. Note that the materials listed here are just examples and are not intended to be limiting.

[0094] Charge polarity-selective electrodes 87 are formed on the sides surrounding the PD 71 located in the light-shielding pixel region 32. The light-shielding pixel region 32 can be configured without an on-chip lens 74. Figure 10 shows a configuration without an on-chip lens 74, in which an oxide film 123 is formed on the light-shielding film 91. The oxide film 123 may be made of the same material as the on-chip lens 74, or it may have the shape of the on-chip lens 74, i.e., a configuration in which an on-chip lens 74 is provided in the light-shielding pixel region 32.

[0095] The light-shielding pixel region 32 may include pixels that lack an n-type impurity diffusion region 71a and only have a p-type impurity diffusion region 71b. In Figure 10, a p-type diffusion layer 131 is formed on such a pixel, and wiring 132 is connected to the p-type diffusion layer 131. The wiring 132 is connected to a power source that supplies a predetermined potential (not shown). When the power source supplies ground potential, ground potential is supplied to the p-type diffusion layer 131, and the p-type impurity diffusion region 71b where the p-type diffusion layer 131 is located becomes ground potential.

[0096] Since the ground potential is also transmitted to the charge polarity-selective electrode 87 that is in contact with the p-type impurity diffusion region 71b, which is the ground potential, the potential of the charge polarity-selective electrode 87 can be set as the ground potential.

[0097] As explained with reference to Figure 4B, the charge polarity selective electrodes 87 are provided between pixels, and since each charge polarity selective electrode 87 is formed in a connected state, a ground potential is supplied to the charge polarity selective electrodes 87 provided in the effective pixel region 31, and the charge polarity selective electrodes 87 can be made to the ground potential.

[0098] Since the charge polarity-selective electrode 87 can be set to the ground potential, and a p-type diffusion layer 131 and wiring 132 are provided to supply the ground potential to the light-shielding pixel region 32, it is possible to have a configuration in which it is not necessary to provide a well contact for supplying the ground potential to the effective pixel 31.

[0099] When a negative potential is supplied to the p-type diffusion layer 131, the charge polarity selectivity electrode 87 is negatively biased. In this case as well, it is possible to have a configuration that does not require a well contact to apply a negative bias to the effective pixel 31.

[0100] Figure 10 shows an example where the light-shielding film 121 is configured to be in contact with the charge polarity-selective electrode 87. The light-shielding film 121 may also be configured not to be in contact with the charge polarity-selective electrode 87, but to be in contact with the p-type impurity diffusion region 71b where the p-type diffusion layer 131 is provided. Since the light-shielding film 121 is at the same potential as the charge polarity-selective electrode 87, if the charge polarity-selective electrode 87 is configured to be at ground potential, the light-shielding film 121 will also be at ground potential.

[0101] Figure 11 shows another example of a configuration relating to the connection between a power source that supplies a predetermined potential and a charge polarity selective electrode 87. In the configuration shown in Figure 11, a contact 141 is formed on the charge polarity selective electrode 87 provided in the light-shielding pixel region 32, a wire 142 is connected to the contact 141, and a power source (not shown) that supplies a predetermined potential is connected to the wire 142.

[0102] In the configuration shown in Figure 11, during the manufacturing process S14 as described with reference to Figure 6, the impurity region 84 filled in the trench 82 is not etched back, and the impurity region 84 is left in the part corresponding to the element isolation section 81, thereby forming the contact 141 that connects to the wiring 142. Since the charge polarity selective electrode 87 and the wiring 142 are connected at the contact 141, the potential of the charge polarity selective electrode 87 becomes the potential supplied by the power source connected via the wiring 142.

[0103] Similar to the configuration described with reference to Figure 10, in the configuration described with reference to Figure 11, the charge polarity selective electrodes 87 are connected to each other in a plan view. Therefore, the charge polarity selective electrodes 87 within the effective pixel region 31 are also connected to the charge polarity selective electrodes 87 having contacts 141, and the potential supplied to the charge polarity selective electrodes 87 having contacts 141 is the same as that supplied to the charge polarity selective electrodes 87 having contacts 141.

[0104] In this way, the potential of the charge polarity selective electrode 87 can be set to a potential supplied from the outside, so for example, as shown in Figure 12, a configuration in which a transistor is placed in the region where the well contact was provided can also be applied. The effective pixel 31 shown in Figure 12, like the effective pixel 31 shown in Figure 4A, consists of four 2x2 effective pixels 31, and these four effective pixels 31 share the FD91 located in the center.

[0105] According to this technology, a configuration can be achieved in which a transistor is placed in each of the four 2x2 pixels. In the example shown in Figure 12, a conversion efficiency switching transistor 151 is placed in the upper left effective pixel 31-1, a selection transistor 79 is placed in the lower left effective pixel 31-2, an amplification transistor 78 is placed in the upper right effective pixel 31-3, and a selection transistor 79 is placed in the lower right effective pixel 31-4.

[0106] By incorporating a transistor 151 for switching conversion efficiency, the conversion efficiency can be changed, thereby expanding the dynamic range.

[0107] If this embodiment is not applied, a well contact is placed in the region where the conversion efficiency switching transistor 151 is located, and the conversion efficiency switching transistor 151 cannot be placed there. However, by applying this embodiment, it is possible to have a configuration in which the well contact is not placed, and a configuration in which the conversion efficiency switching transistor 151 is placed.

[0108] Thus, this technology makes it possible to place a transistor in each pixel. Furthermore, even when a transistor is placed in each pixel, it can be placed without increasing the area for placing the transistor, thus enabling the placement of a transistor in each pixel without hindering pixel miniaturization.

[0109] Figure 13 shows an example of a planar configuration in which eight pixels in a 2x4 arrangement share an FD91 and are equipped with the charge polarity selective electrode 87 described above. In Figure 13, effective pixels 31-1 to 31-8 are arranged, and these eight effective pixels 31 share an FD91-1 and an FD91-2. FD91-1 and FD91-2 are connected, for example, by wiring not shown, and function as a single FD91.

[0110] An amplifying transistor 78-1 is located in the upper left effective pixel 31-1, an amplifying transistor 78-2 is located in the second effective pixel from the top on the left 31-2, an amplifying transistor 78-3 is located in the upper right effective pixel 31-3, and a selection transistor 79 is located in the second effective pixel from the top on the right 31-4. An amplifying transistor 78-4 is located in the third effective pixel from the top on the left 31-5, an amplifying transistor 78-5 is located in the fourth effective pixel from the top on the left 31-6, a reset transistor 77 is located in the third effective pixel from the top on the right 31-7, and an amplifying transistor 78-6 is located in the fourth effective pixel from the top on the right 31-8.

[0111] In the configuration shown in Figure 13, where eight effective pixels 31 share one FD91, six amplification transistors 78 are arranged. Therefore, the effective LW of the amplification transistors 78 can be increased, making it possible to reduce random noise.

[0112] <Fourth Embodiment> Figure 14 shows an example of the cross-sectional configuration of the effective pixel 31 in the fourth embodiment.

[0113] The effective pixel 31 in the fourth embodiment is similar to the effective pixel 31 in the first embodiment shown in Figure 3 in that it has charge polarity selective electrodes 87 between the pixels, but it differs in that a doping layer 171 is formed on the contact 86 side.

[0114] In the fourth embodiment, the effective pixel 31 has a configuration in which trenches 82 are provided between the pixels, a sidewall film 83 is formed on the sidewall wall of the trench 82, and an impurity region 84 is filled in the region surrounded by the sidewall film 83 within the trench 82. This impurity region 84 is connected to a contact 86 formed on the sidewall of the trench 82 via a pinhole 85. This configuration is similar to the charge polarity selective electrode 87 described above, for example with reference to Figure 3.

[0115] Furthermore, in the effective pixel 31 of the fourth embodiment, a doping layer 171 is formed on the side wall of the trench 82 in which the contact 86 is formed, in other words, on the side wall of the trench 82 on the PD71 side, by plasma doping, for example, with boron (B). The charge polarity selective electrode 172 in the fourth embodiment has a configuration that includes a side wall film 83, an impurity region 84, a pinhole 85, a contact 86, and a doping layer 171.

[0116] The impurities in the impurity region 84 and the impurities doped into the doping layer 171 may be the same material, or they may be different materials that yield the same polarity.

[0117] By filling the interface of trench 82 on the PD71 side with holes created by boron doping, the generation of leakage current at the interface can be further suppressed.

[0118] <Fifth Embodiment> Figure 15 shows an example of the cross-sectional configuration of the effective pixel 31 in the fifth embodiment.

[0119] The effective pixel 31 in the fifth embodiment is similar to the effective pixel 31 in the first embodiment shown in Figure 3 in that it has charge polarity selective electrodes 87 between pixels, but it differs in that a void 181 is provided within the impurity region 84 that constitutes the charge polarity selective electrodes 87.

[0120] In the fifth embodiment, the effective pixels 31 are provided with charge polarity selective electrodes 182 between the pixels. These charge polarity selective electrodes 182, like the charge polarity selective electrodes 87 shown in Figure 3, are configured to include a sidewall film 83, an impurity region 84, a pinhole 85, and a contact 86. A void 181 is formed within the impurity region 84 of the charge polarity selective electrodes 182. While the void 181 is used as an example here, a configuration in which a predetermined insulating material is embedded is also possible.

[0121] In the fifth embodiment, the charge polarity-selective electrode 182 has a configuration that includes a sidewall film 83, an impurity region 84 including a void 181, a pinhole 85, and a contact 86.

[0122] The impurity region 84 is composed of polysilicon, but since polysilicon is a light absorber, by providing a void 181 (insertion of an insulator), the volume of polysilicon can be reduced, thereby reducing the amount of light absorbed by the polysilicon. Therefore, the quantum efficiency can be improved.

[0123] <Sixth Embodiment> Figure 16 shows an example of the cross-sectional configuration of the effective pixel 31 in the sixth embodiment.

[0124] The effective pixel 31 in the sixth embodiment is similar to the effective pixel 31 in the first embodiment shown in Figure 3 in that it has charge polarity selective electrodes 204 between the pixels, but it differs in that a fixed charge film 201 is deposited on the contact 86 side.

[0125] In the sixth embodiment, the effective pixel 31 is provided with a charge polarity selective electrode 204 between pixels. This charge polarity selective electrode 204 has the same configuration as the charge polarity selective electrode 87 shown in Figure 3, comprising a side wall film 83, an impurity region 84, a pinhole 85, and a contact 86.

[0126] Furthermore, a fixed charge film 201 having a fixed charge is deposited on the side wall of the trench 82 in which the contact 86 is formed, in other words, on the side wall of the trench 82 on the PD71 side. The fixed charge film 201 is, for example, a negative fixed charge film. By inducing holes by the fixed charge film 201, a hole accumulation region is formed inside the fixed charge film 201. Dark current can be suppressed by the fixed charge film 201.

[0127] In the sixth embodiment, the charge polarity-selective electrode 172 has a configuration that includes a sidewall film 83, an impurity region 84, a pinhole 85, a contact 86, and a fixed charge film 201.

[0128] The fixed charge film 201 shown in Figure 16 has a structure in which a silicon nitride film 202 and an alumina film 203 are stacked. For example, the fixed charge film 201 can be made of an insulating material containing at least one of the following: Si (silicon), N (nitrogen), Al (aluminum), Hf (hafnium), Ta (tantalum), Ti (titanium), O (oxygen), Ca (calcium), Mg (magnesium), Li (lithium), Sr (strontium), Sc (scandium), Ba (barium), Nb (niobium), W (tungsten), Mo (molybdenum), Zr (zirconium), La (lanthanum), Gd (gadolinium), and Y (yttrium). Alternatively, the fixed charge film may have a structure in which films containing these materials are stacked.

[0129] For example, the fixed charge film 201 may be composed of a silicon nitride film, an aluminum oxide film, a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, a silicon aluminum nitride film, magnesium oxide, a silicon aluminum oxide film, a hafnium oxide film, a hafnium aluminum oxide film, a tantalum oxide film, a titanium oxide film, a scandium oxide film, a zirconium oxide film, a gadolinium oxide film, a lanthanum oxide film, or a yttrium oxide film, niobium pentoxide, calcium oxide, lithium oxide, strontium oxide, barium oxide, tungsten oxide, or a molybdenum oxide film, and may also be a laminated structure of these insulating films.

[0130] The thickness of the fixed charge film 201 is, for example, about 10 nm, and it is deposited with a thickness in the range of 1 to 100 nm.

[0131] By making the charge polarity-selective electrode 204 a structure in which a fixed charge film 201 containing a material having a negative fixed charge and a side wall film 83 formed of silica or the like are laminated, it is possible to create a structure that can induce holes at the interface and reduce interfacial leakage current.

[0132] <Seventh Embodiment> Figure 17 shows an example of the cross-sectional configuration of the effective pixel 31 in the seventh embodiment.

[0133] The effective pixels 31 in the seventh embodiment are similar to the effective pixels 31 in the first embodiment shown in Figure 3 in that they have charge polarity selective electrodes 87 between the pixels, but the trench 211 in which the charge polarity selective electrodes 87 are provided is formed without penetrating the Si substrate 70.

[0134] The trench 211 shown in Figure 17 is excavated partway into the Si substrate 70 and has a structure that does not come into contact with the element isolation section 81. A sidewall film 83 is formed on the sidewall of the trench 211 provided between pixels, and an impurity region 84 is filled in the area surrounded by the sidewall film 83 within the trench 211. This impurity region 84 is connected to a contact 86 formed on the sidewall of the trench 211 via a pinhole 85.

[0135] The trench 211 is formed during manufacturing by being carved out from the light incident surface side (the side on which the color filter 73 and on-chip lens 74 are located).

[0136] The charge polarity-selective electrode 87 can be provided in a trench 82 that penetrates the Si substrate 70, or in a trench 211 that does not penetrate the Si substrate 70.

[0137] <Eighth Embodiment> Figure 18 shows an example of the cross-sectional configuration of the effective pixel 31 in the eighth embodiment, and Figure 19 shows an example of the planar configuration of the effective pixel 31 at the position where the element separation section 81 is provided.

[0138] The effective pixel 31 in the first to seventh embodiments differs in that, for example, the effective pixel 31 in the first embodiment shown in Figure 3 is provided with a charge polarity selective electrode 87 in the trench 82, while the effective pixel 31 in the eighth embodiment differs in that a charge polarity selective electrode 221 is provided in the element isolation section 81.

[0139] The charge polarity-selective electrode 221 provided in the element isolation section 81 has an impurity region 224 formed inside in which a predetermined impurity is injected, and a side wall film 223 is formed so as to surround the impurity region 224. The impurity region 224 is a region filled with polysilicon into which impurities such as B (boron), Al (aluminum), Ga (gallium), and In (indium) are injected. The impurity region 224 is connected to the p-type impurity diffusion region 71b via a pinhole 225 and a contact 226.

[0140] Figure 18 shows an example in which a polysilicon electrode 231 is formed in a trench 82 provided between pixels. A sidewall film 232 is formed on the side wall of the trench 82, and an impurity region 233, doped with, for example, boron, is formed inside it. This configuration is the same as the charge polarity selective electrode 87 described with reference to Figure 3, for example, but with the pinhole 85 and contact 86 removed.

[0141] In a polysilicon electrode 231 having such a configuration, by forming the sidewall film 232 thickly, for example to a thickness of about 20 nm, no pinholes 85 or contacts 86 are formed during manufacturing, and a polysilicon electrode 231 consisting of the sidewall film 232 and impurity regions 233 can be formed.

[0142] During pixel operation, a negative bias can be applied to the polysilicon electrode 231 to suppress leakage at the side walls of the trench 82. The polysilicon electrode 231 may be a transparent electrode made of a transparent material or a metal electrode made of metal.

[0143] The polysilicon electrode 231 and the charge polarity selective electrode 221 formed on the element isolation portion 81 are positioned between the sidewall films 232 and 223, and the polysilicon electrode 231 and the charge polarity selective electrode 221 are configured not to come into contact with each other.

[0144] In the effective pixel 31 shown in Figure 18, a configuration can be made in which different potentials are supplied to the polysilicon electrode 231 provided between the pixels and the charge polarity selective electrode 221 provided in the element isolation section 81.

[0145] The charge polarity selective electrode 221 provided in the element isolation section 81 can be configured to receive a ground potential or a negative bias, thereby reducing the decrease in the saturation electron number and increasing the saturation electron quantity.

[0146] Even when the element isolation section 81 is configured as a charge polarity-selective electrode 221, it is possible to suppress the potential shift in the p-type impurity diffusion region 71b, just as in the first to seventh embodiments, and to reduce the decrease in the saturation electron number.

[0147] In the effective pixel 31 shown in Figure 18, an example is shown in which the element isolation portion 81 adjacent to the gate electrode of the transfer transistor 76-2 does not have a charge polarity selective electrode 221. In the case where the gate electrode of the transfer transistor 76-2 and the element isolation portion 81 are provided in close proximity as shown in Figure 18, if the charge polarity selective electrode 221 were provided in this element isolation portion 81 and a negative bias were applied, a large potential difference would be generated between the gate electrode and the charge polarity selective electrode 221, which could affect the operation of the transfer transistor 76-2. To prevent this, Figure 18 shows an example in which the element isolation portion 81 provided adjacent to the gate electrode of the transfer transistor 76-2 does not have a charge polarity selective electrode 221.

[0148] The gate electrode of the transfer transistor 76-2 may be positioned at a location not adjacent to the element isolation section 81, for example, at a location midway between the element isolation sections 81, so as to maintain a distance from the charge polarity selective electrode 221. In this configuration, the charge polarity selective electrode 221 can be provided even to element isolation sections 81 that do not have the charge polarity selective electrode 221 shown in Figure 18.

[0149] In the effective pixel 31 shown in Figure 18, an example is shown in which a charge polarity selective electrode 221 is provided in the element isolation section 81 between pixels. When an effective pixel 31 with such a configuration is viewed in a planar configuration example in the part where the element isolation section 81 in Figure 18 is provided, the configuration is as shown in Figure 19.

[0150] The element isolation section 81 is provided so as to surround the effective pixels 31-1 to 31-4, and is also provided in the area between the effective pixels 31-1 to 31-4, excluding the area where the FD91 is provided. The charge polarity selective electrode 221 is provided in a part of the element isolation section 81.

[0151] In the example shown in Figure 19, the charge polarity selective electrode 221 is provided in a T-shape that includes a part of the element isolation section 81 provided between effective pixels 31-1 and 31-2, and is also provided in a T-shape that includes a part of the element isolation section 81 provided between effective pixels 31-3 and 31-4.

[0152] Even if the charge polarity selective electrode 221 is provided in only a part of the element isolation section 81, the above-described effects can still be obtained. Furthermore, the charge polarity selective electrode 221 can be provided throughout the entire element isolation section 81, or in a wider area than the region shown in Figure 19.

[0153] <Ninth Embodiment> Figure 20 shows an example of the cross-sectional configuration of the effective pixel 31 in the ninth embodiment.

[0154] The effective pixel 31 in the ninth embodiment is configured to have a charge polarity-selective electrode 221 in the element isolation section 81, similar to the effective pixel 31 in the eighth embodiment (Figure 18), and also has a charge polarity-selective electrode 87 in the trench 82.

[0155] In the ninth embodiment shown in Figure 20, the effective pixel 31 has a charge polarity selective electrode 87 provided in a trench 82 provided between pixels, and a charge polarity selective electrode 221 provided in an element isolation section 81. The charge polarity selective electrode 87 and the charge polarity selective electrode 221 are connected. Therefore, when a ground potential is supplied to the charge polarity selective electrode 87 or the charge polarity selective electrode 221, both the charge polarity selective electrode 87 and the charge polarity selective electrode 221 also become ground potential, and when a negative bias is applied, both the charge polarity selective electrode 87 and the charge polarity selective electrode 221 also become negatively biased.

[0156] In the configuration shown in Figure 20, the gate electrode of the transfer transistor 76 is positioned near the center of the PD71, in other words, midway between the element isolation sections 81. By positioning the gate electrode of the transfer transistor 76 near the center of the PD71, a distance can be maintained from the element isolation section 81. For example, even if a negative bias is applied, the operation of the transfer transistor 76 can be prevented from being affected by the charge polarity selective electrode 221 being provided over the entire region where the element isolation section 81 is formed.

[0157] The density of the contacts 86 of the charge polarity-selective electrode 87 and the density of the contacts 226 of the charge polarity-selective electrode 221 may be configured to be different. For example, the density of the contacts 86 of the charge polarity-selective electrode 87 can be configured to be lower than the density of the contacts 226 of the charge polarity-selective electrode 221, and Figure 20 shows such a configuration.

[0158] By forming a thicker sidewall film 83 that constitutes the charge polarity-selective electrode 87, the density of the contact 86 can be reduced. As the density of the contact 86 decreases, the density of the p-type impurity diffusion region at the interface between the trench 82 and the p-type impurity diffusion region 71b decreases, which prevents the lateral spreading of the depletion layer of PD71 from being hindered. This allows the width of the depletion layer of PD71 (in the direction indicated by the arrow in the figure) to be increased, and the number of saturated electrons to be increased.

[0159] By forming a thin sidewall film 223 that constitutes the charge polarity-selective electrode 221, the density of the contacts 226 can be increased. This increased density of contacts 226 strengthens the electrical connection between the impurity region 228 and the Si substrate 70, reducing the resistance of the contacts 226. For example, in a configuration where a ground potential is supplied, this allows for greater stability of the ground potential.

[0160] In this way, the thickness of the sidewall film 83 included in the charge polarity selective electrode 87 provided in the trench 82 provided between pixels and the thickness of the sidewall film 223 included in the charge polarity selective electrode 221 provided in the element isolation section 81 can be configured to be different.

[0161] In this explanation, we have used the example where the thickness of the sidewall film 83 is greater than the thickness of the sidewall film 223. However, the thickness of the sidewall film 83 can also be formed to be thinner than the thickness of the sidewall film 223, and this case is also included in this embodiment.

[0162] <Tenth Embodiment> Figure 21 shows an example of the cross-sectional configuration of the effective pixel 31 in the tenth embodiment, and Figure 22 shows an example of the planar configuration of the effective pixel 31 along the line segment C-C' in Figure 21.

[0163] As a tenth embodiment, we will explain the case in which this technology is applied to a phase-difference detection image. A phase-difference detection pixel is a pixel provided in the pixel array section 3 to realize the AF (autofocus) function, and as shown in Figures 21 and 22, it is a pixel in which the area surrounded by the trench 82 is divided into two regions. A phase difference is calculated according to the signals obtained from each of the two regions provided in the pixel 2, and autofocus is realized by adjusting the position of the lens, etc., according to that phase difference.

[0164] The effective pixel 31, which functions as a phase difference detection pixel, is configured to include two PD71s. In one of the effective pixels 31, the left region (hereinafter referred to as the phase difference detection pixel 31L as appropriate) is provided with a PD71L, and a transfer transistor 76L is provided to transfer charge from the PD71 to the FD91L. A charge polarity selective electrode 87L is provided to the left of the PD71L, and a charge polarity selective electrode 87M is provided to the right. The configuration of the PD71L is basically the same as the configuration of the effective pixel 31 shown in Figure 3.

[0165] In one effective pixel 31, the right-hand region (hereinafter referred to as the phase difference detection pixel 31R as appropriate) is provided with a PD71R, and a transfer transistor 76R is provided to transfer charge from PD71 to FD91R. A charge polarity selective electrode 87R is provided to the right of PD71R, and a charge polarity selective electrode 87M is provided to the left. The configuration of PD71R is basically the same as the configuration of the effective pixel 31 shown in Figure 3.

[0166] Each of the two phase difference detection pixels 31 contained within one effective pixel 31 is configured to be equipped with a charge polarity selective electrode 87. Therefore, the phase difference detection pixel 31L and the phase difference detection pixel 31R are configured to be able to obtain the same effects as in the embodiment described above.

[0167] Referring to the plan view shown in Figure 22, effective pixel 31-1 is located in the upper left of the figure, effective pixel 31-2 is located in the lower left of the figure, effective pixel 31-3 is located in the upper right of the figure, and effective pixel 31-4 is located in the lower right of the figure. Effective pixel 31-1 includes phase difference detection pixels 31-1R and 31-1L, effective pixel 31-2 includes phase difference detection pixels 31-2R ​​and 31-2L, effective pixel 31-3 includes phase difference detection pixels 31-3R and 31-3L, and effective pixel 31-4 includes phase difference detection pixels 31-4R and 31-4L.

[0168] A charge polarity selective electrode 87 is provided so as to surround effective pixels 31-1 to 31-4. Focusing on effective pixel 31-1, the charge polarity selective electrode 87 is provided so as to surround effective pixel 31-1, and a charge polarity selective electrode 87 (corresponding to charge polarity selective electrode 87M) is also provided between phase difference detection pixels 31-1R and 31-1L included in effective pixel 31-1. The charge polarity selective electrode 87M is formed in a shape with a break in the central part. Effective pixels 31-2 to 31-4 have the same configuration as effective pixel 31-1.

[0169] Thus, this technology can also be applied to phase difference detection pixels. In phase difference detection pixels, the same effects as in the first to ninth embodiments can be obtained by providing a charge polarity selective electrode 87.

[0170] <Embodiment 11> Figure 23 shows an example of the cross-sectional configuration of the effective pixel 31 in the eleventh embodiment, and Figure 24 shows an example of the planar configuration of the effective pixel 31 along the line segment C-C' in Figure 23.

[0171] The effective pixel 31 in the 11th embodiment differs from the effective pixel 31 in the 10th embodiment (Figures 21 and 22) in that the trench 82 formed between the phase difference detection pixel 31L and the phase difference detection pixel 31R is a non-penetrating trench and does not have a charge polarity selective electrode 87M formed therein, but is otherwise the same.

[0172] A trench 251 is formed between the phase difference detection pixel 31L and the phase difference detection pixel 31R. The side walls of the trench 251 are formed with a fixed charge film 253 made of, for example, alumina, and an oxide film 252 made of, for example, silica is formed inside the fixed charge film 253. The fixed charge film 253 is provided as, for example, a negative fixed charge film.

[0173] By forming the trench 251 as a non-penetrating trench, a region for arranging the FD91 can be secured on the lower side of the trench 251 in the figure. This FD91 is used as a FD shared by the phase difference detection pixel 31L and the phase difference detection pixel 31.

[0174] Referring to the example of the planar configuration shown in Figure 24, if we focus on the effective pixel 31-1 located in the upper left of the figure, a charge polarity selective electrode 87 is provided so as to surround the effective pixel 31-1.

[0175] In the central part of the effective pixel 31-1, a trench 251 is provided between the phase difference detection pixel 31-1R and the phase difference detection pixel 31-1L included in the effective pixel 31-1, and a non-penetrating trench 251 is provided in the Si substrate 70. A fixed charge film 253 is provided in the trench 251, and an oxide film 252 is formed on the inside of the fixed charge film 253.

[0176] In this way, by providing a fixed charge film 253 with a negative fixed charge between the phase difference detection pixel 31L and the phase difference detection pixel 31, the interfacial leakage current can be suppressed.

[0177] <Twelfth Embodiment> Figure 25 is a diagram showing an example of the cross-sectional configuration of the effective pixel 31 in the twelfth embodiment, and Figure 25 is a diagram showing an example of the planar configuration of the effective pixel 31 along the line segment D-D' in Figure 23.

[0178] In the first to eleventh embodiments, the case in which charge polarity selective electrodes 87 are formed between pixels was described as an example. However, the charge polarity selective electrodes 87 only need to be provided on any of the side, top, or bottom surfaces of the PD71, and even if they are provided on only one of these surfaces, the above-described effects can be obtained. In the twelfth embodiment, as shown in Figure 25, the effective pixel 31 shows an example in which the charge polarity selective electrodes 87 are provided on the top surface (light incident surface side) of the PD71 in the figure.

[0179] The effective pixel 31 shown in Figure 25 has a trench 82 formed to surround the PD 71, and an insulating layer 301 filled with, for example, silica is formed inside the trench 82. This insulating layer 301 can be connected to an insulating sealing film 72 that is formed on the light incident surface side. The insulating layer 301 and the insulating sealing film 72 can be made of the same material and formed in the same process during manufacturing.

[0180] The charge polarity selective electrode 87 is located in the center of the trench 82 and is formed within the insulating sealing film 72. The charge polarity selective electrode 87 has the same configuration as in the embodiment described above, including a side wall film 83, an impurity region 84, a pinhole 85, and a contact 86.

[0181] The sidewall film 83 and the insulating seal film 72 can also be formed from silica, and the sidewall film 83 can be formed as part of the insulating seal film 72.

[0182] As shown in Figure 26, which illustrates a planar configuration example, the charge polarity selective electrode 87 is formed in a grid pattern on a trench 82 that surrounds the PD71, at the same location as the trench 82. As explained with reference to Figures 10 and 11, by connecting the light-shielding pixel region 32 to a supply source that supplies ground potential or negative potential, the charge polarity selective electrode 87 formed on the effective pixel 31 can also be supplied with ground potential or negative potential.

[0183] Thus, a configuration can be made in which the charge polarity-selective electrode 87 is provided between pixels and on the light incident surface side, in a position that does not obstruct the incidence of light to PD71. In this configuration as well, the same effects as in the first to eleventh embodiments can be obtained.

[0184] <13th Embodiment> Figure 27 shows an example of a partial configuration of the cross-section of the effective pixel 31 in the 13th embodiment.

[0185] In the 13th embodiment shown in Figure 27, the effective pixel 31 is provided with a charge polarity selective electrode 87 on the wiring layer 75 side, and the charge polarity selective electrode 87 is configured to function with FD321. The charge polarity selective electrode 87 is provided at a position in contact with the depletion layer, which is in contact with the gate electrode of the transfer transistor 76.

[0186] The contact 86 of the charge polarity-selective electrode 87 is formed in the p-type impurity diffusion region 71b, and the impurity region 84 is formed within the wiring layer 75.

[0187] Conventionally, FDs are formed by high-concentration ion implantation and thermal diffusion, which tends to cause impurities to diffuse over a wide area, resulting in a large required installation area. The charge polarity-selective electrode 87 to which this technology is applied has only a very small diffusion region (contact 86), so even when the charge polarity-selective electrode 87 is placed on the flat surface of the Si substrate 70, the area required for FD installation can be significantly reduced compared to conventional methods.

[0188] By using the charge polarity-selective electrode 87 as FD321, it is possible to place new pixel transistors in the region where FD was conventionally located, or to enlarge the area of ​​the gate electrode of the amplification transistor. Figure 27 shows an example in which the pixel transistor 323 is located on the left side of the FD321 in the figure.

[0189] The charge polarity-selective electrode 87 does not require high-concentration ion implantation or etching of contact holes, and because the metal contact does not come into contact with Si, it generates fewer defects associated with contact formation and can also reduce leakage current.

[0190] Thus, a configuration can be made in which a charge polarity-selective electrode 87 is formed on the wiring layer 75 side and functions as an FD321.

[0191] <Embodiment 14> Figure 28 shows an example of a partial configuration of the cross-section of the effective pixel 31 in the 14th embodiment.

[0192] In the 14th embodiment shown in Figure 28, the effective pixel 31 is equipped with a charge polarity selective electrode 87 on the wiring layer 75 side, and the charge polarity selective electrode 87 is configured to function as a contact. The charge polarity selective electrode 87 is provided at the interface between the PD 71 and the wiring layer 75. The charge polarity selective electrode 87 is used as a contact 331 with the pwell (p-type impurity diffusion region 71b).

[0193] The charge polarity-selective electrode 87, which functions in contact, is connected to a source that supplies a ground potential, for example, and is used as a contact to bring the pwell to ground potential.

[0194] Conventionally, contacts 331 are formed by high-concentration ion implantation and thermal diffusion, which tends to cause impurities to diffuse over a wide area, resulting in a large required installation area. The charge polarity-selective electrode 87 to which this technology is applied has only a very small diffusion region (contact 86), so even when the charge polarity-selective electrode 87 is placed on the flat surface of the Si substrate 70, the area required for installing the pwell contact can be significantly reduced compared to conventional methods.

[0195] By using the charge polarity-selective electrode 87 as the contact 331, it is possible to place new pixel transistors in the area where conventional contacts were located, or to enlarge the area of ​​the gate electrode of the amplification transistor. Figure 28 shows an example in which the pixel transistor 323 is located on the left side of the contact 331 in the figure.

[0196] The charge polarity-selective electrode 87 does not require high-concentration ion implantation or etching of contact holes, and because the metal contact does not come into contact with Si, it generates fewer defects associated with contact formation and can also reduce leakage current.

[0197] Thus, a configuration can be made in which a charge polarity-selective electrode 87 is formed on the wiring layer 75 side and functions as a contact 331.

[0198] <Embodiment 15> Figure 29 shows an example of a partial configuration of the cross-section of the effective pixel 31 in the 15th embodiment.

[0199] In the first to fourteenth embodiments, the effective pixel 31 has a structure in which a Si substrate 70 and a wiring layer 75 are stacked, and an example is shown in which a transistor is formed on the Si substrate 70 side. In the embodiment from Figure 15 onward, the Si substrate 70 and a second substrate 401 on which transistors and the like are formed are stacked, and the effective pixel 31 equipped with the charge polarity selective electrode 87 described above will be explained. In the following description, the Si substrate 70 will be referred to as the first substrate 70 as appropriate.

[0200] The first substrate 70 is a substrate on which pixels including PD71 are formed. Its basic configuration is essentially the same as, for example, the configuration of the effective pixel 31 shown in Figure 3, but it differs in that it does not have transistors such as the amplifying transistor 78 formed on it.

[0201] The second substrate 401 has multiple wiring layers 402 formed on it, and wiring is formed on each wiring layer 402. In the example shown in Figure 29, an amplifying transistor 78 is formed on one of the multiple wiring layers 402 that make up the second substrate 401. The amplifying transistor 78 is connected to wiring 411, and wiring 411 is connected to FD91 formed on the first substrate 70. The second substrate 401 is provided with wiring 412 connected to a diffusion layer 421 formed on the first substrate 70, and wiring 413 connected to a diffusion layer 422 formed within the second substrate 401, in the vertical direction in the figure.

[0202] The diffusion layer 421 formed on the first substrate 70 is, for example, a region with a high concentration of p-type impurities, located within the p-type impurity diffusion region 71b, and formed on the side in contact with the second substrate 401. The wiring 412 connected to the diffusion layer 421 is connected to a source that supplies ground potential (indicated as Y[V] in the figure). In the configuration of the effective pixel 31 shown in Figure 29, the ground potential is supplied to the PD 71 formed on the first substrate 70 via the wiring 412 on the second substrate 401 side.

[0203] The diffusion layer 422 formed on the second substrate 401 is, for example, a region with a high concentration of p-type impurities, located within the p-type impurity region formed within the second substrate 401, and formed within the wiring layer 402 on the second substrate 401 where the transistors are formed. The wiring 413 connected to the diffusion layer 422 is connected to a supply source that supplies a predetermined potential (indicated as X[V] in the figure) to the pixel transistors formed on the second substrate 401.

[0204] A PD71 is formed on the first substrate 70, and a charge polarity-selective electrode 87 is formed surrounding the PD71. In other words, it has the same configuration as the effective pixel 31 in the first embodiment shown in Figure 3.

[0205] Similar to the first embodiment, in the 15th embodiment, by providing a charge polarity-selective electrode 87 on at least a portion of the side surface of PD71, holes generated by photoelectric conversion flow into the impurity region 84 via the contact 86 and pinhole 85, thereby suppressing the potential shift in the p-type impurity diffusion region 71b and reducing the decrease in the saturation electron number.

[0206] <Embodiment 16> Figure 30 shows an example of the cross-sectional configuration of the effective pixel 31 in the 16th embodiment. Figure 31 shows an example of the planar configuration of the effective pixel 31 at positions A, B, and C shown in Figure 30.

[0207] The effective pixel 31 in the 16th embodiment differs from the effective pixel 31 in the 15th embodiment in that the effective pixel 31 is configured such that a ground potential (Y[V]) is supplied to the charge polarity selective electrode 87 formed on the first substrate 70; otherwise, it is basically the same.

[0208] As explained with reference to Figures 8 to 11, the charge polarity selective electrode 87 is formed continuously and extends to the light-shielding pixel region 32. A ground potential supply source is connected to the light-shielding pixel region 32. This configuration can be applied to the first substrate 70, thereby supplying ground potential to the charge polarity selective electrode 87.

[0209] This configuration allows the second substrate 401 to be made thinner. Referring again to Figure 29, in the effective pixel 31 shown in Figure 29, a diffusion layer 421 is provided on the first substrate 70, and wiring 412 for supplying ground potential to the diffusion layer 421 is provided on the second substrate 401. In the effective pixel 31 shown in Figure 30, the diffusion layer 421 provided on the first substrate 70 and the wiring 412 provided on the second substrate 401 can be omitted.

[0210] By omitting the wiring 412 on the second substrate 401, the wiring layer 402 required by providing the wiring 412 can be reduced, the thickness of the second substrate 401 can be reduced, and the imaging device 1 including the effective pixels 31 can be miniaturized.

[0211] Referring again to Figure 29, the wiring 412 is provided in the vertical direction in the figure, but by eliminating this wiring 412, the area for placing transistors such as the amplifying transistor 78 in the wiring layer 402 where the amplifying transistor 78 is located, as shown in Figure 30, can be expanded.

[0212] Figure 31A shows an example of a planar configuration of the effective pixel 31 at position A in Figure 30. At position A, charge polarity selective electrodes 87 are formed so as to surround the PD71 (p-type impurity diffusion region 71b), and the charge polarity selective electrodes 87 are formed in a grid pattern.

[0213] Figure 31B shows an example of a planar configuration of the effective pixel 31 at position B in Figure 30. At position B, an element isolation section 81 is formed so as to surround the PD71 (p-type impurity diffusion region 71b), and the element isolation sections 81 are formed in a grid pattern. When looking at a single PD71 surrounded by the element isolation section 81, an FD91 is provided in the lower left corner of the figure, and the gate electrode of the transfer transistor 76 is provided adjacent to the FD91.

[0214] Figure 31C shows an example of a planar configuration of the effective pixel 31 at position C in Figure 30. Position C is located in the wiring layer 402 of the second substrate 401 where the pixel transistors are arranged, and a portion of the pixel transistors are located in a region of the second substrate 401 where p-type impurities are diffused. A reset transistor 77 (RST), an amplification transistor 78 (AMP), a selection transistor 79 (SEL), a conversion efficiency switching transistor 151 (FCG), etc., can be arranged in this region where p-type impurities are diffused.

[0215] By eliminating the wiring 412, it becomes possible to expand the area where transistors can be placed, allowing for the placement of, for example, the conversion efficiency switching transistor 151 as shown in C of Figure 31.

[0216] In the 16th embodiment, the same effects as in the first to 15th embodiments can be obtained.

[0217] <Embodiment 17> Figure 32 shows an example of the cross-sectional configuration of the effective pixel 31 in the 17th embodiment, and Figure 33 shows an example of the planar configuration of the effective pixel 31 at position A in Figure 32.

[0218] The effective pixel 31 in the 17th embodiment differs from the effective pixel 31 in the 16th embodiment (Figure 30) in that the charge polarity-selective electrode 87 formed on the first substrate 70 is provided on the light incident surface side, but otherwise it is basically the same.

[0219] The 17th embodiment is a combination of the 16th embodiment (Figure 30) and the 12th embodiment (Figure 25). The effective pixel 31 shown in Figure 32 has a charge polarity selective electrode 87 provided on the upper surface (light incident surface side) of the PD71 in the figure. This charge polarity selective electrode 87 has the same configuration as the charge polarity selective electrode 87 described with reference to the 12th embodiment shown in Figure 25.

[0220] The effective pixel 31 shown in Figure 32 has a trench 82 formed to surround the PD 71, and an insulating layer 301 filled with silica, for example, is formed inside the trench 82. This insulating layer 301 is connected to an insulating sealing film 72 formed on the light incident surface side, or the insulating sealing film 72 can be used as part of the sidewall film 83 that constitutes the charge polarity selective electrode 87.

[0221] As shown in Figure 33A, an example of a planar configuration, the trenches 82 are provided between pixels, and the insulating layer 301 formed within the trenches 82 is also provided between pixels. The trenches 82 and the insulating layer 301 are formed to surround the PD71 and are arranged in a grid pattern. The charge polarity selective electrode 87 is formed at the same location as the trenches 82 (insulating layer 301). The charge polarity selective electrode 87 is provided between pixels, formed to surround the PD71 and is arranged in a grid pattern.

[0222] Figure 33B shows another example of a planar configuration of the charge polarity selective electrode 87. As shown in Figure 33B, the charge polarity selective electrode 87 is formed in the same position as the trench 82 (insulating layer 301), but the charge polarity selective electrode 87 is formed continuously on the trench 82 (insulating layer 301) which is formed in the horizontal direction in the figure, and not on the trench 82 which is formed in the vertical direction in the figure.

[0223] The charge polarity selective electrodes 87 shown in Figures 33A and 33B are formed continuously up to the light-shielding pixel region 32. By forming the charge polarity selective electrodes 87 continuously, as explained with reference to Figures 10 and 11, the light-shielding pixel region 32 can be connected to a supply source that supplies ground potential or negative potential. Furthermore, with such a configuration, the charge polarity selective electrodes 87 formed on the effective pixels 31 can also be supplied with ground potential or negative potential.

[0224] Thus, a configuration can be made in which the charge polarity-selective electrode 87 is provided between pixels and on the light incident surface side, in a position that does not obstruct the light to PD71. In this configuration as well, the same effects as in the first to sixteenth embodiments can be obtained.

[0225] <Embodiment 18> Figure 34 shows an example of the cross-sectional configuration of the effective pixel 31 in the 18th embodiment.

[0226] The effective pixel 31 in the 18th embodiment differs from the effective pixel 31 in the 17th embodiment (Figure 32), for example, in that it is provided with a charge polarity-selective electrode 87 on the second substrate 401, but otherwise it is basically the same.

[0227] Referring to Figure 34, the charge polarity selective electrode 87 is provided on the wiring layer 402 in the second substrate 401 where the pixel transistor is located.

[0228] The charge polarity-selective electrode 87 provided within the second substrate 401 functions as a contact that supplies a predetermined potential (X[V]) to the second substrate 401.

[0229] The effective pixels 31 shown in Figure 34 are an example in which charge polarity selective electrodes 87 are not provided between pixels, and the ground potential is supplied from the second substrate 401 side. Therefore, this shows an example configuration in which a diffusion layer 421 is provided on the first substrate 70 and wiring 412 is provided on the second substrate 401.

[0230] Thus, a charge polarity-selective electrode 87 can be provided on the second substrate 401 side and connected to a power source that supplies a predetermined potential to the second substrate 401.

[0231] <Embodiment 19> Figure 35 shows an example of the cross-sectional configuration of the effective pixel 31 in the 19th embodiment.

[0232] The effective pixel 31 in the 19th embodiment differs from the effective pixel 31 in the 18th embodiment (Figure 34) in that a charge polarity selective electrode 87 is also provided on the first substrate 70, but otherwise it is basically the same. Compared to the effective pixel 31 in the 16th embodiment (Figure 30), the difference is that a charge polarity selective electrode 87 is also provided on the second substrate 401, but otherwise it is basically the same.

[0233] The effective pixel 31 shown in Figure 35, like the effective pixel 31 shown in Figure 34, is equipped with a charge polarity-selective electrode 87 within the second substrate 401 and has a configuration that functions as a contact that supplies a predetermined potential (X[V]) within the second substrate 401.

[0234] The effective pixel 31 shown in Figure 35, like the effective pixel 31 shown in Figure 30, is equipped with a charge polarity-selective electrode 87 within the first substrate 70 and functions as an electrode that supplies a predetermined potential (Y[V]) to the first substrate 70 (PD71). The predetermined potential (Y[V]) is either the ground potential or a potential for applying a negative bias.

[0235] In a configuration where charge polarity-selective electrodes 87 are provided on both the first substrate 70 and the second substrate 401, the second substrate 401 can be configured without wiring 412 and wiring 413. Therefore, the wiring layer 402 on which wiring 412 and wiring 413 were provided can be removed from the second substrate 401. In this case, two layers can be reduced. Thus, the second substrate 401 can be made thinner (smaller).

[0236] When the first substrate 70 and the second substrate 401 are each provided with charge polarity-selective electrodes 87, different potentials can be supplied to the first substrate 70 and the second substrate 401.

[0237] <Twentieth Embodiment> Figure 36 shows an example of the cross-sectional configuration of the effective pixel 31 in the 20th embodiment.

[0238] In the 20th embodiment, the effective pixel 31 is provided with a charge polarity selective electrode 87 in the element isolation section 81.

[0239] Figure 36 shows an example in which, for example, a polysilicon electrode 231 is formed in the trench 82 provided between pixels. The polysilicon electrode 231 has the same configuration as the polysilicon electrode 231 of the effective pixel 31 in the eighth embodiment shown in Figure 18.

[0240] The polysilicon electrode 231 has a configuration in which a sidewall film 232 is formed on the side wall of the trench 82, and an impurity region 233, for example, doped with boron, is formed inside. This configuration is the same as the charge polarity selective electrode 87 described with reference to Figure 3, for example, but with the pinhole 85 and contact 86 removed.

[0241] In a polysilicon electrode 231 having such a configuration, by forming the sidewall film 232 thickly, for example to a thickness of about 20 nm, no pinholes 85 or contacts 86 are formed during manufacturing, and a polysilicon electrode 231 consisting of the sidewall film 232 and impurity regions 233 can be formed.

[0242] The configuration of the effective pixel 31 in the first substrate 70 is the same as that of the effective pixel 31 in the eighth embodiment (Figure 18), with a charge polarity selective electrode 221 formed on the element isolation portion 81. As explained with reference to Figure 18, when the gate electrode of the transfer transistor 76 and the element isolation portion 81 are located in close proximity, and a negative bias is applied to the charge polarity selective electrode 221, the potential difference between the gate electrode and the charge polarity selective electrode 221 becomes large, which may affect the operation of the transfer transistor 76.

[0243] To prevent such problems, Figure 36 shows an example where the gate electrode of the transfer transistor 76 is located in a position not close to the element isolation section 81, for example, near the center of the PD71, or in other words, near the center of the element isolation sections 81. By arranging the element isolation section 81 and the gate electrode of the transfer transistor 76 so that they are not close to each other, it is possible to prevent the transfer transistor 76 from being affected even if the charge polarity selective electrode 221 is provided in the element isolation section 81.

[0244] Thus, the element isolation section 81 can also be configured to include a charge polarity-selective electrode 221.

[0245] By providing a charge polarity-selective electrode 221 in the element isolation section 81 and a polysilicon electrode 231 in the trench 82, different potentials can be supplied to each electrode. For example, a configuration can be made in which a ground potential is supplied to the charge polarity-selective electrode 221 and a potential for applying a negative bias is supplied to the polysilicon electrode 231.

[0246] <21st Embodiment> Figure 37 shows an example of the cross-sectional configuration of the effective pixel 31 in the 21st embodiment.

[0247] The effective pixel 31 in the 21st embodiment is different in that the trench 82 of the effective pixel 31 (FIG. 36) in the 20th embodiment is constituted by a non-penetrating trench 211, and other points are basically the same.

[0248] The trench 211 shown in FIG. 37 is dug to the middle of the first substrate 70 and is structured not to contact the element isolation part 81. Inside the trench 211, for example, an insulating layer 301 filled with silica is formed. This insulating layer 301 can be configured to be connected to the insulating encapsulation film 72 formed on the light incident surface side. Also, the insulating layer 301 and the insulating encapsulation film 72 can be made of the same material and can be formed in the same process during manufacturing.

[0249] Thus, this technology can be applied even to a configuration in which pixels are separated by non-penetrating trenches 211.

[0250] <The 22nd Embodiment> FIG. 38 is a diagram showing a cross-sectional configuration example of the effective pixel 31 in the 22nd embodiment.

[0251] The effective pixel 31 in the 22nd embodiment is different in that a charge polarity selective electrode 87 is formed in the non-penetrating trench 211 provided in the effective pixel 31 (FIG. 37) in the 21st embodiment, and other points are basically the same.

[0252] Thus, this technology can be applied even to a configuration in which pixels are separated by non-penetrating trenches 211, and a configuration in which a charge polarity selective electrode 87 is formed in the trench 211 can also be adopted.

[0253] <The 23rd Embodiment> FIG. 39 is a diagram showing a cross-sectional configuration example of the effective pixel 31 in the 23rd embodiment.

[0254] The active pixel 31 in the 23rd embodiment is different in that it is configured not to provide the charge polarity selection electrode 221 of the element isolation part 81 provided in the active pixel 31 (FIG. 38) in the 22nd embodiment, and the other points are basically the same.

[0255] The active pixel 31 in the 23rd embodiment is configured to include a charge polarity selection electrode 87 in the trench 211 and not to include a charge polarity selection electrode 221 in the element isolation part 81. When the element isolation part 81 does not include a charge polarity selection electrode 87, even if the gate electrode of the transfer transistor 76 is close to the element isolation part 81, the influence on the operation of the transfer transistor 76 is small, so as shown in FIG. 39, it can also be arranged near the element isolation part 81.

[0256] <24th Embodiment> FIG. 40 is a diagram showing a cross-sectional configuration example of the active pixel 31 in the 24th embodiment.

[0257] The active pixel 31 in the 24th embodiment is different in that it is configured not to provide the element isolation part 81 provided in the active pixel 31 (FIG. 39) in the 23rd embodiment, and the other points are basically the same.

[0258] The active pixel 31 in the 23rd embodiment is configured to include a charge polarity selection electrode 87 in the trench 211 and not to include the element isolation part 81. Thus, the present technology can also be applied even when the element isolation part 81 is not provided.

[0259] <25th Embodiment> FIG. 41 is a diagram showing a cross-sectional configuration example of the active pixel 31 in the 25th embodiment.

[0260] The 25th embodiment is an embodiment that can be applied in combination with any of the 15th to 24th embodiments (FIGS. 29 to 40) having a configuration in which the first substrate 70 and the second substrate 401 are laminated.

[0261] For comparison, refer to FIG. 40 again. The gate electrode of the amplification transistor 78 provided on the second substrate 401 of the effective pixel 31 shown in FIG. 40 is formed in the wiring layer 402 located on the lower side in the figure. The gate electrode of the amplification transistor 78 provided on the second substrate 401 of the effective pixel 31 shown in FIG. 41 is formed in the wiring layer 402 located on the upper side in the figure.

[0262] Thus, the gate electrode of the transistor provided on the second substrate 401 can be configured to be formed in the wiring layer 402 located above the transistor, or can be configured to be formed in the wiring layer 402 located below.

[0263] <Configuration regarding sharing of FD> FIG. 42 is a diagram showing a configuration regarding the sharing of FD 91. The configuration described below can be applied to any of the above-described embodiments.

[0264] For example, as described with reference to A in FIG. 4, a configuration in which one FD 91 and a diffusion region 92 configured to be in contact with the FD 91 are shared by four 2×2 effective pixels 31 can be applied to any of the above-described embodiments.

[0265] As shown in A of FIG. 42, a configuration in which FD 91 is not shared can also be applied to any of the above-described embodiments. In the planar configuration example shown in A of FIG. 42, FD 91-1 is provided in the effective pixel 31-1, FD 91-2 is provided in the effective pixel 31-2, FD 91-3 is provided in the effective pixel 31-3, and FD 91-4 is provided in the effective pixel 31-4. Each of the effective pixels 31-1 to 31-4 is configured to be surrounded by a trench 82.

[0266] Figure 42B shows another configuration example in which one FD91 is shared among four 2x2 effective pixels 31. The FD supply configuration shown in Figure 42B can also be applied to any of the embodiments described above. In the planar configuration example shown in Figure 42B, each effective pixel 31-1 to 31-4 is surrounded by a trench 82, and the FD91-5 is positioned in the center of the four effective pixels 31.

[0267] Each effective pixel 31-1 to 31-4 is provided with FD91-1 to 91-4. FD91-1 to 91-4 and FD91-5 are formed at different depths. Each of the FD91-1 to 91-4 located in each effective pixel 31 is connected to FD91-5 via wirings 93-1 to 93-4. FD91-1 is connected to FD91-5 via wiring 93-1, FD91-2 is connected to FD91-5 via wiring 93-2, FD91-3 is connected to FD91-5 via wiring 93-3, and FD91-4 is connected to FD91-5 via wiring 93-4.

[0268] The configuration of FD91 shown in Figure 42 can be applied to any of the first to twenty-fifth embodiments described above.

[0269] The first to twenty-fifth embodiments described above can also be implemented in combination of two or more of them.

[0270] <Examples of application to electronic devices> This technology is applicable to all electronic devices that use an image sensor in the image acquisition unit (photoelectric conversion unit), such as imaging devices like digital still cameras and video cameras, portable terminal devices with imaging functions, and photocopiers that use an image sensor in the image reading unit. The image sensor may be formed as a single chip, or it may be in the form of a module with imaging functions in which the imaging unit and signal processing unit or optical system are packaged together.

[0271] FIG. 43 is a block diagram showing a configuration example of an imaging device as an electronic device to which the present technology is applied. The imaging device 1000 in FIG. 43 includes an optical unit 1001 composed of a lens group and the like, an imaging element (imaging device) 1002, and a DSP (Digital Signal Processor) circuit 1003 which is a camera signal processing circuit. The imaging device 1000 also includes a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are interconnected via a bus line 1009.

[0272] The optical unit 1001 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 1002. The imaging element 1002 converts the amount of incident light imaged on the imaging surface by the optical unit 1001 into an electrical signal in pixel units and outputs it as a pixel signal.

[0273] The display unit 1005 is composed of, for example, a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays a moving image or a still image captured by the imaging element 1002. The recording unit 1006 records a moving image or a still image captured by the imaging element 1002 on a recording medium such as a hard disk or a semiconductor memory.

[0274] The operation unit 1007 issues operation commands for various functions of the imaging device 1000 under the operation by the user. The power supply unit 1008 appropriately supplies various power sources that serve as the operating power for the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007 to these supply targets.

[0275] The above-described imaging device 1 can be applied to a part of the imaging device shown in FIG. 43.

[0276] <Application Example to an Endoscopic Surgery System> The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be applied to an endoscopic surgical system.

[0277] Figure 44 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0278] Figure 44 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0279] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0280] An opening into which an objective lens is fitted is provided at the tip of the endoscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the endoscope tube by a light guide extending inside the endoscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0281] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0282] The CCU11201 consists of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU11201 receives image signals from the camera head 11102 and performs various image processing operations on these image signals, such as development processing (demosaic processing), to display the image based on those image signals.

[0283] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0284] The light source device 11203 consists of a light source such as an LED (light-emitting diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0285] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0286] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or vascular sealing. The insufflation device 11206 delivers gas into the patient's body cavity via the insufflation tube 11111 to inflate the body cavity of the patient 11132 for the purpose of securing a field of view by the endoscope 11100 and securing the operator's working space. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0287] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical area, can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to time-divisionally capture images corresponding to each of the RGB light sources by irradiating the observation target with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0288] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0289] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue and irradiating with narrow-band light compared to the irradiation light used during normal observation (i.e., white light), so-called narrow-band imaging is performed to image predetermined tissues such as blood vessels on the surface of mucosa with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light is irradiated onto body tissue and fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated onto the body tissue to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0290] Figure 45 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 44.

[0291] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with one another.

[0292] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0293] The imaging unit 11402 may consist of one image sensor (a so-called single-chip system) or multiple image sensors (a so-called multi-chip system). If the imaging unit 11402 is configured as a multi-chip system, for example, each image sensor may generate image signals corresponding to RGB, and these signals may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is configured as a multi-chip system, multiple lens units 11401 may be provided corresponding to each image sensor.

[0294] Furthermore, the imaging unit 11402 does not necessarily have to be located in the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0295] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0296] The communication unit 11404 consists of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0297] Furthermore, the communication unit 11404 receives control signals from the CCU 11201 to control the drive of the camera head 11102 and supplies them to the camera head control unit 11405. These control signals include information regarding imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0298] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU11201 based on the acquired image signal. In the latter case, the endoscope 11100 will be equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0299] The camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0300] The communication unit 11411 consists of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0301] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0302] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0303] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates control signals to control the driving of the camera head 11102.

[0304] Furthermore, the control unit 11413 displays the captured image showing the surgical area on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery with confidence.

[0305] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0306] In the illustrated example, communication was performed via a wired connection using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0307] <Examples of applications to mobile devices> The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0308] Figure 46 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0309] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 46, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0310] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0311] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0312] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0313] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0314] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0315] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0316] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0317] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0318] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 46, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0319] Figure 47 shows an example of the installation position of the imaging unit 12031.

[0320] In Figure 47, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0321] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0322] Figure 47 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0323] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0324] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0325] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0326] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0327] In this specification, "system" refers to an entire apparatus composed of multiple devices.

[0328] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0329] It should be noted that the embodiments of this technology are not limited to those described above, and various modifications are possible without departing from the spirit of this technology.

[0330] Furthermore, this technology can also be configured as follows. (1) Photoelectric conversion unit, At least a portion of the surface surrounding the photoelectric conversion unit is provided with an electrode through which either holes or electrons flow. Equipped with, The electrode includes an insulating film and an impurity diffusion region in which a predetermined impurity is diffused. The side wall of the insulating film on the photoelectric conversion unit side is provided with a contact that connects the photoelectric conversion unit and the impurity diffusion region. The insulating film includes a connecting region that connects the contact and the impurity diffusion region. Imaging device. (2) In the structure for reading electrons from the photoelectric conversion unit, the electrode is an electrode through which holes flow, and the impurity diffusion region is doped with an impurity that forms an n-type region. The imaging device described in (1) above. (3) In the structure for reading holes from the photoelectric conversion unit, the electrode is an electrode through which electrons flow, and the impurity diffusion region is doped with an impurity that forms a p-type region. The imaging device described in (1) above. (4) The electrode is connected to a power source that supplies a predetermined potential. The imaging device described in any of (1) to (3) above. (5) The aforementioned supply source is connected in the region where the light-shielding pixels are located. The imaging device described in (4) above. (6) The photoelectric conversion portion side of the electrode is further provided with a layer in which impurities having the same polarity as the impurity diffusion region are diffused. The imaging device described in any of (1) to (5) above. (7) The impurity diffusion region contained in the electrode includes a region in which a void or insulating material is embedded. The imaging device described in any of (1) to (6) above. (8) The photoelectric conversion portion side of the electrode is further provided with a fixed charge film having a fixed charge. The imaging device described in any of (1) to (6) above. (9) The electrodes are provided between the photoelectric conversion units. The imaging device described in any of (1) to (8) above. (10) The electrode is provided in the element isolation section. The imaging device described in any of (1) to (9) above. (11) The electrodes between the pixels further include the connection region and the contacts. The imaging device described in (10) above. (12) The electrode consists of a first electrode provided between the photoelectric conversion units and a second electrode provided in the element isolation unit. The thickness of the insulating film constituting the first electrode and the thickness of the insulating film constituting the second electrode are different. An imaging device according to any of (1) to (11) above. (13) Each pixel is provided with two of the aforementioned photoelectric conversion units. The imaging device described in any of (1) to (12) above. (14) A fixed charge film having a fixed charge is provided between the two photoelectric conversion units. The imaging device described in (13) above. (15) The electrode is located on the light incident surface side of the photoelectric conversion unit and is provided in a trench that separates the pixels. An imaging device as described in any of (1) to (14) above. (16) The aforementioned electrode functions as an FD (Floating Diffusion) electrode. An imaging device as described in any of (1) to (15) above. (17) The electrode functions as a contact connected to a supply source that supplies a predetermined potential to the photoelectric conversion unit. The imaging device described in any of (1) to (16) above. (18) A first substrate including the photoelectric conversion unit, The system further comprises a second substrate, which is laminated on the first substrate and includes a pixel transistor for processing signals from the photoelectric conversion unit. An imaging device as described in any of (1) to (17) above. (19) A first substrate including a photoelectric conversion unit, A pixel transistor for processing signals from the photoelectric conversion unit is provided, and a second substrate is stacked on the first substrate, An electrode connected to a supply source that supplies a predetermined potential to the pixel transistor, and an electrode located in the layer of the second substrate on which the pixel transistor is located. Equipped with, The electrode is an electrode through which either holes or electrons flow, It includes an insulating film and an impurity diffusion region in which a predetermined impurity is diffused. The side wall of the insulating film on the photoelectric conversion unit side is provided with a contact that connects the photoelectric conversion unit and the impurity diffusion region. The insulating film includes a connecting region that connects the contact and the impurity diffusion region. Imaging device. (20) The electrodes are also provided on at least a portion of the surface surrounding the photoelectric conversion unit. The imaging device described in (19) above. [Explanation of Symbols]

[0331] 1 Imaging device, 2 Pixel, 3 Pixel array section, 4 Vertical drive circuit, 5 Column signal processing circuit, 6 Horizontal drive circuit, 7 Output circuit, 8 Control circuit, 9 Vertical signal line, 10 Pixel drive wiring, 11 Horizontal signal line, 12 Semiconductor substrate, 13 Input / output terminals, 31 Effective pixel area, 32 Light-shielding pixel area, 70 Si substrate, 71 PD, 72 Insulating sealing film, 73 Color filter, 74 On-chip lens, 75 Wiring layer, 76 Transfer transistor, 77 Reset transistor, 78 Amplifier transistor, 79 Selection transistor, 81 Element isolation section, 82 Trench, 83 Sidewall film, 84 Impurity area, 85 Pinhole, 86 Contact, 87 Charge polarity selective electrode, 91 Light-shielding film, 93 Wiring, 101 Mask, 121 Light-shielding film, 122 Barrier metal, 123 Oxide film, 131 p-type diffusion layer, 132 Wiring, 141 Contact, 142 Wiring, 151 Transistor for conversion efficiency switching, 171 Doping layer, 172 Charge polarity selective electrode, 181 Void, 182 Charge polarity selective electrode, 201 Fixed charge film, 202 Silicon nitride film, 203 Alumina film, 204 Charge polarity selective electrode, 211 Trench, 221 Charge polarity selective electrode, 222 Charge polarity selective electrode, 223 Sidewall film, 224 Impurity region, 225 Pinhole, 226 Contact, 228 Impurity region, 231 Polysilicon electrode, 232 Sidewall film, 233 Impurity region, 251 Trench, 252 Oxide film, 253 Fixed charge film, 301 Insulating layer, 323 Pixel transistor, 331 Contact, 401 Second substrate, 402 Wiring layer, 411, 412, 413 Wiring, 421 Diffusion layer, 422 Diffusion layer

Claims

1. Photoelectric conversion unit, At least a portion of the surface surrounding the photoelectric conversion unit is provided with an electrode through which either holes or electrons flow. Equipped with, The electrode includes an insulating film and an impurity diffusion region in which a predetermined impurity is diffused. The side wall of the insulating film on the photoelectric conversion unit side is provided with a contact that connects the photoelectric conversion unit and the impurity diffusion region. The insulating film includes a connecting region that connects the contact and the impurity diffusion region. Imaging device.

2. In the structure for reading electrons from the photoelectric conversion unit, the electrode is an electrode through which holes flow, and the impurity diffusion region is doped with an impurity that forms an n-type region. The imaging apparatus according to claim 1.

3. In the structure for reading holes from the photoelectric conversion unit, the electrode is an electrode through which electrons flow, and the impurity diffusion region is doped with an impurity that forms a p-type region. The imaging apparatus according to claim 1.

4. The electrode is connected to a power source that supplies a predetermined potential. The imaging apparatus according to claim 1.

5. The aforementioned supply source is connected in the region where the light-shielding pixels are located. The imaging apparatus according to claim 4.

6. The photoelectric conversion portion side of the electrode is further provided with a layer in which impurities having the same polarity as the impurity diffusion region are diffused. The imaging apparatus according to claim 1.

7. The impurity diffusion region contained in the electrode includes a region in which a void or insulating material is embedded. The imaging apparatus according to claim 1.

8. The photoelectric conversion portion side of the electrode is further provided with a fixed charge film having a fixed charge. The imaging apparatus according to claim 1.

9. The electrodes are provided between the photoelectric conversion units. The imaging apparatus according to claim 1.

10. The electrode is provided in the element isolation section. The imaging apparatus according to claim 1.

11. The electrodes between the pixels further include the connection region and the contacts. The imaging apparatus according to claim 10.

12. The electrode consists of a first electrode provided between the photoelectric conversion units and a second electrode provided in the element isolation unit. The thickness of the insulating film constituting the first electrode and the thickness of the insulating film constituting the second electrode are different. The imaging apparatus according to claim 1.

13. Each pixel is provided with two of the aforementioned photoelectric conversion units. The imaging apparatus according to claim 1.

14. A fixed charge film having a fixed charge is provided between the two photoelectric conversion units. The imaging device according to claim 13.

15. The electrode is located on the light incident surface side of the photoelectric conversion unit and is provided in a trench that separates the pixels. The imaging apparatus according to claim 1.

16. The aforementioned electrode functions as a floating diffusion (FD) electrode. The imaging apparatus according to claim 1.

17. The electrode functions as a contact connected to a supply source that supplies a predetermined potential to the photoelectric conversion unit. The imaging apparatus according to claim 1.

18. A first substrate including the photoelectric conversion unit, The system further comprises a second substrate, which is laminated on the first substrate and is provided with pixel transistors for processing signals from the photoelectric conversion unit. The imaging apparatus according to claim 1.

19. A first substrate including a photoelectric conversion unit, A pixel transistor for processing signals from the photoelectric conversion unit is provided, and a second substrate is stacked on the first substrate, An electrode connected to a supply source that supplies a predetermined potential to the pixel transistor, and an electrode located in the layer of the second substrate on which the pixel transistor is located. Equipped with, The electrode is an electrode through which either holes or electrons flow, It includes an insulating film and an impurity diffusion region in which a predetermined impurity is diffused. The side wall of the insulating film on the photoelectric conversion unit side is provided with a contact that connects the photoelectric conversion unit and the impurity diffusion region. The insulating film includes a connecting region that connects the contact and the impurity diffusion region. Imaging device.

20. The electrodes are also provided on at least a portion of the surface surrounding the photoelectric conversion unit. The imaging device according to claim 19.

Images