Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a silicon substrate, a nitride buffer composite layer, an active layer and a silicon barrier composite layer. The nitride buffer composite layer is arranged above the silicon substrate, the active layer is arranged above the nitride buffer composite layer, and the silicon blocking composite layer is clamped in the nitride buffer composite layer and substantially blocks diffusion of a silicon impurity from the silicon substrate so as to reduce leakage current.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, particularly to a semiconductor structure for reducing the diffusion of silicon impurities in a silicon substrate. Background Art

[0002] In high electron mobility transistors (HEMTs) and gallium nitride on silicon (GaN-on-Silicon) devices, the diffusion of silicon impurities in the silicon substrate may have the following effects on device performance: (1) Lattice defects: If silicon impurities in the silicon substrate diffuse into the gallium nitride layer, it may lead to the generation of lattice defects, which will increase the leakage current, reduce the breakdown voltage of the device, and affect the reliability of the device; (2) Reduction of electron mobility: Impurity diffusion will cause an increase in carrier scattering, thereby reducing the mobility of electrons in the channel and affecting the high-frequency performance and output power of HEMT devices; (3) Formation of parasitic conductive layers: The diffusion of silicon impurities may lead to the formation of parasitic conductive layers in the gallium nitride layer or buffer layer, which will increase the leakage current and reduce the efficiency of the device; and (4) Gate voltage drift: The diffusion of silicon impurities may cause a voltage drift between the gate and the source, affecting the control ability of the gate and thus causing instability of the device. Therefore, how to reduce the adverse effects caused by the diffusion of silicon impurities in the silicon substrate on the device is an urgent problem to be solved at present. Summary of the Invention

[0003] The main object of the present invention is to provide an innovative semiconductor structure and its manufacturing method, by reducing the diffusion of silicon impurities volatilized from the silicon substrate to the upper insulating high-impedance epitaxial layer, to improve the breakdown voltage of the device and reduce the leakage current path.

[0004] To achieve the above object, the present invention provides a semiconductor structure, comprising a silicon substrate, a nitride buffer composite layer, an active layer, and a silicon blocking composite layer. The nitride buffer composite layer is disposed above the silicon substrate, the active layer is disposed above the nitride buffer composite layer, and the silicon blocking composite layer is sandwiched in the nitride buffer composite layer to substantially block the diffusion of a silicon impurity from the silicon substrate to reduce the leakage current.

[0005] In an embodiment of the semiconductor structure of the present invention, the silicon blocking composite layer comprises a plurality of aluminum-containing nitride layers, each aluminum-containing nitride layer has a carbon doping concentration, and the carbon doping concentration of each aluminum-containing nitride layer is higher closer to the active layer.

[0006] In an embodiment of the semiconductor structure of the present invention, each aluminum-containing nitride layer is a gallium aluminum nitride layer (Al x Ga (1-x) N, 0 < x < 1), an indium aluminum nitride layer (Alx In (1-x) N, where 0 < x < 1), and an aluminum gallium indium nitride layer (Al x Ga y In (1-x-y) N, where 0 < x < 1 and 0 < x + y < 1).

[0007] In an embodiment of the semiconductor structure of the present invention, each aluminum nitride-containing layer has an aluminum content, and the aluminum content of each aluminum nitride-containing layer is higher the closer it is to the active layer.

[0008] In an embodiment of the semiconductor structure of the present invention, each aluminum nitride-containing layer has an aluminum content, and the aluminum content of each aluminum nitride-containing layer is lower the closer it is to the active layer.

[0009] In an embodiment of the semiconductor structure of the present invention, the carbon doping concentration of each aluminum nitride-containing layer is higher the closer it is to the active layer, starting from 1E17 - 1E19 / cm 3 upward.

[0010] In an embodiment of the semiconductor structure of the present invention, the thickness of each aluminum nitride-containing layer is less than 500 nanometers (nm).

[0011] In an embodiment of the semiconductor structure of the present invention, the silicon blocking composite layer comprises a plurality of aluminum nitride-containing layers, each aluminum nitride-containing layer has an iron doping concentration, and the iron doping concentration of each aluminum nitride-containing layer is higher the closer it is to the active layer.

[0012] In an embodiment of the semiconductor structure of the present invention, the nitride buffer composite layer has a first aluminum nitride buffer layer and a second aluminum nitride buffer layer, wherein the first aluminum nitride buffer layer is disposed above the silicon substrate.

[0013] In an embodiment of the semiconductor structure of the present invention, the active layer above the nitride buffer composite layer sequentially comprises a carbon-doped gallium nitride layer, a gallium nitride channel layer, an aluminum gallium nitride buffer layer, and an undoped gallium nitride cladding layer.

[0014] To achieve the above object, the present invention provides a method for manufacturing a semiconductor structure, which comprises providing a silicon substrate; providing a nitride buffer composite layer disposed above the silicon substrate; providing an active layer disposed above the nitride buffer composite layer; and providing a silicon blocking composite layer sandwiched in the nitride buffer composite layer to substantially block the diffusion of a silicon impurity from the silicon substrate to reduce leakage current.

[0015] In an embodiment of the method for manufacturing the semiconductor structure of the present invention, the step of providing a silicon blocking composite layer is to provide a plurality of aluminum nitride-containing layers, perform carbon doping on each aluminum nitride-containing layer, and the carbon doping concentration of each aluminum nitride-containing layer is higher the closer it is to the active layer.

[0016] In one embodiment of the manufacturing method of the semiconductor structure of the present invention, carbon doping is performed by doping, natural doping in a cavity, or diffusion using one of methane (CH4), ethylene (C2H4), pentane (C5H 12 ) as the doping gas.

[0017] In one embodiment of the manufacturing method of the semiconductor structure of the present invention, the step of forming each aluminum nitride-containing layer is made using materials including trimethylgallium (TMGa), triethylgallium (TEGa), trimethylaluminum (TMAl), trimethylindium (TMIn), and ammonia (NH3) by metalorganic vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0018] In one embodiment of the manufacturing method of the semiconductor structure of the present invention, each aluminum nitride-containing layer is an aluminum gallium nitride layer (Al x Ga (1-x) N, 0 < x < 1), an aluminum indium nitride layer (Al x In (1-x) N, 0 < x < 1), or an aluminum gallium indium nitride layer (Al x Ga y In (1-x-y) N, 0 < x < 1, 0 < y < 1, x + y < 1).

[0019] In one embodiment of the manufacturing method of the semiconductor structure of the present invention, the step of providing each aluminum nitride-containing layer is a step of providing an aluminum content of each aluminum nitride-containing layer that is higher the closer it is to the active layer.

[0020] In one embodiment of the manufacturing method of the semiconductor structure of the present invention, the step of providing each aluminum nitride-containing layer is a step of providing an aluminum content of each aluminum nitride-containing layer that is lower the closer it is to the active layer.

[0021] In one embodiment of the manufacturing method of the semiconductor structure of the present invention, the step of providing each aluminum nitride-containing layer is a step of providing a carbon doping concentration of each aluminum nitride-containing layer that is higher the closer it is to the active layer starting from 1E17 - 1E19 / cm 3 .

[0022] In one embodiment of the manufacturing method of the semiconductor structure of the present invention, the step of providing a silicon blocking composite layer is a step of providing a plurality of aluminum nitride-containing layers, performing iron doping on each aluminum nitride-containing layer, and having an iron doping concentration of each aluminum nitride-containing layer that is higher the closer it is to the active layer.

[0023] In one embodiment of the manufacturing method of the semiconductor structure of the present invention, the step of providing a nitride buffer composite layer is a step of providing a first aluminum nitride buffer layer and a second aluminum nitride buffer layer, where the first aluminum nitride buffer layer is disposed above the silicon substrate.

[0024] Other objects of the present invention, as well as the technical means and implementation methods of the present invention, will be understood by those skilled in the art upon referring to the accompanying drawings and the embodiments described below. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a semiconductor structure in one embodiment of the present invention;

[0026] Figure 2 For the present invention Figure 1 A partially enlarged schematic diagram of the aluminum nitride layer; and

[0027] Figure 3 This is a schematic diagram of the manufacturing process steps of a semiconductor structure in one embodiment of the present invention.

[0028] Explanation of reference numerals in the attached figures

[0029] 10 Silicon substrate

[0030] 20 Nitride Buffer Composite Layer

[0031] 22 First aluminum nitride buffer layer

[0032] 24 Second aluminum nitride buffer layer

[0033] 30 Silicon barrier composite layer

[0034] 301 Aluminum Nitride Layer

[0035] 302 aluminum nitride layer

[0036] 303 aluminum nitride layer

[0037] 30 n-1 Aluminum nitride layer

[0038] 30 n Aluminum nitride layer

[0039] 40 Active Layer

[0040] 42 Carbon-doped gallium nitride layer

[0041] 44 Gallium nitride channel layer

[0042] 46. ​​AlGaN Buffer Layer

[0043] 48 Undoped gallium nitride coating. Detailed Implementation

[0044] The following embodiments will explain the content of this invention. These embodiments are not intended to limit the implementation of this invention to any specific environment, application, or special method described in the embodiments. Therefore, the descriptions of the embodiments are merely illustrative of the invention and not intended to limit it. It should be noted that in the following embodiments and drawings, elements not directly related to this invention have been omitted and are not shown, and the dimensional relationships between the elements in the drawings are for ease of understanding only and are not intended to limit the actual scale.

[0045] Please see Figure 1 This invention illustrates a semiconductor structure and its manufacturing method in one embodiment, particularly a high electron mobility transistor or a silicon-based nitride light-emitting diode and its manufacturing method. The following description uses a high electron mobility transistor as an example. First, a silicon substrate 10 is provided. Then, a nitride buffer composite layer 20 is formed on the silicon substrate 10, and a silicon barrier composite layer 30 is sandwiched within the nitride buffer composite layer 20. In this embodiment, the nitride buffer composite layer 20 includes a first aluminum nitride buffer layer 22 and a second aluminum nitride buffer layer 24, with the first aluminum nitride buffer layer 22 disposed above the silicon substrate 10. Finally, an active layer 40 of the device is formed on the nitride buffer composite layer 20. Specifically, the active layer 40 sequentially includes a carbon-doped gallium nitride layer 42, a gallium nitride channel layer 44, an aluminum gallium nitride buffer layer 46, and an undoped gallium nitride coating layer 48 above the second aluminum nitride buffer layer 24.

[0046] Please refer to both together. Figure 1 and Figure 2 ,in Figure 2 show Figure 1 A magnified schematic diagram of the silicon barrier composite layer. It should be noted that traditional high electron mobility transistor devices only have an aluminum nitride buffer layer. This aluminum nitride buffer layer cannot overcome the lattice defects and tensile stress of the silicon substrate, making it difficult to connect lattice differences in subsequent epitaxial structures, thus leading to problems such as poor two-dimensional electron gas characteristics of the device. In view of this, the present invention specifically sandwiches a silicon barrier compound semiconductor layer in addition to the aluminum nitride buffer layer to increase compressive strain and improve the diffusion degree of silicon impurities from the silicon substrate, reducing leakage paths.

[0047] like Figure 2 As shown, the silicon barrier composite layer 30 in the first aluminum nitride buffer layer 22 and the second aluminum nitride buffer layer 24 includes multiple aluminum nitride-containing layers 301, 302, 303...30 n-1 30 n, wherein each aluminum nitride-containing layer can be alternately stacked by thin film deposition techniques. For example, the available thin film deposition techniques include Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE), etc. Specifically, the aforementioned thin film deposition techniques can use materials such as trimethylgallium (TMGa), triethylgallium (TEGa), trimethylaluminum (TMAl), trimethylindium (TMIn), and ammonia (NH3) to form multiple aluminum nitride-containing layers 301, 302, 303... 30 n-1 , 30 n . For example, each aluminum nitride-containing layer 301, 302, 303... 30 n-1 , 30 n can be an aluminum gallium nitride layer (Al x Ga (1-x) N, 0 < x < 1), an aluminum indium nitride layer (Al x In (1-x) N, 0 < x < 1) layer, or an aluminum gallium indium nitride layer (Al x Ga y In (1-x-y) N, 0 < x < 1, 0 < x + y < 1), and they are alternately stacked with one of the ternary or quaternary compound semiconductor layers. The aluminum content of each layer is between 0 and 100%, and the total thickness of the silicon blocking composite layer 30 is less than 3 micrometers (μm). The number of layers of each aluminum nitride-containing layer can be 150 layers, and the thickness of each layer is less than 500 nanometers (nm). Preferably, the thickness of each layer can be between 50 and 300 nanometers (nm). In particular, when the silicon blocking composite layer 30 uses aluminum gallium nitride, aluminum indium nitride, or aluminum gallium indium nitride as the material for each layer, the aluminum content in the aluminum-containing compounds between each layer can be adjusted to ensure lattice matching between each epitaxial layer and adjust the stress, which is one of the keys to overcoming the excessive tensile stress in traditional HEMT devices.

[0048] Specifically, there are two methods to adjust the different aluminum contents in each aluminum nitride-containing layer 301, 302, 303... 30 n-1 , 30 n . One of them can be to sequentially increase the aluminum content of each layer from bottom to top, making it higher the closer it is to the active layer 40, or conversely, to sequentially decrease the aluminum content of each layer from bottom to top, making it lower the closer it is to the active layer 40. The above two methods usually take sequentially decreasing the aluminum content of each layer as the preferred implementation scheme. That is, the aluminum content of the first aluminum nitride-containing layer 301 is greater than the aluminum content of the second aluminum nitride-containing layer 302, and the aluminum content of the second aluminum nitride-containing layer 302 is greater than the aluminum content of the third aluminum nitride-containing layer 303. And so on, the aluminum content of the (n - 1)-th aluminum nitride-containing layer 30 n-1The aluminum content is greater than that of the nth aluminum nitride layer by 30. n Aluminum content.

[0049] On the other hand, conversely, if the aluminum content of each layer in the silicon barrier composite layer 30 is increased sequentially, the aluminum content of the silicon barrier layer closer to the active layer 40 is higher. While a high-aluminum-content buffer layer can introduce compressive stress to compensate for the tensile stress caused by the thermal expansion difference between the active layer and the silicon substrate, thereby reducing the total stress in the active layer, the problem of wafer warping due to thermal expansion caused by high aluminum content needs further overcoming. One way to overcome this is to add a supporting substrate, such as a ceramic substrate or a QST (Quartz Substrate Technology) substrate, under the silicon substrate 10 to increase the strength of the silicon substrate 10 and reduce wafer warping due to thermal expansion. In other words, while strengthening the silicon substrate 10, sequentially increasing the aluminum content of each layer in the silicon barrier composite layer 30, making it higher closer to the active layer 40, is also a feasible solution to adjust stress and overcome the excessive tensile stress within traditional HEMT devices.

[0050] In addition, each aluminum nitride layer 301, 302, 303…30 n-1 30 n The carbon doping concentration is 1, with higher concentrations closer to the active layer. This is used to reduce the diffusion of silicon impurities volatilized from the silicon substrate to the upper insulating high-resistivity epitaxial layer, increasing its insulation, blocking leakage paths, and improving the device breakdown voltage. Specifically, methane (CH4), ethylene (C2H4), and pentane (C5H4) can be used for carbon doping. 12 One method is doping with a doping gas, natural doping within a cavity, or diffusion. The carbon doping concentration of the first aluminum nitride layer 301 is 1E17–1E19 / cm³. 3 The carbon doping concentration of the second aluminum nitride layer 302 is 1E17~1E20 / cm³. 3 The carbon doping concentration of the third aluminum nitride layer 303 is 1E17~1E21 / cm³. 3 The carbon doping concentration of the fourth aluminum nitride layer is 1E17~1E22 / cm³. 3 It should be noted that in each aluminum nitride layer 301, 302, 303…30… n-1 30 n In addition to carbon, iron can also be doped into it. When the iron doping concentration of each aluminum nitride layer is closer to that of the active layer, it can also block the diffusion of silicon impurities in the silicon substrate, increase its insulation, improve the device breakdown voltage, and reduce leakage current.

[0051] Please refer to Figure 3This diagram illustrates the process steps of the semiconductor structure of the present invention. First, in step S01, a silicon substrate is provided. Second, in step S02, a nitride buffer composite layer is provided and disposed above the silicon substrate. In step S03, an active layer is provided and disposed above the nitride buffer composite layer. In step S04, a silicon barrier composite layer is provided, sandwiched within the nitride buffer composite layer, which substantially blocks the diffusion of silicon impurities from the silicon substrate to reduce leakage current. The composition and relationship of each component in each process step can be referred to the foregoing description and will not be repeated here.

[0052] The above embodiments are merely illustrative of implementation schemes of the present invention and to explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalent arrangements that can be easily made by those skilled in the art are within the scope of the present invention, and the scope of protection of the present invention should be determined by the claims.

Claims

1. A semiconductor structure, comprising: a silicon substrate; a nitride buffer composite layer disposed above the silicon substrate; an active layer disposed above the nitride buffer composite layer; and a silicon barrier composite layer interposed in the nitride buffer composite layer substantially blocking diffusion of a silicon impurity from the silicon substrate to reduce leakage current.

2. The semiconductor structure of claim 1, wherein the silicon barrier composite layer comprises a plurality of aluminum-containing nitride layers, each of the aluminum-containing nitride layers having a carbon doping concentration, and the carbon doping concentration of each of the aluminum-containing nitride layers is higher closer to the active layer.

3. The semiconductor structure according to claim 2, wherein each of the aluminum nitride-containing layers is one of an aluminum gallium nitride layer (Al x Ga (1-x) N, 0 < x < 1), an aluminum indium nitride layer (Al x In (1-x) N, 0 < x < 1), and an aluminum gallium indium nitride layer (Al x Ga y In (1-x-y) N, 0 < x < 1, 0 < x + y < 1).

4. The semiconductor structure of claim 2, wherein each of the aluminum-containing nitride layers has an aluminum content, and the aluminum content of each of the aluminum-containing nitride layers is higher closer to the active layer.

5. The semiconductor structure of claim 2, wherein each of the aluminum-containing nitride layers has an aluminum content, and the aluminum content of each of the aluminum-containing nitride layers is lower closer to the active layer.

6. The semiconductor structure of claim 2, wherein the carbon doping concentration of each of the aluminum-containing nitride layers is from 1E17 to 1E19 / cm 3 increases closer to the active layer.

7. The semiconductor structure of claim 2, wherein each of the aluminum-containing nitride layers has a thickness less than 500 nanometers.

8. The semiconductor structure of claim 1, wherein the silicon barrier composite layer comprises a plurality of aluminum-containing nitride layers, each of the aluminum-containing nitride layers having an iron doping concentration, and the iron doping concentration of each of the aluminum-containing nitride layers is higher closer to the active layer.

9. The semiconductor structure of claim 1, wherein the nitride buffer composite layer has a first aluminum nitride buffer layer disposed above the silicon substrate and a second aluminum nitride buffer layer.

10. The semiconductor structure of claim 1, wherein the active layer above the nitride buffer composite layer comprises, in order, a carbon-doped gallium nitride layer, a gallium nitride channel layer, an aluminum gallium nitride buffer layer, and an undoped gallium nitride capping layer.

11. A method of fabricating a semiconductor structure, comprising: providing a silicon substrate; providing a nitride buffer composite layer disposed above the silicon substrate; providing an active layer disposed above the nitride buffer composite layer; and providing a silicon barrier composite layer interposed in the nitride buffer composite layer substantially blocking diffusion of a silicon impurity from the silicon substrate to reduce leakage current.

12. The method of claim 11, wherein the step of providing a silicon barrier composite layer is providing a plurality of aluminum-containing nitride layers and carbon doping each of the aluminum-containing nitride layers, and the carbon doping concentration of each of the aluminum-containing nitride layers is higher closer to the active layer.

13. The method of claim 12, wherein the carbon doping is doping with one of methane, ethylene, and pentane as a doping gas, cavity natural doping, or diffusion.

14. The method of claim 12, wherein the step of forming each of the aluminum-containing nitride layers is using materials including trimethyl gallium, triethyl gallium, trimethyl aluminum, trimethyl indium, and ammonia gas for metal organic vapor deposition or molecular beam epitaxy.

15. The manufacturing method according to claim 12, wherein each of the aluminum nitride-containing layers is a gallium aluminum nitride layer (Al x Ga (1-x) N, 0 < x < 1), an indium aluminum nitride layer (Al x In (1-x) N, 0 < x < 1), and a gallium indium aluminum nitride layer (Al x Ga y In (1-x-y) N, 0 < x < 1, 0 < y < 1, x + y < 1).

16. The method of claim 12, wherein the step of providing each of the aluminum-containing nitride layers is providing an aluminum content of each of the aluminum-containing nitride layers that is higher closer to the active layer.

17. The manufacturing method of claim 12, wherein the step of providing each of the aluminum-containing nitride layers is a step of providing each of the aluminum-containing nitride layers with an aluminum content that is lower the closer to the active layer.

18. The manufacturing method of claim 12, wherein the step of providing each of the aluminum-containing nitride layers is to provide the carbon-doped concentration of each of the aluminum-containing nitride layers from 1E17 to 1E19 / cm 3 the step of providing the active layer is to provide the active layer with a higher concentration of carbon atoms as the active layer is closer to the substrate.

19. The manufacturing method of claim 11, wherein the step of providing a silicon-blocking composite layer is a step of providing a plurality of aluminum-containing nitride layers, and each of the aluminum-containing nitride layers is doped with iron, and the iron doping concentration of each of the aluminum-containing nitride layers is higher the closer to the active layer.

20. The manufacturing method of claim 11, wherein the step of providing a nitride-buffer composite layer is a step of providing a first aluminum nitride buffer layer and a second aluminum nitride buffer layer, wherein the first aluminum nitride buffer layer is disposed above the silicon substrate.

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