Display substrate, display panel and display device

Abstract

The utility model relates to a display substrate, a display panel and a display device. The display substrate comprises an interlayer dielectric layer located on one side of a substrate and a plurality of data lines, and the data lines are arranged on the side, away from the substrate, of the interlayer dielectric layer and located in a display area; the multiple first fan-out lines are arranged on the side, away from the substrate, of the interlayer dielectric layer and located in the fan-out area, and the first fan-out lines are electrically connected with the data lines; the planarization layer is located on the side, away from the substrate, of the layer where the data lines are located, and a part of the planarization layer makes contact with the interlayer dielectric layer; wherein the interlayer dielectric layer is provided with a plurality of grooves, at least parts of the first fan-out lines are located in the grooves, and the thickness of the first fan-out lines is different from the depth of the grooves; and / or the display substrate further comprises a protection layer located on the side, away from the substrate, of the first fan-out line, one part of the protection layer makes contact with the interlayer dielectric layer, and the adhesion between the protection layer and the interlayer dielectric layer is larger than the adhesion between the planarization layer and the interlayer dielectric layer.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a display substrate, a display panel, and a display device. Background Technology

[0002] In the field of display technology, liquid crystal displays (LCDs) have become a major research topic in display technology in recent years due to their advantages such as low voltage operation, no radiation scattering, light weight and small size. They have also been widely used in display devices such as LCD TVs, mobile phones, personal digital assistants, digital cameras and computer screens. Summary of the Invention

[0003] This disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a display substrate, a display panel, and a display device.

[0004] To achieve the above objectives, this disclosure provides a display substrate having a display area, a bonding area located on one side of the display area, and a fan-out area located between the display area and the bonding area, the display substrate comprising:

[0005] Substrate;

[0006] An interlayer dielectric layer and multiple data lines are located on one side of the substrate. The data lines are disposed on the side of the interlayer dielectric layer away from the substrate and are located in the display area.

[0007] Multiple first fan-out lines are disposed on the side of the interlayer dielectric layer away from the substrate and located in the fan-out region; the first fan-out lines are electrically connected to the data lines.

[0008] A planarization layer is located on the side of the layer containing the first fan-out line that is away from the substrate, and a portion of the planarization layer is in contact with the interlayer dielectric layer.

[0009] The interlayer dielectric layer has multiple grooves, at least a portion of the first fan-out line is located in the grooves, and the thickness of the first fan-out line is different from the depth of the grooves.

[0010] And / or, the display substrate further includes a protective layer located on the side of the first fan-out line away from the substrate, a portion of the protective layer being in contact with the interlayer dielectric layer, and the adhesion between the protective layer and the interlayer dielectric layer being greater than the adhesion between the planarization layer and the interlayer dielectric layer.

[0011] In some embodiments, the display substrate further includes a protective layer;

[0012] The planarization layer has at least one first opening, the first opening exposing at least a portion of the first fan-out line and a portion of the interlayer dielectric layer. The protective layer includes a first protective portion located within the first opening. A portion of the first protective portion is disposed in contact with the surface of the interlayer dielectric layer away from the substrate. Another portion of the first protective portion is located on the side of the first fan-out line away from the substrate and is disposed in contact with the first fan-out line.

[0013] In some embodiments, the protective layer further includes a second protective portion located on the side of the planarization layer away from the substrate.

[0014] In some embodiments, there are multiple first openings, the multiple first openings are arranged along a first direction, and the first openings extend along a second direction, the second direction intersecting the first direction;

[0015] Wherein, the second direction is the same as the extension direction of either the first fan-out line or the data line, or the display substrate further includes a gate line located in the display area, the gate line being intersected with the data line, and the second direction being the same as the extension direction of the gate line.

[0016] In some embodiments, the display substrate further includes a passivation layer located on the side of the planarization layer away from the substrate.

[0017] The protective layer and the passivation layer are disposed in the same layer and are made of the same material.

[0018] In some embodiments, the protective layer and the passivation layer are connected as a single structure.

[0019] In some embodiments, the display substrate includes a protective layer located between the planarization layer and the layer containing the first fan-out line.

[0020] In some embodiments, the protective layer includes a plurality of spaced-apart third protective portions, the third protective portions having the same extension direction as the first fan-out line, and the third protective portions covering at least a portion of the first fan-out line.

[0021] In some embodiments, at least two third protective parts are connected as a single structure.

[0022] In some embodiments, the fan-out area includes a plurality of first regions and second regions arranged along a third direction, the first regions being located on opposite sides of the second regions along the third direction, the third direction intersecting the arrangement direction of the fan-out area and the binding area, and at least the first region being provided with the first fan-out line.

[0023] In some embodiments, the fan-out region includes a first region and a second region arranged along a third direction, the first fan-out line is located in the first region, the display substrate further includes a second fan-out line located in the second region, and the distribution density of the first fan-out line in the first region is greater than the distribution density of the second fan-out line in the second region.

[0024] In some embodiments, both the interlayer dielectric layer and the protective layer are made of inorganic materials.

[0025] This disclosure also provides a display panel, including a display substrate as described in any of the above-described embodiments.

[0026] In some embodiments, the display panel further includes:

[0027] The cell substrate is disposed opposite to the display substrate;

[0028] The sealing adhesive is located between the display substrate and the cell substrate. The orthographic projection of the sealing adhesive on the substrate surrounds the display area and overlaps with the orthographic projection of the first fan-out line on the substrate.

[0029] In some embodiments, the display substrate includes a protective layer, the planarization layer having at least one first opening, and a portion of the sealant being located within the first opening and in contact with the surface of the protective layer away from the substrate.

[0030] This disclosure also provides a display device, including a display panel as described in any of the above-described embodiments. Attached Figure Description

[0031] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0032] Figure 1 These are cross-sectional structural schematic diagrams of the display device in some embodiments;

[0033] Figure 2 yes Figure 1 A schematic diagram of the planar structure of the central display panel;

[0034] Figure 3 yes Figure 2 A cross-sectional view of the display panel is shown.

[0035] Figure 4 This is a cross-sectional structural diagram of the display panel in some other embodiments;

[0036] Figure 5 This is a cross-sectional structural diagram of the display panel in some other embodiments;

[0037] Figure 6 This is a schematic cross-sectional view of the display panel in some embodiments of this disclosure;

[0038] Figure 7 This is a schematic cross-sectional view of the display panel in some embodiments of this disclosure;

[0039] Figure 8 This is a schematic cross-sectional view of the display panel in some embodiments of this disclosure;

[0040] Figure 9 This is a cross-sectional structural schematic diagram of the display substrate in some other embodiments of this disclosure;

[0041] Figure 10 This is a cross-sectional structural schematic diagram of the display substrate in some other embodiments of this disclosure;

[0042] Figure 11 This is a cross-sectional structural schematic diagram of the display substrate in some other embodiments of this disclosure;

[0043] Figure 12 This is a cross-sectional structural schematic diagram of the display substrate in some other embodiments of this disclosure;

[0044] Figure 13 This is a schematic diagram of the planar structure of the display substrate in some other embodiments of this disclosure;

[0045] Figure 14A This is a schematic diagram of the planar structure of the fan-out area in some embodiments of this disclosure;

[0046] Figure 14B and Figure 14C They are Figure 14A A schematic diagram of the planar structure of each single-layer membrane layer in the middle;

[0047] Figure 15A This is a schematic diagram of the planar structure of the fan-out region in some other embodiments of this disclosure;

[0048] Figure 15B yes Figure 15A Schematic diagram of the planar structure of the intermediate planarization layer;

[0049] Figure 16A This is a schematic diagram of the planar structure of the fan-out region in some other embodiments of this disclosure;

[0050] Figure 16B yes Figure 16A A schematic diagram of the planar structure of the planarization layer. Detailed Implementation

[0051] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0052] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0053] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0054] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0055] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0056] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and areas is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the areas shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0057] With the continuous development of display technology, the requirements for the drop resistance and reliability of display devices are becoming increasingly stringent. During a drop, due to the violent impact, the film layers contained within the display device may slip or be damaged, rendering the display device unusable.

[0058] Figure 1 These are cross-sectional structural schematic diagrams of the display device in some embodiments.

[0059] like Figure 1 As shown, the display device includes a housing KT, a backlight module BLM, and a liquid crystal display panel. The housing forms a receiving cavity, and the backlight module and the liquid crystal display panel are located within the receiving cavity. The backlight module is located on the backlight side of the liquid crystal display panel, and the backlight module BLM may include, for example, a backlight source and a light guide plate for providing a light source for the display panel.

[0060] like Figure 1 As shown, a liquid crystal display panel generally includes a display substrate (TFT), a cell substrate (CF), and a liquid crystal layer and sealant located between the TFT and the cell. The liquid crystal layer and sealant are not... Figure 1 As shown in the diagram, the sealant seals the liquid crystal layer between the display substrate TFT and the cell substrate CF.

[0061] like Figure 1 As shown, the liquid crystal display panel also includes a first polarizer POL1 located on the side of the display substrate TFT away from the counter substrate CF, a second polarizer POL2 located on the side of the counter substrate CF away from the display substrate TFT, and a cover plate CG located on the side of the second polarizer POL2 away from the counter substrate CF. The cover plate CG and the second polarizer POL2 are bonded together by an optical adhesive layer OCA.

[0062] The display substrate TFT has multiple sub-pixels arranged in an array. Each sub-pixel includes a pixel electrode, and a common electrode is provided on the cell substrate CF. Under the voltage applied between the pixel electrode and the common electrode, the liquid crystal molecules in the liquid crystal layer LCL can be deflected. Furthermore, the liquid crystal display substrate TFT also needs to be provided with a pixel driving circuit electrically connected to the pixel electrode to specifically control the deflection of the liquid crystal molecules between the pixel electrode and the common electrode.

[0063] With the development of full-screen technology, in order to achieve a higher screen ratio, technologies such as COF (chip on film), COP (chip on panel), and COG (chip on glass) are currently mainly used to manufacture TFT liquid crystal display substrates.

[0064] Figure 1 The liquid crystal display panel shown uses a chip-on-film capacitor (COF) to drive the sub-pixels in the TFT of the display substrate. The COF can be electrically connected to the TFT of the display substrate via a flexible printed circuit (FPC).

[0065] Figure 2 yes Figure 1 A schematic diagram of the planar structure of the display panel. Figure 3 yes Figure 2 The diagram shows a cross-sectional structure of the display panel, specifically along... Figure 2 A schematic diagram of the cross-sectional structure of the cutting line XX'.

[0066] like Figure 2 As shown, the display panel has a display area AA. It should be understood that the display substrate TFT also has a corresponding display area AA.

[0067] The display area AA is provided with multiple gate lines and multiple data lines. These gate lines and data lines intersect to define multiple pixel areas. Each pixel area contains sub-pixels, which include pixel electrodes and driving elements electrically connected to the pixel electrodes. The driving elements can be, for example, thin-film transistors (TFTs). The TFTs are electrically connected to both the gate lines and data lines. The gate lines can provide scan drive signals to the transistors, controlling their on / off state. The data lines can control the pixel electrodes through the TFTs; for example, when the TFTs are on, the data lines can provide data drive signals to the pixel electrodes.

[0068] Specifically, the display substrate TFT also has a non-display area surrounding the display area AA. In one example, the non-display area may be provided with a gate driving circuit, such as a GOA (Gate Driver on Array) driving circuit, with the gate lines electrically connected to the gate driving circuit, which can provide scan driving signals to the gate lines.

[0069] In one example, such as Figure 2As shown, the non-display area includes a bonding area PA1 located on at least one side of the display area AA, and a fan-out area FA located between the bonding area PA1 and the display area AA. The bonding area PA1 is provided with multiple bonding pads, and the fan-out area FA is provided with multiple fan-out lines SD.

[0070] One end of the fan-out SD card is electrically connected to the data cable, and the other end is electrically connected to the bonding pad. The bonding pad can be electrically connected to one end of the flexible circuit board, and the other end of the flexible circuit board is electrically connected to the flip-chip film.

[0071] During the process of the display device falling, such as Figure 1 As shown, the forces transmitted from the housing KT to the cover plate CG are F1 and F4. F1 points towards the light-emitting side of the display device, and F4 extends along the cover plate CG from its edge towards its center. After the cover plate CG deforms under stress, it exerts a tensile force F2 on the substrate CF through the optical adhesive layer OCA, with F2 pointing towards the light-emitting side of the display device. The flexible circuit board (FPC) is bent and attached to the display substrate TFT and the chip-on-film (COF) film respectively. Therefore, the FPC exerts a force F3 on the display substrate TFT towards the backlight module and an outward pulling force F5 on the COF film. The COF film is attached between the backlight module BLM and the housing KT; therefore, the COF film exerts a pulling force on both the backlight module BLM and the housing KT. In this situation, when the entire display device falls to the bottom, due to the different vibration directions and force directions of the cover plate CG, housing KT and flexible circuit board FPC, the flexible circuit board FPC is easily pulled, which causes the electrical connection between the flexible circuit board FPC and the display substrate TFT to be pulled. Furthermore, the film layer at the electrical connection between the flexible circuit board FPC and the display substrate TFT is prone to separation and displacement.

[0072] like Figure 3 As shown, the cell substrate CF includes a second substrate SUB2 and a black matrix layer BM and an organic layer OC, which are sequentially disposed on one side of the second substrate SUB2 and along the direction close to the liquid crystal layer LCL.

[0073] like Figure 3 As shown, the display substrate TFT includes a first substrate SUB1 and a buffer layer BUFFER, a gate insulating layer GI, and an interlayer dielectric layer ILD, which are sequentially stacked on one side of the first substrate SUB1 and in a direction away from the first substrate SUB1. The display substrate TFT also includes layers not present in the first substrate SUB1. Figure 3 Some of the films shown include gate metal layers, semiconductor layers, etc. The gate metal layer may include the gate of a thin-film transistor, and the semiconductor layer includes the active layer of a thin-film transistor.

[0074] The display substrate TFT also includes multiple fan-out lines SD located on the side of the interlayer dielectric layer ILD away from the first substrate SUB1 and in the fan-out region FA. The fan-out lines SD are located in the source and drain metal layers. The source and drain metal layers may also include the source and drain of the thin-film transistor.

[0075] Furthermore, the display substrate TFT also includes a planarization layer PLN located on the side of the source / drain metal layer (fan-out line SD) away from the first substrate SUB1, and a passivation layer PVX located on the side of the planarization layer PLN away from the first substrate SUB1. The passivation layer PVX has a via, which exposes a portion of the planarization layer PLN. The orthographic projection of the via onto the first substrate SUB1 does not overlap with the orthographic projection of the liquid crystal layer LCL onto the first substrate SUB1, and a portion of the sealant SEAL is located within the via.

[0076] As mentioned above, during the impact, the flexible printed circuit board (FPC) will stretch the display substrate TFT.

[0077] Specifically, such as Figure 3 As shown, the flexible printed circuit board (FPC) is electrically connected to the display substrate TFT through bonding pads (PADs). In other words, the flexible printed circuit board (FPC) will pull on the bonding pads (PADs), and further, the bonding pads (PADs) will pull on nearby film layers and other structures.

[0078] Depend on Figure 3 As can be seen, the bonding pads (PADs) are relatively close to the planarization layer (PLN) and the fan-out line (SD). Therefore, the bonding pads are prone to causing film separation between the planarization layer (PLN) and the fan-out line (SD), as well as film separation between the planarization layer (PLN) and the interlayer dielectric layer (ILD). Furthermore, because the fan-out line (SD) is densely distributed in the fan-out region (FA), the contact area between the planarization layer (PLN) and the fan-out line (SD) is relatively large. Generally, the planarization layer (PLN) uses an organic insulating material, while the fan-out line (SD) uses a metallic material; therefore, the adhesion between the planarization layer (PLN) and the fan-out line (SD) is relatively poor.

[0079] After the planarization layer PLN separates from the fan-out line SD and the interlayer dielectric layer ILD and vibrates and displaces, the planarization layer PLN can easily scratch the fan-out line SD or cause the fan-out line SD to displace, resulting in short circuits between different fan-out line SDs. Since the polarities of adjacent fan-out line SDs are opposite, the voltage neutralization after the short circuit causes dark lines and dark areas to appear. Therefore, if the display device is dropped, it can easily cause the fan-out line SD to malfunction, leading to display defects.

[0080] Figure 4 This is a cross-sectional structural diagram of the display panel in some other embodiments.

[0081] like Figure 4As shown, the planarization layer PLN separated from the fan-out line SD and the interlayer dielectric layer ILD. During drop vibration, the planarization layer PLN vibrates back and forth. In this case, the planarization layer PLN may scratch the fan-out line SD, causing poor transmission, or the planarization layer PLN may drive the fan-out line SD to vibrate. Since the spacing between the fan-out line SDs is relatively small, different fan-out line SDs may overlap, causing a short circuit.

[0082] Figure 5 This is a cross-sectional structural diagram of the display panel in some other embodiments.

[0083] like Figure 5 As shown, if the planarization layer PLN is displaced significantly or subjected to severe vibration, it can also cause damage to the sealant SEAL or even cause it to come unglued, resulting in liquid leakage. That is, the liquid crystal in the liquid crystal layer LCL leaks from the display area AA to the non-display area.

[0084] Of course, in some embodiments, problems such as fan-out line SD failure and leakage may occur simultaneously.

[0085] In order to at least alleviate or resolve one of the aforementioned technical problems, this disclosure provides a display substrate, a display panel, and a display device.

[0086] The planar structural schematic diagrams of the display substrates of some embodiments disclosed herein can be compared with... Figure 2 The schematic diagram of the planar structure of the display substrate shown is the same.

[0087] like Figure 2 As shown, the present disclosure provides a display substrate TFT having a display area AA, a bonding area PA1 located on one side of the display area AA, and a fan-out area FA located between the display area AA and the bonding area PA1.

[0088] Figure 6 This is a cross-sectional structural diagram of the display panel in some embodiments of this disclosure. Figure 7 This is a cross-sectional structural diagram of the display panel in some embodiments of this disclosure. Figure 8 This is a cross-sectional structural diagram of the display panel in some embodiments of this disclosure.

[0089] In some embodiments, such as Figures 6 to 8 As shown, the display substrate TFT includes: a first substrate SUB1 and an interlayer dielectric layer ILD, multiple gate lines, multiple data lines, multiple first fan-out lines SD1, and a planarization layer PLN located on one side of the first substrate SUB1.

[0090] The data line is located on the side of the interlayer dielectric layer (ILD) away from the first substrate (SUB1) and is situated in the display area (AA). Optionally, the data line can be disposed on the same layer as the first fan-out line (SD1).

[0091] In this embodiment of the disclosure, "same-layer setting" means that the two structures are formed by the same material layer through a patterning process, so the two are in the same layer in terms of layering relationship.

[0092] The first fan-out line SD1 is disposed on the side of the interlayer dielectric layer (ILD) away from the first substrate (SUB1) and located in the fan-out region FA. Furthermore, the first fan-out line SD1 is electrically connected to the data line.

[0093] The planarization layer PLN is located on the side of the data line layer away from the first substrate SUB1, or the planarization layer PLN is located on the side of the first fan-out line SD1 layer away from the first substrate SUB1, and a portion of the planarization layer PLN is in contact with the interlayer dielectric layer ILD.

[0094] Furthermore, the interlayer dielectric layer (ILD) has multiple grooves, at least a portion of the first fan-out line SD1 is located in the grooves, and the thickness of the first fan-out line SD1 is different from the depth of the grooves. For example, the thickness of the first fan-out line SD1 is greater than the depth of the grooves, or the thickness of the first fan-out line SD1 is less than the depth of the grooves.

[0095] And / or, the display substrate TFT also includes a protective layer 10 located on the side of the first fan-out line SD1 away from the first substrate SUB1, a portion of the protective layer 10 is in contact with the interlayer dielectric layer ILD, and the adhesion between the protective layer 10 and the interlayer dielectric layer ILD is greater than the adhesion between the planarization layer PLN and the interlayer dielectric layer ILD.

[0096] Specifically, in Figure 6 In the illustrated embodiment, the interlayer dielectric layer (ILD) has multiple grooves, at least a portion of the first fan-out line SD1 is located within the grooves, and the thickness H1 of the first fan-out line SD1 is different from the depth H2 of the grooves. For example, in this embodiment of the present disclosure, the thickness H1 of the first fan-out line SD1 is greater than the depth H2 of the grooves.

[0097] In this embodiment, a groove is formed by cutting a groove in the interlayer dielectric layer (ILD), and at least a portion of the first sector outgoing line SD1 is located within the groove. This embodiment allows at least a portion of the first sector outgoing line SD1 to be embedded in the ILD. Therefore, even if the planarization layer (PLN) separates from the first sector outgoing line SD1 and the ILD, the damage caused by the PLN to the first sector outgoing line SD1 is reduced. Furthermore, because the first sector outgoing line SD1 is embedded in the ILD, the ILD can fix its position. Therefore, this embodiment at least prevents the PLN from causing the first sector outgoing line SD1 to move, thereby preventing short circuits between different first sector outgoing lines SD1. In summary, this embodiment can alleviate or avoid the problem of malfunctions in the first sector outgoing line SD1.

[0098] exist Figure 7 In the embodiment shown, the display substrate TFT further includes a protective layer 10, a portion of which is in contact with the interlayer dielectric layer ILD. The adhesion between the protective layer 10 and the interlayer dielectric layer ILD is greater than the adhesion between the planarization layer PLN and the interlayer dielectric layer ILD.

[0099] In this embodiment, the protective layer 10 is located on the side of the first fan-out line SD1 away from the first substrate SUB1, and a portion of the protective layer 10 is in contact with the interlayer dielectric layer ILD. Therefore, at least a portion of the protective line is located between the interlayer dielectric layer ILD and the protective layer 10. In this case, even if the planarization layer PLN separates from the interlayer dielectric layer ILD, the presence of the protective layer 10 prevents the planarization layer PLN from scratching the first fan-out line SD1.

[0100] Furthermore, the adhesion between the protective layer 10 and the interlayer dielectric layer ILD is greater than that between the planarization layer PLN and the interlayer dielectric layer ILD. That is, the protective layer 10 is not as prone to film detachment as the planarization layer PLN. Therefore, the protective layer 10 can also fix the position of the first outgoing line SD1 and prevent the first outgoing line SD1 from moving.

[0101] Furthermore, by Figure 7 As shown, a portion of the protective layer 10 is also located between adjacent first outgoing lines SD1. Therefore, the protective layer 10 can also isolate adjacent first outgoing lines SD1, thereby preventing short circuits caused by overlapping of adjacent first outgoing lines SD1.

[0102] exist Figure 8In the illustrated embodiment, the interlayer dielectric layer (ILD) has multiple grooves, and at least a portion of the first fan-out line SD1 is located within these grooves. For example, in this embodiment, the thickness H1 of the first fan-out line SD1 is less than the depth H2 of the grooves. Simultaneously, the display substrate TFT further includes a protective layer 10, located on the side of the first fan-out line SD1 away from the first substrate SUB1, and a portion of the protective layer 10 is in contact with the interlayer dielectric layer (ILD). The adhesion between the protective layer 10 and the interlayer dielectric layer (ILD) is greater than the adhesion between the planarization layer PLN and the interlayer dielectric layer (ILD).

[0103] Accordingly, in this embodiment of the present disclosure, the first outgoing line SD1 is embedded in the groove opened in the interlayer dielectric layer ILD, so the interlayer dielectric layer ILD can fix the position of the first outgoing line SD1.

[0104] Meanwhile, since the protective layer 10 is located on the side of the first fan-out line SD1 away from the first substrate SUB1, that is, at least part of the first fan-out line SD1 in this embodiment is located between the interlayer dielectric layer ILD and the planarization layer PLN, or it can also be understood that at least part of the first fan-out line SD1 is covered by the protective layer 10, that is, the first fan-out line SD1 is no longer in contact with the planarization layer PLN. Therefore, in this embodiment, even if the planarization layer PLN and the interlayer dielectric layer ILD separate, the first fan-out line SD1 covered by the protective layer 10 is no longer affected by the planarization layer PLN, that is, it will not be scratched by the planarization layer PLN, nor will it be displaced by the planarization layer PLN.

[0105] Furthermore, the adhesion between the protective layer 10 and the interlayer dielectric layer ILD is greater than that between the planarization layer PLN and the interlayer dielectric layer ILD. That is, the protective layer 10 in this embodiment will not separate from the interlayer dielectric layer ILD like the planarization layer PLN, which would cause scratches or other effects on the first fan-out line SD1.

[0106] In summary, by creating grooves and / or providing a protective layer 10, the embodiments of this disclosure can prevent the first outgoing line SD1 from being affected by the separation of the planarization layer PLN during a fall or impact.

[0107] In some embodiments, such as Figure 7 As shown, the planarization layer PLN has at least one first opening, which exposes at least a portion of the first fan-out line SD1 and a portion of the interlayer dielectric layer ILD.

[0108] The protective layer 10 includes a first protective portion 11 located within the first opening. A portion of the first protective portion 11 is in contact with the surface of the interlayer dielectric layer ILD away from the first substrate SUB1, and another portion of the first protective portion 11 is located on the side of the first fan-out line SD1 away from the substrate and is in contact with the first fan-out line SD1.

[0109] In this embodiment of the disclosure, by opening a first opening in the planarization layer PLN and placing a portion of the protective layer 10, namely the first protective part 11, inside the first opening, the vibration phenomenon of the planarization layer PLN after film separation from the interlayer dielectric layer ILD can be reduced by the adhesion force between the first protective part 11 and the interlayer dielectric layer ILD, thereby reducing the impact of the planarization layer PLN on some first fan-out lines SD1 that are not covered by the protective layer 10.

[0110] Furthermore, a portion of the first part is in contact with the interlayer dielectric layer (ILD), and another portion is located on the side of the first fan-out line SD1 away from the first substrate (SUB1) and is in contact with the first fan-out line SD1. That is, it can be understood that in this embodiment of the present disclosure, at least a portion of the first fan-out line SD1 is surrounded by the first protective portion 11 and the interlayer dielectric layer (ILD). Therefore, the first protective portion 11 can prevent the first fan-out line SD1 from being affected by the film separation planarization layer (PLN). Moreover, the adhesion between the first protective portion 11 and the interlayer dielectric layer (ILD) is greater; therefore, the first protective portion 11 will not separate from the interlayer dielectric layer (ILD) like the planarization layer (PLN), thus not affecting the first fan-out line SD1.

[0111] Figure 9 This is a cross-sectional structural diagram of the display substrate in some other embodiments of this disclosure.

[0112] In some embodiments, such as Figure 9 As shown, the protective layer 10 in this embodiment further includes a second protective portion 12 located on the side of the planarization layer PLN away from the first substrate SUB1.

[0113] In this embodiment of the present disclosure, the second protective portion 12 is located on the side of the planarization layer PLN away from the first substrate SUB1, such as... Figure 9 As shown, the first protective portion 11 and the second protective portion 12 are connected to form a single protective layer 10. Alternatively, the protective layer 10 can be understood as continuous, meaning the first protective portion 11 and the second protective portion 12 are connected. Therefore, a portion of the planarization layer PLN is surrounded by the protective layer 10 and the interlayer dielectric layer ILD. Since the protective layer 10 has strong adhesion to the interlayer dielectric layer ILD, the protective layer 10 will not easily separate from the interlayer dielectric layer ILD. Therefore, in this embodiment, the separation of the planarization layer PLN from the interlayer dielectric layer ILD can be reduced or avoided.

[0114] In addition, in the case where the portion of the planarization layer PLN not surrounded by the protective layer 10 and the interlayer dielectric layer ILD separates from the interlayer dielectric layer ILD, the protective layer 10 of the present disclosure embodiment can also reduce the vibration degree of the planarization layer PLN after separation, thereby avoiding the planarization layer PLN from affecting the first fan-out line SD1 of the lower film layer.

[0115] In some embodiments, such as Figure 9 As shown, the display substrate TFT also includes a passivation layer PVX located on the side of the planarization layer PLN away from the first substrate SUB1. The protective layer 10 is disposed in the same layer as the passivation layer PVX and is made of the same material.

[0116] In this embodiment, the protective layer 10 can be prepared simultaneously with the passivation layer PVX, that is, it can be formed using the same preparation process as the passivation layer PVX. Therefore, this embodiment can simplify the preparation process and reduce the preparation difficulty.

[0117] In some embodiments, the materials of the protective layer 10 and the passivation layer PVX can be inorganic materials containing Si, such as at least one of SiO, SiN, and SiON.

[0118] In this embodiment, for example, SiN is chosen as the material for the protective layer. SiN is very dense and can effectively protect the first outgoing line SD, as well as resist moisture intrusion. Furthermore, the protective layer 10 is made of a similar or identical material to the passivation layer PVX, which can improve the adhesion between the protective layer 10 and the passivation layer PVX.

[0119] Figure 10 This is a cross-sectional structural diagram of the display substrate TFT in some other embodiments of this disclosure.

[0120] In some embodiments, such as Figure 10 As shown, the protective layer 10 and the passivation layer PVX are connected as a single structure.

[0121] In this embodiment, the protective layer 10 and the passivation layer PVX are integrally connected as a continuous film layer, and a portion of the protective layer 10 is in contact with the interlayer dielectric layer ILD. The passivation layer PVX is located on the side of the planarization layer PLN away from the first substrate SUB1. Therefore, the continuous film layer formed by the connection of the protective layer 10 and the passivation layer PVX can protect or fix the position of the planarization layer PLN during a drop or impact, avoiding or mitigating film separation between the planarization layer PLN and the interlayer dielectric layer ILD. Furthermore, in the event of film separation between the planarization layer PLN and the interlayer dielectric layer ILD, the position of the planarization layer PLN is restricted to prevent significant displacement and vibration of the separated planarization layer PLN, thereby avoiding impact on the first fan-out line SD1 or other film layer structures of the attachment.

[0122] Figure 11 This is a cross-sectional structural diagram of the display substrate in some other embodiments of this disclosure. Figure 12 This is a cross-sectional structural diagram of the display substrate in some other embodiments of this disclosure.

[0123] like Figure 8 , Figure 11 and Figure 12 As shown, the display substrate TFT includes a protective layer 10, which is located between the planarization layer PLN and the layer where the first fan-out line SD1 is located.

[0124] In this embodiment, a protective layer 10 is formed directly to protect the first fan-out line SD1 before the planarization layer PLN is formed. It is clear that this embodiment adds a step of forming the protective layer 10 to the existing TFT fabrication process for the display substrate.

[0125] And in Figure 7 , Figure 9 and Figure 10 In the illustrated embodiment, the protective layer 10 is formed after the planarization layer PLN. Specifically, after the planarization layer PLN is formed, the planarization layer PLN is patterned to form the first opening before the protective layer 10 is formed. However, as described in the aforementioned embodiments, Figure 7 , Figure 9 , Figure 10 In the illustrated embodiment, the protective layer 10 can be prepared simultaneously with the passivation layer PVX; therefore, Figure 7 , Figure 9 and Figure 10 The embodiment shown does not require an additional step of forming a protective layer 10 on top of the original TFT fabrication process for the display substrate.

[0126] Specifically, in one example, the original display substrate TFT fabrication process steps include: sequentially forming a light-shielding layer, a semiconductor layer, a gate metal layer, an interlayer dielectric layer (ILD), a source / drain metal layer, a planarization layer (PLN), a common electrode layer, a passivation layer (PVX), and a pixel electrode layer on one side of the first substrate SUB1.

[0127] In this embodiment of the disclosure, the TFT fabrication process of the display substrate includes: sequentially forming a light-shielding layer, a semiconductor layer, a gate metal layer, an interlayer dielectric layer (ILD), a source / drain metal layer, a protective layer 10, a planarization layer (PLN), a common electrode layer, a passivation layer (PVX), and a pixel electrode layer on one side of the first substrate SUB1.

[0128] Although the embodiments of this disclosure include an additional step of preparing the protective layer 10 separately, it is because Figure 8 , Figure 11 and Figure 12As shown, the protective layer 10 can effectively cover the first outgoing line SD1, thereby isolating the planarization layer PLN and the first outgoing line SD1. Therefore, the embodiments of this disclosure can completely avoid the influence of the planarization layer PLN on the first outgoing line SD1.

[0129] like Figure 11 As shown, the protective layer 10 includes a plurality of spaced third protective parts 13. The third protective parts 13 extend in the same direction as the first outgoing line SD1 and cover at least a portion of the first outgoing line SD1.

[0130] The embodiments disclosed herein can cover and protect each first outgoing line SD1 by means of the third protection unit 13, thereby achieving precise protection of the first outgoing line SD1.

[0131] Meanwhile, compared to embodiments without protective layer 10, such as Figure 3 As shown, in this embodiment, the depth to which the planarization layer PLN is embedded between two adjacent third protection portions 13 is greater than [the depth of the embedded layer]. Figure 3 In the illustrated embodiment, the planarization layer PLN is embedded at a depth between two adjacent first fan-out lines SD1. Therefore, this embodiment of the present disclosure can also limit the displacement and vibration amplitude of the planarization layer PLN that has separated from the interlayer dielectric layer ILD, thereby reducing the impact caused by the separation of the planarization layer PLN.

[0132] like Figure 12 As shown, at least two of the third protective parts 13 are connected as a single structure. Furthermore, all the third protective parts 13 are connected as a single structure.

[0133] In this embodiment of the present disclosure, at least two third protective parts 13 are connected as an integral structure, which can increase the contact area between the protective layer 10 and the interlayer dielectric layer ILD, thereby increasing the adhesion between the protective layer 10 and the interlayer dielectric layer ILD.

[0134] Furthermore, all the third protective parts 13 are connected as a single structure, which reduces the steps of patterning the protective layer 10, thereby reducing the difficulty of preparation.

[0135] Figure 13 This is a schematic diagram of the planar structure of the display substrate in some other embodiments of this disclosure.

[0136] In some embodiments, such as Figure 13 As shown, the fan-out region FA includes multiple first regions FA1 and second regions FA2 arranged along a third direction. The first regions FA1 are located on opposite sides of the second regions FA2 along the third direction.

[0137] For example, the fan-out region FA includes two first regions FA1 and a second region FA2, and the first region FA1 is located on opposite sides of the second region FA2 in the third direction.

[0138] Wherein, the third direction intersects the arrangement direction of the fan-out area FA and the bonding area PA1, and at least the first area FA1 is provided with a first fan-out line SD1, that is, at least the fan-out line SD in the first area FA1 includes the first fan-out line SD1, that is, a corresponding groove or protective layer 10 needs to be provided in the first area FA1. Alternatively, the fan-out lines SD in both the first area FA1 and the second area FA2 include the first fan-out line SD1, that is, a corresponding groove or protective layer 10 needs to be provided in both the first area FA1 and the second area FA2.

[0139] It is understood that in this embodiment of the present disclosure, the first region FA1 is located at the edge of the display substrate TFT compared to the second region FA2. During the drop impact, the film layer in the first region FA1 will be subjected to a greater impact than the film layer in the second region FA2. Therefore, the planarization layer PLN and the first fan-out line SD1 in the first region FA1 will be more affected. Thus, the first fan-out line SD1 is more likely to fail in the first region FA1.

[0140] Therefore, in this embodiment of the present disclosure, at least a corresponding groove and / or protective layer 10 are provided in the first region FA1 to protect the planarization layer PLN and the first fan-out line SD1 in the first region FA1, so as to avoid the problem of the first fan-out line SD1 being faulty in the first region FA1 as much as possible.

[0141] In some embodiments, such as Figure 13 As shown, the fan-out region FA includes a first region FA1 and a second region FA2 arranged along a third direction. The first fan-out line SD1 is located in the first region FA1. The display substrate TFT also includes a second fan-out line SD2SD located in the second region FA2. The distribution density of the first fan-out line SD1 in the first region FA1 is greater than the distribution density of the second fan-out line SD2SD in the second region FA2.

[0142] Obviously, in this embodiment of the present disclosure, the groove and the protective layer 10 are respectively set in the area where the distribution density of the fan-out line SD in the fan-out area FA is relatively large.

[0143] As mentioned above, the denser the fan-out line SD, the more easily the fan-out line SD will be affected and become defective when the planarization layer PLN separates from the interlayer dielectric layer ILD or from the fan-out line SD.

[0144] Therefore, in this embodiment of the present disclosure, at least a corresponding groove and / or protective layer 10 are provided in the first region FA1 to protect the planarization layer PLN and the first fan-out line SD1 in the first region FA1, so as to avoid the problem of the first fan-out line SD1 being defective in the first region FA1 with a larger distribution density.

[0145] Optionally, such as Figure 13 As shown, the display substrate TFT also includes pad areas PA2 located on opposite sides of the bonding area PA1 in the third direction. The pad areas PA2 are provided with multiple test pads. In one example, some of these test pads can be electrically connected to the bonding pads of the bonding area PA1. Therefore, during the testing of the display substrate TFT, data driving signals can be provided to the display substrate TFT through the test pads.

[0146] In some embodiments, the materials of both the interlayer dielectric layer (ILD) and the protective layer 10 include inorganic materials. For example, they may both include Si-containing inorganic materials, specifically, for example, at least one of SiO, SiN, and SiON.

[0147] In this embodiment, both the interlayer dielectric layer (ILD) and the protective layer 10 are made of inorganic materials, which can increase the adhesion between the interlayer dielectric layer (ILD) and the protective layer 10. Furthermore, the materials of the interlayer dielectric layer (ILD) and the protective layer 10 can be the same, thereby maximizing the adhesion between the interlayer dielectric layer (ILD) and the protective layer 10 and preventing film separation between the protective layer 10 and the interlayer dielectric layer (ILD).

[0148] Figure 14A This is a schematic diagram of the planar structure of the fan-out region in some embodiments of this disclosure. Specifically, it may be a schematic diagram of the planar structure of the second region FA2. Figure 14B and Figure 14C They are Figure 14A A schematic diagram of the planar structure of each single-layer film layer, wherein, Figure 14B Specifically Figure 14A A schematic diagram of the planar structure of the planarization layer PLN. Figure 14C yes Figure 14A A schematic diagram of the planar structure of the first outgoing line SD1.

[0149] like Figure 14A As shown, multiple first openings are arranged along a first direction, and the first openings extend along a second direction, which intersects with the first direction.

[0150] In fact, the extension direction of the first opening and the arrangement direction of the plurality of first openings in the embodiments of this disclosure can be selected by the user.

[0151] Optionally, the orthographic projection of the first opening onto the first substrate SUB1 can be rectangular, circular, elliptical, polygonal, or irregular in shape, etc., and this embodiment of the present disclosure does not limit this. In order to improve the yield and ensure the exposure of the first opening to the interlayer dielectric layer ILD and the first fan-out line SD1 to ensure the adhesion between the interlayer dielectric layer ILD and the protective layer 10, this embodiment of the present disclosure sets the shape of the orthographic projection of the first opening onto the first substrate SUB1 to be rectangular or rounded rectangle.

[0152] Accordingly, Figure 7 , Figure 8 The cross-sectional view of an embodiment with a first opening is a schematic diagram of a cross-sectional structure that can be cut along the width direction of the first direction. For example, specifically, it can be along... Figure 14A A schematic diagram of the cross-sectional structure cut by the tangent line YY'.

[0153] In order to improve yield and reduce preparation difficulty, in this embodiment of the disclosure, the second direction is set to be the same as the extension direction of the data line.

[0154] Figure 15A This is a schematic diagram of the planar structure of the fan-out region in some other embodiments of this disclosure. Specifically, it may be a schematic diagram of the planar structure of the second region FA2. Figure 15B yes Figure 15A A schematic diagram of the planar structure of the planarization layer PLN. Figure 15A The schematic diagram of the first outgoing line SD1 in the middle can be compared with... Figure 14C The planar structure diagram of the first outgoing fan SD1 shown is the same.

[0155] Similarly, in order to improve yield and reduce preparation difficulty, in this embodiment of the disclosure, the second direction is set to be the same as the extension direction of the gate line.

[0156] Figure 16A This is a schematic diagram of the planar structure of the fan-out region in some other embodiments of this disclosure. Specifically, it may be a schematic diagram of the planar structure of the second region FA2. Figure 16B yes Figure 16A A schematic diagram of the planar structure of the planarization layer PLN. Figure 16A The schematic diagram of the first outgoing line SD1 in the middle can be compared with... Figure 14C The planar structure diagram of the first outgoing fan SD1 shown is the same.

[0157] Similarly, in order to improve yield and reduce preparation difficulty, in this embodiment of the disclosure, the second direction is set to be the same as the extension direction of the first fan-out line SD1.

[0158] In summary, the width of the first opening is greater than the width of the first fan-out line SD1. This ensures that a portion of the protective layer is located on the side of the first fan-out line SD1 away from the first substrate SUB1, and that a portion of the protective layer can contact the interlayer dielectric layer ILD, thereby ensuring the protective effect of the protective layer 10 on the first fan-out line SD1.

[0159] It should be noted that the first opening in the accompanying drawings of this embodiment does not represent its specific size; the specific size and position can be adjusted according to different products. For example, in one example, the first region has a width of approximately 8 mm in the third direction, and the number of first openings is approximately 500.

[0160] In other embodiments, this disclosure also provides a display panel including a display substrate TFT as described in any embodiment of this disclosure.

[0161] In other embodiments, the display panel further includes: a cell substrate CF disposed opposite to the display substrate TFT and a sealing adhesive SEAL located between the display substrate TFT and the cell substrate CF.

[0162] Among them, the orthographic projection of the sealing adhesive SEAL on the first substrate SUB1 surrounds the display area AA, and overlaps with the orthographic projection of the first fan-out line SD1 on the first substrate SUB1.

[0163] In this embodiment of the present disclosure, the orthographic projection of the sealant SEAL on the first substrate SUB1 overlaps with the orthographic projection of the first fan-out line SD1 on the first substrate SUB1. That is, it can be further understood that the orthographic projection of the sealant SEAL on the first substrate SUB1 overlaps with the orthographic projection of at least one of the groove and the protective layer 10 on the first substrate SUB1.

[0164] Therefore, based on the protection of the first fan-out line SD1 by the setting of the protective layer 10 and the groove, that is, based on the ability to alleviate the vibration and displacement of the planarization layer PLN after film separation, the setting of the protective layer 10 and the groove in this embodiment can further alleviate or avoid the impact on the sealing adhesive SEAL caused by excessive vibration or displacement of the planarization layer PLN, and avoid the occurrence of leakage problems.

[0165] Specifically, such as Figure 7 and Figure 8 As shown, the display substrate TFT includes a protective layer 10, a planarization layer PLN having at least one first opening, and a portion of the sealant SEAL located within the first opening and in contact with the surface of the protective layer 10 away from the first substrate SUB1.

[0166] Obviously, in Figure 3In the embodiment shown, a portion of the sealant SEAL is in contact with the side of the planarization layer PLN away from the first substrate SUB1. Therefore, if the planarization layer PLN vibrates too violently, the sealant SEAL may be damaged, resulting in leakage.

[0167] In this embodiment, the sealant SEAL is in contact with the surface of the protective layer 10 away from the first substrate SUB1, and the protective layer 10 can adhere well to the interlayer dielectric layer ILD without film separation. Therefore, this embodiment can avoid damage to the sealant SEAL caused by the large vibration of the protective layer 10 due to impact film separation.

[0168] Furthermore, the present embodiment increases the contact area between the protective layer 10 and the sealant, thereby increasing the adhesion between the protective layer 10 and the sealant.

[0169] Furthermore, the protective layer 10 can also slow down the film separation and vibration of the planarization layer PLN. Therefore, the embodiments of this disclosure can also slow down or avoid damage to the sealant SEAL by the planarization layer PLN.

[0170] Therefore, the embodiments disclosed herein can avoid the problem of liquid leakage in the display panel.

[0171] In summary, this disclosure proposes new technical solutions to address the problem of display device failure caused by drop impacts. For example, one solution involves designing a grooved groove in the planarization layer (PLN) covering the frame sealant (SEAL) on the existing product process, and using a protective layer 10 to cover the first outgoing line SD1. This ensures that even if the planarization layer (PLN) floats or shifts, it will not scratch the first outgoing line SD1. Another solution is to add a protective layer 10 to the existing process, using either SiN or SiO2 for separate coverage, to protect the densely packed area of ​​the first outgoing line SD1, thereby improving the product's drop resistance.

[0172] This disclosure also provides a display device, including a display panel as described in any embodiment of this disclosure.

[0173] In summary, the embodiments of this disclosure incorporate grooves and protective designs in weak areas of the fan-out region, such as areas with dense fan-out lines. This achieves the dual purpose of protecting the fan-out lines from scratches caused by the planarization layer (PLN) during drop tests and increasing the contact area of ​​the sealing adhesive to maintain adhesion and improve the strength of the display panel during drop tests. Therefore, the grooved design and stacked protective layer structure proposed in these embodiments not only prevent scratches from drop tests but also improve local adhesion, resulting in enhanced product strength.

[0174] The first region in this embodiment is merely an example of the problem area, and there may be slight variations in different actual products. The ultimate goal of this embodiment is to protect densely packed wiring and prevent the planarization layer PLN from separating and shifting from the underlying film layer during strength tests such as drop and vibration, which could cause scratches on the fan-out lines.

[0175] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate comprising a display area, a bonding area located on one side of the display area, and a fan-out area located between the display area and the bonding area, characterized in that, The display substrate includes: Substrate; An interlayer dielectric layer and multiple data lines are located on one side of the substrate. The data lines are disposed on the side of the interlayer dielectric layer away from the substrate and are located in the display area. Multiple first fan-out lines are disposed on the side of the interlayer dielectric layer away from the substrate and located in the fan-out region; the first fan-out lines are electrically connected to the data lines. A planarization layer is located on the side of the layer containing the first fan-out line that is away from the substrate, and a portion of the planarization layer is in contact with the interlayer dielectric layer. The interlayer dielectric layer has multiple grooves, at least a portion of the first fan-out line is located in the grooves, and the thickness of the first fan-out line is different from the depth of the grooves. And / or, the display substrate further includes a protective layer located on the side of the first fan-out line away from the substrate, a portion of the protective layer being in contact with the interlayer dielectric layer, and the adhesion between the protective layer and the interlayer dielectric layer being greater than the adhesion between the planarization layer and the interlayer dielectric layer.

2. The display substrate according to claim 1, characterized in that, The display substrate also includes a protective layer; The planarization layer has at least one first opening, the first opening exposing at least a portion of the first fan-out line and a portion of the interlayer dielectric layer. The protective layer includes a first protective portion located within the first opening. A portion of the first protective portion is disposed in contact with the surface of the interlayer dielectric layer away from the substrate. Another portion of the first protective portion is located on the side of the first fan-out line away from the substrate and is disposed in contact with the first fan-out line.

3. The display substrate according to claim 2, characterized in that, The protective layer also includes a second protective portion located on the side of the planarization layer away from the substrate.

4. The display substrate according to claim 2, characterized in that, There are multiple first openings, which are arranged along a first direction and extend along a second direction, which intersects the first direction. Wherein, the second direction is the same as the extension direction of either the first fan-out line or the data line, or the display substrate further includes a gate line located in the display area, the gate line being intersected with the data line, and the second direction being the same as the extension direction of the gate line.

5. The display substrate according to claim 2, characterized in that, The display substrate further includes a passivation layer located on the side of the planarization layer away from the substrate. The protective layer and the passivation layer are disposed in the same layer and are made of the same material.

6. The display substrate according to claim 5, characterized in that, The protective layer and the passivation layer are connected as a single structure.

7. The display substrate according to claim 1, characterized in that, The display substrate includes a protective layer located between the planarization layer and the layer containing the first fan-out line.

8. The display substrate according to claim 7, characterized in that, The protective layer includes a plurality of spaced-apart third protective portions, which extend in the same direction as the first fan-out line and cover at least a portion of the first fan-out line.

9. The display substrate according to claim 8, characterized in that, At least two of the third protection units are connected as a single structure.

10. The display substrate according to any one of claims 1 to 9, characterized in that, The fan-out area includes a plurality of first areas and second areas arranged along a third direction. The first areas are located on opposite sides of the second areas along the third direction. The third direction intersects the arrangement direction of the fan-out area and the binding area. At least the first area is provided with the first fan-out line.

11. The display substrate according to any one of claims 1 to 9, characterized in that, The fan-out area includes a first region and a second region arranged along a third direction. The first fan-out line is located in the first region. The display substrate also includes a second fan-out line located in the second region. The distribution density of the first fan-out line in the first region is greater than the distribution density of the second fan-out line in the second region.

12. The display substrate according to any one of claims 2 to 9, characterized in that, Both the interlayer dielectric layer and the protective layer are made of inorganic materials.

13. A display panel, characterized in that, Includes the display substrate as described in any one of claims 1 to 12.

14. The display panel according to claim 13, characterized in that, The display panel also includes: The cell substrate is disposed opposite to the display substrate; The sealing adhesive is located between the display substrate and the cell substrate. The orthographic projection of the sealing adhesive on the substrate surrounds the display area and overlaps with the orthographic projection of the first fan-out line on the substrate.

15. The display panel according to claim 14, characterized in that, The display substrate includes a protective layer, the planarization layer has at least one first opening, and a portion of the sealing adhesive is located within the first opening and in contact with the surface of the protective layer away from the substrate.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 13 to 15.

Images