Display substrate and display device

Abstract

The embodiment of the utility model provides a display substrate and a display device. The display substrate comprises a display area and a non-display area, and further comprises a substrate, at least one electrostatic short circuit ring, a first conductive wire and a second conductive wire, the electrostatic short circuit ring is located in the non-display area and comprises a first thin film transistor and a second thin film transistor, and a first source electrode in the first thin film transistor is connected with a first grid electrode; a second source electrode in the second thin film transistor is connected with a second grid electrode; the first grid electrode is coupled with one of the first conductive wire and the second conductive wire, the second grid electrode is coupled with the other one of the first conductive wire and the second conductive wire, one of the first conductive wire and the second conductive wire is located on the first metal layer, the other one is located on the second metal layer, and a first insulating layer is arranged between the first metal layer and the second metal layer. According to the technical scheme, overall failure of the electrostatic short circuit ring can be avoided, short circuit of the two conductive wires is prevented, and the reject ratio of products is reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] With the development of consumer electronics, electronic paper products are widely used. Electronic paper products adopt the principle of reflective display and have the advantage of low power consumption. In order to expand the application scenarios of electronic paper, color paper films are developed and applied in the field of color electronic paper (E-Note). Color paper films need to meet the scene of high voltage and high brush driving. Therefore, the semiconductor in the color paper film is changed from amorphous silicon (a-Si) to oxide. With the high mobility and low leakage characteristics of oxide, low-power products can be developed by matching color paper films, thereby expanding the application scenarios.

[0003] The color E-Note products in the related art have horizontal line defect problems, which affect the product yield. UTILITY MODEL CONTENT

[0004] Embodiments of the present disclosure provide a display substrate and a display device to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of the embodiments of the present disclosure, a display substrate is provided, comprising a display area and a non-display area outside the display area, the display substrate comprising:

[0006] a substrate;

[0007] at least one electrostatic short circuit ring located on one side of the substrate and in the non-display area, the electrostatic short circuit ring comprising a first thin film transistor and a second thin film transistor, a first gate of the first thin film transistor and a second gate of the second thin film transistor are located in a first metal layer, a first source in the first thin film transistor is coupled with the first gate, a second source in the second thin film transistor is coupled with the second gate, a first drain of the first thin film transistor is coupled with a second drain of the second thin film transistor, the first drain and the second drain are located between the first source and the second source, the first source, the second source, the first drain and the second drain are located in a second metal layer, the second metal layer is located on a side of the first metal layer away from the substrate, and a first insulating layer is arranged between the second metal layer and the first metal layer;

[0008] The first conductive trace and the second conductive trace are located on a side of the substrate facing the electrostatic shorting ring, one of the first conductive trace and the second conductive trace is coupled to the first gate, and the other of the first conductive trace and the second conductive trace is coupled to the second gate, one of the first conductive trace and the second conductive trace is located on the first metal layer, and the other of the first conductive trace and the second conductive trace is located on the second metal layer.

[0009] In some embodiments, further comprising a gate line located in the display area and extending in a first direction, and the first conductive trace comprises the gate line.

[0010] The display substrate further comprises a first electrostatic discharge line located in the non-display area, and the second conductive trace comprises the first electrostatic discharge line.

[0011] The at least one electrostatic shorting ring comprises a first electrostatic shorting ring, a first gate in the first electrostatic shorting ring is coupled to the gate line, and a second gate in the first electrostatic shorting ring is coupled to the first electrostatic discharge line; the gate line is located on the first metal layer, and the first electrostatic discharge line is located on the second metal layer.

[0012] In some embodiments, the non-display area comprises a first sub-area extending in a second direction, the first electrostatic shorting ring is located in the first sub-area, and the first electrostatic discharge line is located in the first sub-area and extends in the second direction within the first sub-area, the second direction being perpendicular to the first direction.

[0013] In some embodiments, further comprising a data line located in the display area and extending in a second direction, and the second conductive trace comprises the data line.

[0014] The display substrate further comprises a second electrostatic discharge line located in the non-display area, and the first conductive trace comprises the second electrostatic discharge line.

[0015] The at least one electrostatic shorting ring comprises a second electrostatic shorting ring, the first gate in the second electrostatic shorting ring is coupled to the second electrostatic discharge line, and the second gate in the second electrostatic shorting ring is coupled to the data line; the second electrostatic discharge line is located on the first metal layer, and the data line is located on the second metal layer.

[0016] In some embodiments, the non-display area comprises a second sub-area extending in a first direction, the second electrostatic shorting ring is located in the second sub-area, and the second electrostatic discharge line is located in the second sub-area and extends in the first direction within the second sub-area, the second direction being perpendicular to the first direction.

[0017] In some embodiments, the non-display region includes a second sub-region extending along a first direction and a first sub-region extending along a second direction perpendicular to the first direction.

[0018] The display substrate includes a first electrostatic discharge line in the first sub-region and a second electrostatic discharge line in the second sub-region, the first conductive trace includes the second electrostatic discharge line, and the second conductive trace includes the first electrostatic discharge line.

[0019] The at least one electrostatic short circuit ring includes a third electrostatic short circuit ring, a first gate in the third electrostatic short circuit ring is coupled to the second electrostatic discharge line, and a second gate in the third electrostatic short circuit ring is coupled to the first electrostatic discharge line, the second electrostatic discharge line is in the first metal layer, and the first electrostatic discharge line is in the second metal layer.

[0020] In some embodiments, the first electrostatic discharge line extends along the second direction in the first sub-region, and the second electrostatic discharge line extends along the first direction in the second sub-region.

[0021] In some embodiments, the non-display region further includes a third sub-region extending along the first direction, the third sub-region and the second sub-region are respectively located on opposite sides of the display region, and the third sub-region includes a binding region including a ground signal pin.

[0022] The display substrate further includes a third electrostatic discharge line in the third sub-region, the third electrostatic discharge line is coupled to the ground signal pin, and the first conductive trace further includes the third electrostatic discharge line.

[0023] The at least one electrostatic short circuit ring further includes a fourth electrostatic short circuit ring, a first gate in the fourth electrostatic short circuit ring is coupled to the third electrostatic discharge line, and a second gate in the fourth electrostatic short circuit ring is coupled to the first electrostatic discharge line, the third electrostatic discharge line is in the first metal layer.

[0024] In some embodiments, the third sub-region further includes a fourth electrostatic discharge line, the at least one electrostatic short circuit ring further includes a fifth electrostatic short circuit ring, a first gate in the fifth electrostatic short circuit ring is coupled to the fourth electrostatic discharge line, and a second gate in the fifth electrostatic short circuit ring is coupled to the third electrostatic discharge line, the fourth electrostatic discharge line is in the first metal layer.

[0025] In some embodiments, a positive projection of the first drain on the substrate is located on a side of the first projection boundary of the first gate away from the second projection boundary, and a distance between the positive projection of the first drain on the substrate and the first projection boundary is greater than or equal to a first preset distance, the first projection boundary being a positive projection on the substrate of a boundary of the first gate opposite to the second gate, and the second projection boundary being a positive projection on the substrate of a boundary of the second gate opposite to the first gate.

[0026] The first drain is coupled to the second drain through a first transfer line, and a positive projection of the first transfer line on the substrate is located outside the first projection boundary.

[0027] In some embodiments, a positive projection of the second drain on the substrate is located on a side of the second projection boundary away from the first projection boundary, and a distance between the positive projection of the second drain on the substrate and the second projection boundary is greater than or equal to the first preset distance, and a positive projection of the first transfer line on the substrate is located outside the second projection boundary.

[0028] In some embodiments,

[0029] A distance between the positive projection of the first transfer line on the substrate and the first projection boundary is greater than or equal to the first preset distance; and / or,

[0030] A distance between the positive projection of the first transfer line on the substrate and the second projection boundary is greater than or equal to the first preset distance.

[0031] In some embodiments, the first thin film transistor further comprises a first active layer, and the second thin film transistor further comprises a second active layer, and the first active layer and the second active layer are arranged in the same layer and located on a side of the first metal layer away from the substrate.

[0032] A positive projection of the first active layer on the substrate is located on a side of the first projection boundary away from the second projection boundary, and a distance between the positive projection of the first active layer on the substrate and the first projection boundary is greater than or equal to the first preset distance; and / or, a positive projection of the second active layer on the substrate is located on a side of the second projection boundary away from the first projection boundary, and a distance between the positive projection of the second active layer on the substrate and the second projection boundary is greater than or equal to the first preset distance.

[0033] In some embodiments, the display substrate comprises gate lines and data lines in the display area, the gate lines are located in the first metal layer, and the data lines are located in the second metal layer.

[0034] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device comprising the display substrate in the embodiments of the present disclosure.

[0035] The technical solution of the embodiments of the present disclosure sets one of the first conductive trace and the second conductive trace in the first metal layer and sets the other in the second metal layer, so that the first conductive trace and the second conductive trace are in different layers, thereby avoiding the problem that the first insulating layer is damaged at the positions of the opposite edges of the first gate and the second gate due to static electricity in the process after the first insulating layer is formed and before the second metal layer is formed, avoiding the problem that the first thin film transistor and the second thin film transistor are both failed, thereby avoiding the overall failure of the static short circuit ring, preventing the short circuit of the first conductive trace and the second conductive trace, and reducing the product failure rate.

[0036] The above summary is intended to illustrate the present description and is not intended to limit in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features will be readily apparent to those skilled in the art by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0037] In the drawings, like numerals refer to like elements throughout the various drawings. The drawings are not necessarily to scale, the emphasis instead being placed on the relations between various elements. It should be understood that the drawings only depict some embodiments according to the present disclosure and should not be considered limiting of the scope of the disclosure.

[0038] Figure 1 FIG. 1 is a partial plan view of a display panel in the related art;

[0039] Figure 2 FIG. 2 is a cross-sectional view of A-A in FIG. 1; Figure 1

[0040] Figure 3 FIG. 7 is a schematic diagram of the electrical connection between a gate line and a first static discharge line;

[0041] Figure 4 FIG. 8 is a schematic diagram of an electron microscope of a static short circuit ring position after damage of a gate line and a first static discharge line;

[0042] Figure 5 FIG. 9 is a schematic diagram of gate signals of a gate line GL i and a gate line GL j in a normal operation of a display module;

[0043] Figure 6 FIG. 10 is a plan view of a display substrate in an embodiment of the present disclosure;

[0044] Figure 7 FIG. 11 is a cross-sectional view of B-B in FIG. 10; and Figure 6 ​An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment;

[0045] Figure 8 An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment; Figure 7 An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment;

[0046] Figure 9 An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment;

[0047] Figure 10 An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment; Figure 9 An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment;

[0048] Figure 11 An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment; Figure 6 An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment;

[0049] Figure 12 An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment; Figure 11 An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment;

[0050] Figure 13 An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment;

[0051] Figure 14 An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment; Figure 6 An enlarged schematic view of the display substrate shown in FIG. 1D in one embodiment;

[0052] BRIEF DESCRIPTION OF THE DRAWINGS

[0053] 10, electrostatic shorting ring; 101, first thin film transistor; 102, second thin film transistor; 11, first electrostatic shorting ring; 12, second electrostatic shorting ring; 13, third electrostatic shorting ring; 14, fourth electrostatic shorting ring; 15, fifth electrostatic shorting ring;

[0054] 21, substrate; 221, first gate; 222, second gate; 23, first insulating layer; 241, first active layer; 242, second active layer; 251, first source; 252, second source; 253, first drain; 254, second drain; 255, first / second transfer line; 26, first passivation layer; 27, organic planarization layer; 28, shielding portion; 29, second passivation layer;

[0055] 41, first electrostatic discharge line; 42, second electrostatic discharge line; 43, third electrostatic discharge line; 44, fourth electrostatic discharge line;

[0056] 51, first conductive trace; 52, second conductive trace; 53, discharge transfer line. DETAILED DESCRIPTION

[0057] In the following, only certain exemplary embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure, and different embodiments can be combined arbitrarily without conflict. Therefore, the drawings and the description are considered to be exemplary in nature rather than limiting.

[0058] Figure 1 is a partial plan view of a display panel in the related art, Figure 2 is Figure 1 is a cross-sectional view of A-A in Figure 1 and Figure 2 , as shown, the display panel includes a display area AA and a non-display area VA, the display area is provided with a plurality of gate lines GL, the non-display area VA is provided with a first electrostatic discharge line 41, and the plurality of gate lines GL and the first electrostatic discharge line 41 are located in the same metal layer, which can be called the first metal layer. The gate lines GL extend along the horizontal direction, and the length of the gate lines GL is approximately equal to the size of the display area AA in the horizontal direction. The first electrostatic discharge line 41 extends along the vertical direction, and the length of the first electrostatic discharge line 41 is approximately equal to the size of the display area AA in the vertical direction. Therefore, the lengths of the gate lines GL and the first electrostatic discharge line 41 are both relatively long. Each gate line GL is connected to the first electrostatic discharge line 41 through a corresponding electrostatic short circuit ring 10, so that the static electricity on the gate line GL can be discharged onto the first electrostatic discharge line 41 through the electrostatic short circuit ring 10.

[0059] Figure 3 is an electrical connection principle diagram of the gate line and the first electrostatic discharge line. As shown in Figures 1-3 , the electrostatic short circuit ring 10 includes a first thin film transistor (TFT) 101 and a second thin film transistor 102. The first thin film transistor 101 includes a first gate 221, a first source 251, a first drain 253, and a first active layer 241, and the second thin film transistor 102 includes a second gate 222, a second source 252, a second drain 254, and a second active layer 242. Among them, the first source 251, the first drain 253, the second source 252, and the second drain 254 are located in the same metal layer, which can be called the second metal layer. The first gate 221 is connected to the gate line GL, the second gate 222 is connected to the first electrostatic discharge line 41, the first gate 221, the second gate 222, the gate line GL, and the first electrostatic discharge line 41 are located in the same metal layer, and the first gate 221 and the second gate 222 are oppositely arranged, so that the end of the gate line GL is oppositely arranged with the first electrostatic discharge line 41 and the second gate 222. The first source 251 is connected to the first gate 221, the second source 252 is connected to the second gate 222, and the first drain 253 is connected to the second drain 254.

[0060] From Figure 2As can be seen, the first insulating layer 23 is arranged between the second metal layer and the first metal layer, and the first insulating layer 23 is located on the side of the first metal layer away from the substrate 21, and the second metal layer is located on the side of the first insulating layer 23 away from the substrate 21. Therefore, in the preparation of the display substrate, the first gate 221 and the second gate 222 are formed on the substrate 21, then the first insulating layer 23 is formed above the first gate 221 and the second gate 222, and then the first drain 253 and the second drain 254 are formed above the first insulating layer 23.

[0061] In the display substrate manufacturing process, before the second metal layer is prepared, the static electricity generated by the mechanical hand rubbing the display substrate can be transmitted along the long metal lines in the first metal layer, such as the gate line GL, to hurt the first insulating layer 23.

[0062] Figure 4 An electron microscope diagram of the damage of a gate line to the first static discharge line at the position of the static short circuit ring. The inventors found that, because the length of the gate line GL and the first static discharge line 41 is relatively long, and the gate line GL and the first static discharge line 41 are arranged in the same layer, when the static electricity in the process is transmitted along the gate line GL, the relative positions of the first gate 221 and the second gate 222 will be damaged due to the tip discharge, as shown in Figure 4 In the figure, the left boundary of the first gate 221 generates damage points A and B, and the right boundary of the second gate 222 generates damage point C, so that the first insulating layer 23 generates vias at the positions of the damage points A, B and C. Therefore, when the second metal layer is subsequently formed, the first drain 253 will be short-circuited with the first gate 221 through the vias at the positions of the damage points A and B, so that the first thin film transistor 101 is disabled, and the second drain 254 will be short-circuited with the second gate 222 through the via at the position of the damage point C, so that the second thin film transistor 102 is disabled, so that the thin film transistors on both sides of the static short circuit ring are disabled, and then the gate line GL is short-circuited with the first static discharge line 41 through the static short circuit ring.

[0063] Figure 5 A schematic diagram of the gate signals of the gate line GL i and the gate line GL j in the normal operation of the display module. Figure 1 As shown in the figure, two gate lines GL are connected with the first static discharge line 41 through corresponding static short circuit rings, the gate line GL i is connected with the first static discharge line 41 through the static short circuit ring 10a, and the gate line GL j is connected with the first static discharge line 41 through the static short circuit ring 10b. In the normal case, when the display module is powered on, the gate signals of the gate line GL i and the gate line GL j are as shown in Figure 5As shown, the gate signals of gate lines GLi and GLj do not overlap in time. When both electrostatic short-circuit rings 10a and 10b are shorted, gate lines GLi and GLj are shorted through the first electrostatic discharge line 41. When the display module is powered on, after gate line GLi is provided with a gate signal, the gate signal on gate line GLi will be transmitted to gate line GLj through the first electrostatic discharge line 41, resulting in poor horizontal stripe quality.

[0064] To prevent horizontal stripe defects caused by electrostatic discharge, this disclosure provides a display substrate.

[0065] Figure 6 This is a plan view of a display substrate according to an embodiment of the present disclosure. Figure 7 for Figure 6 The diagram shown is an enlarged view of portion D of the display substrate in one embodiment. Figure 8 for Figure 6 A schematic diagram of the BB section. (See diagram below.) Figure 6 As shown, this disclosure provides a display substrate, which includes a display area AA and a non-display area VA located outside the display area. The non-display area VA may include a first sub-region VA1 located along a first direction on at least one side of the display area, a second sub-region VA2 located along a second direction on one side of the display area, and a third sub-region VA3 located along the second direction on the other side of the display area. The third sub-region VA3 and the second sub-region VA2 are located on opposite sides of the display area along the second direction. The second direction is perpendicular to the first direction. Figure 6 In the diagram, the first direction is horizontal, and the second direction is vertical.

[0066] like Figures 6-8 As shown, the display substrate may include a substrate 21, and may also include at least one electrostatic discharge (ESD) short-circuit ring 10, as well as a first conductive trace 51 and a second conductive trace 52. The substrate 21 may be a glass substrate or a flexible substrate. At least one ESD short-circuit ring 10 is located on one side of the substrate 21 and in a non-display area. The ESD short-circuit ring 10 may include a first thin-film transistor 101 and a second thin-film transistor 102. The first thin-film transistor 101 may include a first gate 221, a first source 251, a first drain 253, and a first active layer 241, and the second thin-film transistor 102 may include a second gate 222, a second source 252, a second drain 254, and a second active layer 242.

[0067] Note that in a switching thin film transistor, the source and the drain can be interchangeable, one of the source and the drain can be called a first electrode, and the other can be called a second electrode. Here, the terms "source" and "drain" are used to distinguish the first electrode and the second electrode in the first thin film transistor and the second thin film transistor. For example, the first electrode in the first thin film transistor is called a first source, and the second electrode is called a first drain, or the first electrode in the first thin film transistor is called a first drain, and the second electrode is called a first source. Correspondingly, the first electrode in the second thin film transistor is called a second source, and the second electrode is called a second drain, or the first electrode in the second thin film transistor is called a second drain, and the second electrode is called a second source.

[0068] In the electrostatic short circuit ring 10, the first gate 221 of the first thin film transistor 101 and the second gate 222 of the second thin film transistor 102 are both located in the first metal layer. The first source 251 in the first thin film transistor 101 is coupled with the first gate 221. The second source 252 in the second thin film transistor 102 is coupled with the second gate 222. The first drain 253 of the first thin film transistor 101 is coupled with the second drain 254 of the second thin film transistor 102. The first drain 253 and the second drain 254 are located between the first source 251 and the second source 252. The first source 251, the second source 252, the first drain 253, and the second drain 254 are all located in the second metal layer, which is located on the side of the first metal layer away from the substrate 21. The second metal layer is provided with the first insulating layer 23 between the first metal layer.

[0069] The first conductive trace 51 and the second conductive trace 52 are both located on the side of the substrate 21 facing the electrostatic short circuit ring 10. The first gate 221 is coupled with one of the first conductive trace 51 and the second conductive trace 52, and the second gate 222 is coupled with the other of the first conductive trace 51 and the second conductive trace 52. One of the first conductive trace 51 and the second conductive trace 52 is located in the first metal layer, and the other is located in the second metal layer.

[0070] Exemplarily, the two thin film transistors in the electrostatic short circuit ring can be of a symmetrical structure, and therefore, the positions of the first thin film transistor 101 and the second thin film transistor 102 can be interchangeable, and the connection relationship can also be interchangeable. For the convenience of description, in the embodiments of the present disclosure below, the first gate 221 is coupled with the first conductive trace 51, and the second gate 222 is coupled with the second conductive trace 52. In specific implementations, the first gate 221 can be coupled with the second conductive trace 52, and the second gate 222 can be coupled with the first conductive trace 51.

[0071] Figure 9An electron microscope schematic diagram of electrostatic shock test of the first gate and the second gate of the display substrate of an embodiment of the present disclosure in the process, Figure 10 For Figure 9 The electrical connection principle diagram of the corresponding electrostatic short circuit ring. In Figure 9 The first conductive trace 51 and the first gate 221 and the second gate 222 are located in the first metal layer, and the second conductive trace 52 is located in the second metal layer (not shown in Figure 9 After the first metal layer and the first insulating layer 23 are formed, the electrostatic generated in the process is transmitted along the first conductive trace 51 before the second metal layer is prepared, and the Figure 9 It can be seen that the edge of the first gate 221 opposite to the second gate 222 (i.e. the right edge of the first gate 221) is shocked at the point E, while the edge of the second gate 222 is not shocked. Referring to Figure 10 And Figure 2 The first insulating layer 23 at the position of the shock point E generates a via hole, so that when the first drain 253 is deposited, the first drain 253 is short-circuited with the first gate 221 through the via hole, resulting in the failure of the first thin film transistor 101, while the second thin film transistor 102 is not shocked and will not fail. Since only one side of the two thin film transistors in the electrostatic short circuit ring fails, and the other side does not fail, the entire electrostatic short circuit ring will not fail, and the first conductive trace 51 and the second conductive trace 52 will not be short-circuited.

[0072] In the related art, both of the two thin film transistors in the electrostatic short circuit ring fail, resulting in the short-circuit of the gate line GL and the first electrostatic discharge line 41 through the electrostatic short circuit ring.

[0073] The technical solution of the present disclosure sets one of the first conductive trace 51 and the second conductive trace 52 in the first metal layer and the other in the second metal layer, so that the first conductive trace 51 and the second conductive trace 52 are in different layers, so that in the process after the first insulating layer 23 is formed and before the second metal layer is formed, the first insulating layer 23 will not be shocked at the opposite edges of the first gate 221 and the second gate 222 due to electrostatic, avoiding the failure of the first thin film transistor 101 and the second thin film transistor 102, and further avoiding the overall failure of the electrostatic short circuit ring, preventing the short-circuit of the first conductive trace 51 and the second conductive trace 52, and reducing the product failure rate.

[0074] In one embodiment, as Figure 7As shown, the first gate 221 and the second gate 222 can be oppositely arranged, for example, the first gate 221 and the second gate 222 are located on the same straight line, the first gate 221 and the second gate 222 can be arranged along a third direction, and the third direction can be the length direction of the first gate 221 and the second gate 222. In this way, the width of the electrostatic short circuit ring can be reduced, and the occupation area of the electrostatic short circuit ring can be reduced.

[0075] In one embodiment, the first gate 221 and the second gate 222 can be arranged along the extension direction of the first conductive trace 51 or the second conductive trace 52.

[0076] As shown in Figure 6 and Figure 7 As shown, the display substrate can further include a gate line GL located in the display area and extending along the first direction, and the first conductive trace 51 includes the gate line GL. The display substrate can further include a first electrostatic discharge line 41 located in the non-display area, and the second conductive trace 52 includes the first electrostatic discharge line 41.

[0077] The at least one electrostatic short circuit ring includes a first electrostatic short circuit ring 11, the first gate 221 in the first electrostatic short circuit ring 11 is coupled with the gate line GL, and the second gate 222 in the first electrostatic short circuit ring 11 is coupled with the first electrostatic discharge line 41. The gate line GL is located in the first metal layer, and the first electrostatic discharge line 41 is located in the second metal layer.

[0078] In the embodiments of the present disclosure, the first electrostatic discharge line 41 is arranged in the second metal layer, and the gate line GL is arranged in the first metal layer, so that the first electrostatic discharge line 41 and the gate line GL are located in different metal layers, thereby, in the process, the first electrostatic short circuit ring 11 does not have the problem of failure of both sides of the thin film transistor, and further, the short circuit of the gate line GL and the first electrostatic discharge line 41 is prevented.

[0079] The display substrate includes a plurality of gate lines GL, and at least two gate lines GL are coupled with the first electrostatic discharge line 41 through corresponding first electrostatic short circuit rings 11. For example, Figure 7 In the embodiments of the present disclosure, the gate line GL i is coupled with the first electrostatic discharge line 41 through a first electrostatic short circuit ring 11a, and the gate line GL j is coupled with the first electrostatic discharge line 41 through another first electrostatic short circuit ring 11b. Since the two first electrostatic short circuit rings 11a and 11b do not have the problem of overall failure, the short circuit of the gate line GL i and the gate line GL j through the first electrostatic discharge line 41 is avoided, and further, the horizontal stripe defect can be avoided.

[0080] Exemplarily, the number of the first electrostatic short circuit rings 11 can be the same as the number of the gate lines GL, the plurality of first electrostatic short circuit rings 11 correspond to the plurality of gate lines GL one by one, and each gate line GL is coupled with the first electrostatic discharge line 41 through a corresponding first electrostatic short circuit ring 11, which is helpful for the release of static electricity.

[0081] As shown in Figure 6 , the first sub-area VA1 can extend along the second direction. The first electrostatic short circuit ring 11 can be located in the first sub-area VA1 without occupying the area of the display area. The first electrostatic discharge line 41 is located in the first sub-area VA1 and extends along the second direction in the first sub-area VA1, and the second direction is perpendicular to the first direction. Here, the first electrostatic discharge line 41 extends along the second direction, which should be understood as that the first electrostatic discharge line 41 extends generally along the second direction. For example, the first electrostatic discharge line 41 can be a straight line extending along the second direction, and can also be a zigzag line or a wavy line extending along the second direction.

[0082] The first sub-area VA1 can be located on opposite sides of the display area AA in the first direction, for example, Figure 6 , the left side and the right side of the display area AA are both provided with the first sub-area VA1. The left end of the gate line GL can be coupled to the first electrostatic discharge line 41 in the left first sub-area VA1 through the corresponding first electrostatic short circuit ring 11, or the right end of the gate line GL can be coupled to the first electrostatic discharge line 41 in the right first sub-area VA1 through the corresponding first electrostatic short circuit ring 11.

[0083] Figure 11 As shown in the enlarged schematic view of the display substrate in one embodiment E part, Figure 6 , the cross-sectional view of C-C in Figure 12 , the cross-sectional view of C-C in Figure 11 , as shown in Figure 6 , Figure 11 and Figure 12 , the display substrate can further include a data line DL located in the display area AA and extending along the second direction, and the second conductive trace 52 includes the data line DL. The display substrate further includes a second electrostatic discharge line 42 located in the non-display area, and the first conductive trace 51 includes the second electrostatic discharge line 42.

[0084] The at least one electrostatic short circuit ring includes a second electrostatic short circuit ring 12, and the first gate 221 in the second electrostatic short circuit ring 12 is coupled to the second electrostatic discharge line 42, and the second gate 222 in the second electrostatic short circuit ring 12 is coupled to the data line DL. The second electrostatic discharge line 42 is located in the first metal layer, and the data line DL is located in the second metal layer.

[0085] In the embodiments of the present disclosure, the second electrostatic discharge line 42 and the data line DL are located in different metal layers, so that in the process, the second electrostatic short circuit ring 12 does not cause the failure of both sides of the thin film transistor, thereby preventing the short circuit of the data line DL and the second electrostatic discharge line 42.

[0086] The display substrate includes a plurality of data lines DL, and each of the at least two data lines DL is coupled to the second static discharge line 42 through a corresponding second static short circuit ring 12. Since the two second static short circuit rings 12 do not cause overall failure problems, the two data lines DL are prevented from being short-circuited through the second static discharge line 42, and thus the vertical stripe defect can be avoided.

[0087] Exemplarily, the number of the second static short circuit rings 12 can be the same as the number of the data lines DL, and the plurality of second static short circuit rings 12 correspond to the plurality of data lines DL one by one, and each data line DL is coupled to the second static discharge line 42 through a corresponding second static short circuit ring 12, which is helpful for the release of static electricity.

[0088] As shown in Figure 6 , the second sub-region VA2 can extend along the first direction. The second static short circuit ring 12 can be located in the second sub-region VA2 and does not occupy the area of the display region. The second static discharge line 42 is located in the second sub-region VA2 and extends along the first direction in the second sub-region VA2. Here, the second static discharge line 42 extending along the first direction should be understood as extending generally along the first direction. For example, the second static discharge line 42 can be a straight line extending along the first direction, and can also be a zigzag line or a wavy line extending along the first direction.

[0089] In one embodiment, the third sub-region VA3 can also be provided with the second static discharge line 42. The upper end of the data line DL can be coupled to the second static discharge line 42 in the second sub-region VA2 through the corresponding second static short circuit ring 12, or the lower end of the data line DL can be coupled to the second static discharge line 42 in the third sub-region VA3 through the corresponding second static short circuit ring 12.

[0090] It should be noted that, Figure 6 , the first sub-region VA1 shows one first static discharge line 41, and the second sub-region VA2 and the third sub-region VA3 each show one second static discharge line 42. It can be understood that the specific number and length of the first static discharge line 41 or the second static discharge line 42 can be set as needed, Figure 6 and cannot be understood as a limitation on the number.

[0091] Figure 13 This is a plan view of a display substrate in another embodiment of the present disclosure. As shown in Figure 6 and Figure 13 , the non-display region can include the first sub-region VA1 and the second sub-region VA2, the first static discharge line 41 is located in the first sub-region VA1, the second static discharge line 42 is located in the second sub-region VA2, the first conductive trace 51 includes the second static discharge line 42, and the second conductive trace 52 includes the first static discharge line 41.

[0092] The at least one electrostatic short circuit ring includes a third electrostatic short circuit ring 13, a first gate 221 in the third electrostatic short circuit ring 13 is coupled with the second electrostatic discharge wire 42, and a second gate 222 in the third electrostatic short circuit ring 13 is coupled with the first electrostatic discharge wire 41. The second electrostatic discharge wire 42 is located in the first metal layer, and the first electrostatic discharge wire 41 is located in the second metal layer.

[0093] The first electrostatic discharge wire 41 and the second electrostatic discharge wire 42 are arranged in layers and connected by the third electrostatic short circuit ring 13. In normal operation, electrostatic on one of the first electrostatic discharge wire 41 and the second electrostatic discharge wire 42 can be prevented from entering the other to affect product performance. In the presence of static electricity, electrostatic on the first electrostatic discharge wire 41 or the second electrostatic discharge wire 42 can be transmitted to each other through the third electrostatic short circuit ring 13 without affecting the release of static electricity.

[0094] In Figure 6 In an embodiment, the display substrate can further include a release jumper 53, which can be located in the non-display area. The second electrostatic discharge wire 42 is coupled with the first electrostatic discharge wire 41 through the third electrostatic short circuit ring 13 and the release jumper 53. For example, the first gate 221 in the third electrostatic short circuit ring 13 is coupled with the second electrostatic discharge wire 42, the second gate 222 in the third electrostatic short circuit ring 13 is coupled with the release jumper 53, and the release jumper 53 is coupled with the first electrostatic discharge wire 41 through the sixth electrostatic short circuit ring 16.

[0095] In Figure 6 In an embodiment, the release jumper 53 can be located in the first metal layer or in the second metal layer. The first gate 221 in the sixth electrostatic short circuit ring 16 is coupled with the first electrostatic discharge wire 41, and the second gate 222 in the sixth electrostatic short circuit ring 16 is coupled with the release jumper 53.

[0096] It can be understood that the length of the release jumper 53 is much smaller than that of the first electrostatic discharge wire 41 and the second electrostatic discharge wire 42. Therefore, when the release jumper 53 is located in the first metal layer, the third electrostatic short circuit ring 13 connected between the second electrostatic discharge wire 42 and the release jumper 53 will not fail as a whole. Similarly, when the release jumper 53 is located in the second metal layer, the sixth electrostatic short circuit ring 16 connected between the first electrostatic discharge wire 41 and the release jumper 53 will also not fail as a whole.

[0097] As Figure 6As shown, the third sub-region VA3 may include a bonding area BA, which includes a ground signal pin GND. The display substrate also includes a third electrostatic discharge line 43 located in the third sub-region VA3, which is coupled to the ground signal pin GND. The first conductive trace 51 also includes the third electrostatic discharge line 43.

[0098] At least one electrostatic short-circuit ring further includes a fourth electrostatic short-circuit ring 14, wherein a first gate 221 in the fourth electrostatic short-circuit ring 14 is coupled to the third electrostatic discharge line 43, a second gate 222 in the fourth electrostatic short-circuit ring 14 is coupled to the first electrostatic discharge line 41, and the third electrostatic discharge line 43 is located in the first metal layer.

[0099] Static electricity on the second electrostatic discharge line 42 can be conducted to the first electrostatic discharge line 41 through the third electrostatic short-circuit ring 13. The third electrostatic discharge line 43 is located in the third sub-region VA3. The third electrostatic discharge line 43 is mainly used to conduct static electricity on the first electrostatic discharge line 41 to the ground signal pin GND. Therefore, the length of the third electrostatic discharge line 43 can be set as needed.

[0100] By placing the third electrostatic discharge line 43 on the first metal layer, which is on a different layer than the first electrostatic discharge line 41, the overall failure of the fourth electrostatic short-circuit ring 14 can be avoided, further ensuring the transfer of static electricity between the first electrostatic discharge line 41 and the third electrostatic discharge line 43.

[0101] The length of the third electrostatic discharge line 43 is usually much smaller than that of the first electrostatic discharge line 41 and the second electrostatic discharge line 42. Therefore, the third electrostatic discharge line 43 can also be located in the same metal layer as the first electrostatic discharge line 41. Since the third electrostatic discharge line 43 is smaller in length, it will not cause the fourth electrostatic short-circuit ring 14 to fail as a whole.

[0102] like Figure 6 As shown, the third sub-region VA3 further includes a fourth electrostatic discharge line 44. The at least one electrostatic short-circuit ring also includes a fifth electrostatic short-circuit ring 15, in which a first gate 221 is coupled to the fourth electrostatic discharge line 44, and a second gate 222 is coupled to the third electrostatic discharge line 44. The fourth electrostatic discharge line 44 is located in the first metal layer.

[0103] The third electrostatic discharge line 43 can be symmetrically arranged, and correspondingly, the ground signal pin GND in the bonding area BA can be symmetrically arranged, with the third electrostatic discharge line 43 coupled to the ground signal pin GND on the corresponding side. One end of the fourth electrostatic discharge line 44 can be coupled to the third electrostatic discharge line 43 on one side through a fifth electrostatic short-circuit ring 15, and the other end can be coupled to the third electrostatic discharge line 43 on the other side through another fifth electrostatic short-circuit ring 15. Both ends of the fourth electrostatic discharge line 44 can also be directly connected to the third electrostatic discharge lines 43 on both sides.

[0104] In one embodiment, such as Figure 7 As shown, the first drain 253 and the second drain 254 are connected by a second adapter wire 255, which is located in the second metal layer and extends in a third direction. The orthographic projection of the first drain 253 on the substrate 21 overlaps with the first projection boundary of the first gate 221, that is, at least a portion of the first projection boundary is located inside the orthographic projection of the first drain 253 on the substrate 21. The first projection boundary is the orthographic projection of the boundary of the first gate 221 opposite to the second gate 222 (i.e., the left boundary of the first gate 221) onto the substrate 21.

[0105] The orthographic projection of the second drain 254 onto the substrate 21 overlaps with the second projection boundary of the second gate 222. That is, at least a portion of the second projection boundary lies within the orthographic projection of the second drain 254 onto the substrate 21. The second projection boundary is the orthographic projection of the boundary of the second gate 222 opposite to the first gate 221 (i.e., the right boundary of the second gate 222) onto the substrate 21.

[0106] Figure 14 for Figure 6 The diagram shown is an enlarged view of portion D of the display substrate in another embodiment. Figure 14 In the illustrated embodiment, the orthographic projection of the first drain 253 on the substrate 21 is located on the side of the first projection boundary TB1 of the first gate 221 that is away from the second projection boundary TB2, and the distance between the orthographic projection of the first drain 253 on the substrate 21 and the first projection boundary TB1 is greater than or equal to a first preset distance. The value of the first preset distance can be set as needed.

[0107] like Figure 14 As shown, the first drain 253 is coupled to the second drain 254 through the first adapter wire 255, and the orthographic projection of the first adapter wire 255 on the substrate 21 is located outside the first projection boundary TB1.

[0108] Analysis of relevant technologies shows that the first insulating layer 23 at the first projection boundary position will be damaged, creating a via.

[0109] The configuration of this embodiment allows the first drain 253 and the first adapter line 255 to be far away from the first projection boundary TB1. Even if the first insulating layer 23 at the first projection boundary TB1 is damaged and a via is generated, since the first drain 253 and the first adapter line 255 are far away from the first projection boundary TB1, the problem of the first drain 253 or the first adapter line 255 being short-circuited to the first gate 221 through the via will not occur, thereby avoiding the failure of the first thin film transistor 101.

[0110] The orthographic projection of the second drain 254 on the substrate 21 can be located on the side of the second projection boundary TB2 away from the first projection boundary TB1, and the distance between the orthographic projection of the second drain 254 on the substrate 21 and the second projection boundary TB2 is greater than or equal to the first preset distance. The orthographic projection of the first adapter wire 255 on the substrate 21 is located outside the second projection boundary TB2. In this way, the second drain 254 and the first adapter wire 255 are far away from the second projection boundary TB2. Even if the first insulating layer 23 at the location of the second projection boundary TB2 is damaged and a via is generated, since the second drain and the first adapter wire 255 are far away from the second projection boundary TB2, there will be no problem of the second drain or the first adapter wire 255 being short-circuited to the second gate through the via, thereby avoiding the failure of the second thin film transistor 102.

[0111] The distance between the orthographic projection of the first adapter cable 255 on the substrate 21 and the first projection boundary TB1 is greater than or equal to the first preset distance. The distance between the orthographic projection of the first adapter cable 255 on the substrate 21 and the second projection boundary TB2 is greater than or equal to the first preset distance.

[0112] In the analysis of related technologies, it is understood that electrostatic discharge (ESD) damage is not a single point, but an area. A first preset distance ensures that the first drain electrode 253, the second drain electrode 254, and the first adapter cable 255 avoid the damaged area, thereby preventing short circuits between the first drain electrode 253, the second drain electrode 254, and the first adapter cable 255 and the first drain electrode 253 and the second drain electrode 254. The specific value of the first preset distance can be determined by the size of the damaged area or by experience, as long as it ensures that the first drain electrode 253, the second drain electrode 254, and the first adapter cable 255 avoid the damaged area.

[0113] like Figure 7 As shown, the first active layer 241 and the second active layer 242 are disposed in the same layer and located on the side of the first metal layer away from the substrate 21. The materials of the first active layer 241 and the second active layer 242 may include oxide semiconductors.

[0114] The orthographic projection of the first active layer 241 onto the substrate 21 is located on the side of the first projection boundary TB1 that is away from the second projection boundary TB2, and the distance between the orthographic projection of the first active layer 241 onto the substrate 21 and the first projection boundary TB1 is greater than or equal to the first preset distance. This ensures that the first active layer 241 avoids the damaged area, preventing the first drain 253 from short-circuiting with the first gate 221 through the conductive region of the first active layer 241, further preventing the failure of the first thin-film transistor 101.

[0115] The orthographic projection of the second active layer 242 onto the substrate 21 is located on the side of the second projection boundary TB2 that is away from the first projection boundary TB1, and the distance between the orthographic projection of the second active layer 242 onto the substrate 21 and the second projection boundary TB2 is greater than or equal to the first preset distance. This ensures that the second active layer 242 avoids the damaged area, preventing the second drain 254 from short-circuiting with the second gate 222 through the conductive region of the second active layer 242, further preventing the failure of the second thin-film transistor 102.

[0116] In one embodiment, such as Figure 8 As shown, the first metal layer is located on one side of the substrate 21, the first insulating layer 23 is located on the side of the first metal layer facing away from the substrate 21, and the second metal layer is located on the side of the first insulating layer 23 facing away from the substrate 21. The first active layer 241 and the second active layer 242 are located on the side of the first metal layer facing away from the substrate 21. Thus, both the first thin-film transistor 101 and the second thin-film transistor 102 are bottom-gate thin-film transistors. In other embodiments, both the first thin-film transistor 101 and the second thin-film transistor 102 may be top-gate thin-film transistors.

[0117] like Figure 8 As shown, the display substrate may further include a first passivation layer 26, an organic planarization layer 27, and a third metal layer. The first passivation layer 26 is located on the side of the second metal layer facing away from the substrate 21, the organic planarization layer 27 is located on the side of the first passivation layer 26 facing away from the substrate 21, and the third metal layer is located on the side of the organic planarization layer 27 facing away from the substrate 21. The electrostatic short-circuit ring may further include a shielding portion 28, which is located on the third metal layer. The orthographic projections of the first active layer 241 and the second active layer 242 on the substrate 21 are located within the orthographic projection of the shielding portion 28 on the substrate 21. The display substrate may further include a second passivation layer 29, which is located on the side of the shielding portion 28 facing away from the substrate 21.

[0118] In one embodiment, the gate line GL is located in the first metal layer, that is, the first gate 221 and the second gate 222 are arranged in the same layer as the gate line GL in the display substrate. The data line DL is located in the second metal layer, and the first source 251, the second source 252, the first drain 253 and the second drain 254 are arranged in the same layer as the data line DL in the display substrate.

[0119] In the exemplary embodiments, the first insulating layer, the first passivation layer and the second passivation layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, multiple layers or a composite layer. The first metal layer and the second metal layer can be any one or more of metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure such as Ti / Al / Ti, etc.

[0120] Based on the inventive concept of the foregoing embodiments, the embodiments of the present disclosure further provide a display device including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, wearable display device, etc.

[0121] In the description of the present specification, it should be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “upper”, “lower”, “front”, “rear”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential” and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present disclosure.

[0122] In addition, the terms “first” and “second” are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of “plurality” is two or more, unless otherwise specifically limited.

[0123] In the present disclosure, unless specifically defined otherwise, the terms "mounting", "connection", "connecting", "fixed", and like terms should be construed broadly and, for example, can be a fixed connection, or detachable connection, or integral; can be a mechanical connection, or electrical connection, or communication; can be direct connection, or indirect connection through an intermediate medium; can be internal connection of two elements, or interaction relationship between two elements. For those skilled in the art, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances.

[0124] In the present disclosure, unless specifically defined otherwise, "on" or "under" of a first feature to a second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, "on", "above" and "over" of a first feature to a second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the first feature is higher than the second feature in horizontal height. "Under", "below" and "underneath" of a first feature to a second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the first feature is lower than the second feature in horizontal height.

[0125] The above disclosure provides many different embodiments or examples for implementing different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0126] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any skilled person in the art can easily think of various changes or replacements within the technical scope disclosed by the present disclosure, and different parts in different embodiments can be combined with each other without conflict, which should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, characterized by, The display substrate comprises a display area and a non-display area outside the display area, and comprises: a substrate; at least one electrostatic short circuit ring located on one side of the substrate and in the non-display area, the electrostatic short circuit ring comprising a first thin film transistor and a second thin film transistor, a first gate of the first thin film transistor and a second gate of the second thin film transistor are both located in a first metal layer, a first source in the first thin film transistor is coupled with the first gate, a second source in the second thin film transistor is coupled with the second gate, a first drain of the first thin film transistor is coupled with a second drain of the second thin film transistor, the first drain and the second drain are located between the first source and the second source, the first source, the second source, the first drain and the second drain are all located in a second metal layer, the second metal layer is located on a side of the first metal layer away from the substrate, and a first insulating layer is arranged between the second metal layer and the first metal layer; a first conductive trace and a second conductive trace, both located on a side of the substrate facing the electrostatic short circuit ring, the first gate is coupled with one of the first conductive trace and the second conductive trace, the second gate is coupled with the other of the first conductive trace and the second conductive trace, one of the first conductive trace and the second conductive trace is located in the first metal layer, and the other is located in the second metal layer.

2. The display substrate of claim 1, wherein, Further comprising a gate line located in the display area and extending in a first direction, and the first conductive trace comprises the gate line; The display substrate further comprises a first electrostatic discharge line located in the non-display area, and the second conductive trace comprises the first electrostatic discharge line; The at least one electrostatic short circuit ring comprises a first electrostatic short circuit ring, the first gate in the first electrostatic short circuit ring is coupled with the gate line, and the second gate in the first electrostatic short circuit ring is coupled with the first electrostatic discharge line; the gate line is located in the first metal layer, and the first electrostatic discharge line is located in the second metal layer. 3.The display substrate of claim 2, wherein, The non-display area comprises a first sub-area extending in a second direction, the first electrostatic short circuit ring is located in the first sub-area, and the first electrostatic discharge line is located in the first sub-area and extends in the second direction within the first sub-area, and the second direction is perpendicular to the first direction.

4. The display substrate of claim 1, wherein, Further comprising a data line located in the display area and extending in a second direction, and the second conductive trace comprises the data line; The display substrate further comprises a second electrostatic discharge line located in the non-display area, and the first conductive trace comprises the second electrostatic discharge line; The at least one electrostatic short circuit ring comprises a second electrostatic short circuit ring, the first gate in the second electrostatic short circuit ring is coupled with the second electrostatic discharge line, and the second gate in the second electrostatic short circuit ring is coupled with the data line; the second electrostatic discharge line is located in the first metal layer, and the data line is located in the second metal layer.

5. The display substrate of claim 4, wherein, The non-display area includes a second sub-area extending along a first direction, the second electrostatic short circuit ring is located in the second sub-area, and the second electrostatic discharge wire is located in the second sub-area and extends along the first direction in the second sub-area, the second direction being perpendicular to the first direction.

6. The display substrate according to any one of claims 1-5, wherein, The non-display area includes a second sub-area extending along a first direction and a first sub-area extending along a second direction, the second direction being perpendicular to the first direction. The display substrate includes a first electrostatic discharge wire located in the first sub-area and a second electrostatic discharge wire located in the second sub-area, the first conductive trace including the second electrostatic discharge wire, and the second conductive trace including the first electrostatic discharge wire. The at least one electrostatic short circuit ring includes a third electrostatic short circuit ring, a first gate in the third electrostatic short circuit ring being coupled with the second electrostatic discharge wire, and a second gate in the third electrostatic short circuit ring being coupled with the first electrostatic discharge wire; the second electrostatic discharge wire being located in the first metal layer, and the first electrostatic discharge wire being located in the second metal layer.

7. The display substrate of claim 6, wherein, The first electrostatic discharge wire extends along the second direction in the first sub-area, and the second electrostatic discharge wire extends along the first direction in the second sub-area. 8.The display substrate of claim 6, wherein, The non-display area further includes a third sub-area extending along the first direction, the third sub-area and the second sub-area being located on opposite sides of the display area respectively, the third sub-area including a binding area, and the binding area including a ground signal pin. The display substrate further includes a third electrostatic discharge wire located in the third sub-area, the third electrostatic discharge wire being coupled with the ground signal pin, and the first conductive trace further including the third electrostatic discharge wire. The at least one electrostatic short circuit ring further includes a fourth electrostatic short circuit ring, a first gate in the fourth electrostatic short circuit ring being coupled with the third electrostatic discharge wire, and a second gate in the fourth electrostatic short circuit ring being coupled with the first electrostatic discharge wire; the third electrostatic discharge wire being located in the first metal layer. 9.The display substrate of claim 8, wherein, The third sub-area further includes a fourth electrostatic discharge wire, the at least one electrostatic short circuit ring further including a fifth electrostatic short circuit ring, a first gate in the fifth electrostatic short circuit ring being coupled with the fourth electrostatic discharge wire, and a second gate in the fifth electrostatic short circuit ring being coupled with the third electrostatic discharge wire; the fourth electrostatic discharge wire being located in the first metal layer. 10.The display substrate of claim 1, wherein, A projection of the first drain on the substrate is located on a side of a first projection boundary of the first gate away from a second projection boundary, and a distance between the projection of the first drain on the substrate and the first projection boundary is greater than or equal to a first preset distance, the first projection boundary being a projection on the substrate of a boundary of the first gate opposite to the second gate, and the second projection boundary being a projection on the substrate of a boundary of the second gate opposite to the first gate. The first drain is coupled with the second drain through a first adapter line, and a projection of the first adapter line on the substrate is located outside the first projection boundary. 11.The display substrate of claim 10, wherein, The orthographic projection of the second drain electrode on the substrate is located on a side of the second projection boundary away from the first projection boundary, and a distance between the orthographic projection of the second drain electrode on the substrate and the second projection boundary is greater than or equal to the first preset distance, and the orthographic projection of the first transfer line on the substrate is located outside the second projection boundary.

12. The display substrate of claim 11, wherein, a distance between the orthographic projection of the first transfer line on the substrate and the first projection boundary is greater than or equal to the first preset distance; and / or, a distance between the orthographic projection of the first transfer line on the substrate and the second projection boundary is greater than or equal to the first preset distance. 13.The display substrate of claim 10, wherein, The first thin film transistor further comprises a first active layer, and the second thin film transistor further comprises a second active layer, and the first active layer and the second active layer are arranged in the same layer and located on a side of the first metal layer away from the substrate; the orthographic projection of the first active layer on the substrate is located on a side of the first projection boundary away from the second projection boundary, and a distance between the orthographic projection of the first active layer on the substrate and the first projection boundary is greater than or equal to the first preset distance; and / or, the orthographic projection of the second active layer on the substrate is located on a side of the second projection boundary away from the first projection boundary, and a distance between the orthographic projection of the second active layer on the substrate and the second projection boundary is greater than or equal to the first preset distance. 14.The display substrate of claim 1, wherein, The display substrate comprises gate lines and data lines in the display area, the gate lines are located on the first metal layer, and the data lines are located on the second metal layer.

15. A display device comprising: The display substrate comprises the display substrate according to any one of claims 1-14. The display substrate comprises the display substrate according to any one of claims 1-14.

Images