Universal data acquisition preprocessing simulation control daughter card

Abstract

The utility model relates to the technical field of data acquisition, in particular to a universal data acquisition preprocessing simulation control daughter card. Comprising a master control module, a power conversion unit, a clock unit and an interface unit. The system is used for controlling various ADC acquisition chips, the ZYNQ chip is adopted to realize the connection of the SPI, the LVTTL discrete line, the 16-bit parallel port, the LVDS interface and the JESD204B interface with the ADC chip of an external acquisition system, a main data acquisition system is assisted to carry out signal preprocessing and execute preliminary data processing or analysis, the function of the main acquisition system is enhanced, and the data acquisition efficiency is improved. And more accurate signal conditioning and faster data processing capability are provided.

Description

Technical Field

[0001] This utility model relates to the field of data acquisition technology, and more specifically, to a general-purpose data acquisition preprocessing simulation control sub-card. Background Technology

[0002] Using ADC chips for data acquisition is an indispensable part of modern information technology and automation systems.

[0003] By performing preprocessing simulations on the data acquisition system during data acquisition, the speed, accuracy, and quality of data acquisition can be improved. Traditional data acquisition preprocessing simulations are mainly performed through the main acquisition system, which cannot accurately analyze the performance indicators of the data acquisition function and cannot meet the needs of data acquisition preprocessing simulations for a wider range of acquisition systems. Utility Model Content

[0004] This invention addresses the problem that existing data acquisition and preprocessing simulations are mainly performed through the main acquisition system, which cannot accurately analyze the performance indicators of the data acquisition function and cannot meet the needs of data acquisition and preprocessing simulations for a wider range of acquisition systems. It proposes a universal data acquisition and preprocessing simulation control sub-card. The hardware architecture uses ZYNQ as the main control chip and employs a PS+PL approach to flexibly assist in the preprocessing of acquired signals and signal quality analysis. A universal control interface design is used to configure and control various types of ADC acquisition chips.

[0005] The specific implementation details of this utility model are as follows:

[0006] A general-purpose data acquisition and preprocessing simulation control daughter card, which connects to an external ADC acquisition system; includes a main control module, a power conversion unit, a clock unit, and an interface unit;

[0007] The input terminal of the power conversion unit is connected to an external power source, and the output terminal of the power conversion unit is connected to the main control module, the clock unit, and the interface unit.

[0008] The output of the clock unit is connected to the main control module;

[0009] The interface unit is connected to the main control module;

[0010] The power conversion unit is used to convert the input external power supply into multiple operating voltages;

[0011] The clock unit is used to generate a reference clock;

[0012] The interface unit is used to implement a network interface and an RS322 interface with the main control module;

[0013] The main control module connects to an external ADC acquisition system via a connector to control the ADC chip and configure its registers, and performs preprocessing simulation and data processing analysis on the data acquired from the ADC chip.

[0014] To better realize this utility model, the main control module further includes a ZYNQ chip, a DDR chip, an EMMC chip, and a FLASH chip;

[0015] The Bank502 interface on the PS side of the ZYNQ chip is connected to the DDR chip;

[0016] The Bank501 interface of the ZYNQ chip is connected to the EMMC chip;

[0017] The Bank500 interface of the ZYNQ chip is connected to the FLASH chip.

[0018] To better realize this utility model, the power conversion unit further includes an LTM4644 chip;

[0019] The LTM4644 chip receives a 12V input and outputs 1.0V, 1.2V, 1.8V, and 3.3V.

[0020] To better realize this utility model, the clock unit further includes a first crystal oscillator unit, a second crystal oscillator unit, and a clock driver chip;

[0021] The output terminal of the first crystal oscillator unit is connected to the ZYNQ chip;

[0022] The output of the second crystal oscillator unit is connected to the clock driver chip;

[0023] The clock driver chip is connected to the PHY chip and to the ZYNQ chip via the SPI bus.

[0024] To better realize this utility model, the interface unit further includes a network interface, an RS232 serial port, and an external connector;

[0025] The ZYNQ chip's PS terminal RGMII interface connects to the PHY chip to enable network communication.

[0026] The ZYNQ chip's PS terminal UART interface is connected to the MAX3232 chip to achieve RS232 serial communication.

[0027] The network interface and RS232 serial port are connected to the PC, and the ADC chip configuration and control command issuance, data acquisition reception and analysis are completed through the PC.

[0028] The ZYNQ chip is connected to an external ADC acquisition system via an external connector.

[0029] To better realize this utility model, the ZYNQ chip further includes an external interface;

[0030] The external interfaces include SPI interface, LVTTL discrete line interface, 16-bit parallel port, LVDS interface and JESD204B interface.

[0031] To better realize this utility model, the ZYNQ chip is further described as an XC7Z030-2FFG676I chip.

[0032] This utility model has the following beneficial effects:

[0033] (1) This utility model uses ZYNQ chip to realize SPI, LVTTL discrete line, 16-bit parallel port, LVDS interface and JESD204B interface to connect with the ADC chip of external acquisition system, assist the main data acquisition system to perform signal preprocessing and perform preliminary data processing or analysis, and enhance the function of the main acquisition system.

[0034] (2) This utility model has multiple ADC acquisition chip interface types to meet the data acquisition and preprocessing simulation requirements of various acquisition systems. Attached Figure Description

[0035] Figure 1 A schematic block diagram of the structure provided for this utility model.

[0036] Figure 2 A schematic diagram of the power conversion circuit provided by this utility model.

[0037] Figure 3 A schematic diagram of the crystal oscillator circuit provided by this utility model.

[0038] Figure 4 The schematic diagram of the clock drive circuit provided by this utility model.

[0039] Figure 5 The schematic diagram of the network interface circuit provided by this utility model.

[0040] Figure 6 The schematic diagram of the RS232 interface circuit provided by this utility model. Detailed Implementation

[0041] To more clearly illustrate the technical solutions of the embodiments of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of this utility model, not all embodiments, and therefore should not be regarded as a limitation on the scope of protection. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0042] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0043] Example 1:

[0044] This embodiment proposes a general data acquisition and preprocessing simulation control sub-card, such as... Figure 1 As shown, it connects to an external ADC acquisition system; it includes a main control module, a power conversion unit, a clock unit, and an interface unit.

[0045] The input terminal of the power conversion unit is connected to an external power source, and the output terminal of the power conversion unit is connected to the main control module, the clock unit, and the interface unit.

[0046] The output of the clock unit is connected to the main control module;

[0047] The interface unit is connected to the main control module;

[0048] The power conversion unit is used to convert the input external power supply into multiple operating voltages;

[0049] The clock unit is used to generate a reference clock;

[0050] The interface unit is used to implement a network interface and an RS322 interface with the main control module;

[0051] The main control module connects to an external ADC acquisition system via a connector to control the ADC chip and configure its registers, and performs preprocessing simulation and data processing analysis on the data acquired from the ADC chip.

[0052] Working Principle: This embodiment uses a ZYNQ chip as the main control chip, employing a PS+PL approach to flexibly assist in the preprocessing and signal quality analysis of the acquired signals. This is used for preprocessing simulation control of the ADC chip during data acquisition, ensuring the quality of the acquired data and preparing for subsequent data analysis. A universal control interface design is adopted to configure and control various types of ADC acquisition chips. The power conversion unit provides power to the daughter card chip and various functional circuits; the clock unit connects to the ZYNQ and PHY chip, providing them with the correct clock signal; the interface unit connects to the ZYNQ to implement network and RS232 interfaces.

[0053] Example 2:

[0054] This embodiment is based on the above embodiment 1, such as... Figure 1 As shown, the specific structure of the main control module is described in detail using a specific embodiment.

[0055] The main control module includes a ZYNQ chip, a DDR chip, an eMMC chip, and a FLASH chip;

[0056] The Bank502 interface on the PS side of the ZYNQ chip is connected to the DDR chip;

[0057] The Bank501 interface of the ZYNQ chip is connected to the EMMC chip;

[0058] The Bank500 interface of the ZYNQ chip is connected to the FLASH chip.

[0059] The ZYNQ chip includes an external interface;

[0060] The external interfaces include SPI interface, LVTTL discrete line interface, 16-bit parallel port, LVDS interface and JESD204B interface.

[0061] Working Principle: In this embodiment, the ZYNQ unit serves as the core unit of the daughter card, connecting with the DDR chip, eMMC chip, and FLASH chip to form the main control system. It connects to an external ADC data acquisition module via an SFM-150-02-SDA connector. This embodiment uses the XC7Z030-2FFG676I chip for the ZYNQ unit. The ZYNQ PS terminal's Bank502 interface connects to the DDR chip (MT41K256M16TW), the Bank501 interface connects to the eMMC chip (MTFC32GAKAEDQ), and the Bank500 interface connects to the FLASH chip (S25FL256SAGMFIR) to form the main control system. The ZYNQ PS terminal's RGMII interface connects to the PHY chip to implement the network interface, and the UART interface connects to the RS232 chip to implement the RS232 serial port. ZYNQ's external interfaces include SPI, LVTTL discrete line, 16-bit parallel port, LVDS, and JESD204B. It connects to an external ADC acquisition system via a connector to control the ADC chip and configure its registers. Simultaneously, the ADC chip acquires data and transmits it to ZYNQ for preprocessing simulation and data processing analysis.

[0062] The other parts of this embodiment are the same as those in Embodiment 1 above, so they will not be described again.

[0063] Example 3:

[0064] This embodiment is based on any one of Embodiments 1-2 above, such as Figure 2 As shown, the specific structure of the power conversion unit is described in detail with reference to a specific embodiment.

[0065] The power conversion unit includes an LTM4644 chip;

[0066] The LTM4644 chip receives a 12V input and outputs 1.0V, 1.2V, 1.8V, and 3.3V.

[0067] Working principle: The data acquisition, preprocessing, simulation, and control daughter card in this embodiment requires multiple voltages. The LTM4644 chip is used to convert the external 12V voltage to 1.0V, 1.2V, 1.8V, and 3.3V to power the various functional circuits and chips of the daughter card.

[0068] The other parts of this embodiment are the same as any one of the above embodiments 1-2, so they will not be described again.

[0069] Example 4:

[0070] This embodiment is based on any one of embodiments 1-3 above, such as Figure 3 , Figure 4As shown, the structure of the clock unit is illustrated with a specific embodiment.

[0071] The clock unit includes a first crystal oscillator unit, a second crystal oscillator unit, and a clock driver chip;

[0072] The output terminal of the first crystal oscillator unit is connected to the ZYNQ chip;

[0073] The output of the second crystal oscillator unit is connected to the clock driver chip;

[0074] The clock driver chip is connected to the PHY chip and to the ZYNQ chip via the SPI bus.

[0075] Working principle: In this embodiment, both the ZYNQ unit and the PHY chip of the data acquisition, preprocessing, simulation, and control daughter card require the use of multiple independent reference clocks. The XO53-YAGRC-50MHz crystal oscillator is used to provide the system operating clock for the ZYNQ chip, and the XO75P-AGRP-100MHz crystal oscillator is used in conjunction with the clock driver chip AD9516-3BCPZ. The ZYNQ chip and the clock driver chip are connected via an SPI bus. After configuring the AD9516-3BCPZ chip register, a 25MHz operating clock is provided to the PHY chip and a high-speed differential clock is provided to the ZYNQ chip's GTX Bank.

[0076] The other parts of this embodiment are the same as any one of the embodiments 1-3 above, so they will not be described again.

[0077] Example 5:

[0078] This embodiment is based on any one of embodiments 1-4 above, such as Figure 5 , Figure 6 As shown, the specific structure of the interface unit is described in detail with reference to a specific embodiment.

[0079] The interface unit includes a network interface, an RS232 serial port, and an external connector;

[0080] The ZYNQ chip's PS terminal RGMII interface connects to the PHY chip to enable network communication.

[0081] The ZYNQ chip's PS terminal UART interface is connected to the MAX3232 chip to achieve RS232 serial communication.

[0082] The network interface and RS232 serial port are connected to the PC, and the ADC chip configuration and control command issuance, data acquisition reception and analysis are completed through the PC.

[0083] The ZYNQ chip is connected to an external ADC acquisition system via an external connector.

[0084] Working Principle: The data acquisition, preprocessing, simulation, and control daughter card interface unit in this embodiment includes a network interface, an RS232 serial port, and an external connector. The ZYNQ PS-side RGMII interface connects to the PHY chip 88E1512 for network communication; the ZYNQ PS-side UART interface connects to the MAX3232 chip for RS232 serial communication. The network interface and RS232 serial port are used to connect to a PC, through which ADC chip configuration, control command issuance, data reception, and analysis are completed. The external connector SFM-150-02-SDA enables interconnection with various external ADC acquisition systems.

[0085] The data acquisition and preprocessing simulation control daughter card uses ZYNQ as the main control chip. It connects one SPI signal, 20 LVTTL signals, 16-bit parallel port signal, two synchronous interface signals, 16 LVDS signals, and one JESD204B signal to the SFM-150-02-SDA connector. It interconnects with the data acquisition and preprocessing simulation control daughter card according to the interface type of the external acquisition system's ADC chip. The data acquisition and preprocessing simulation control daughter card controls and configures the external ADC chip. The external ADC chip transmits the acquired data to the data acquisition and preprocessing simulation control daughter card through the 16-bit parallel port, LVDS interface, or JESD204B interface. The data acquisition and preprocessing simulation control daughter card performs preprocessing simulation of the acquired signals and performs preliminary data processing or analysis.

[0086] This embodiment features multiple ADC acquisition chip interface types to meet the data acquisition preprocessing simulation requirements of various acquisition systems. It is typically used to control multiple ADC acquisition chips, assisting the main data acquisition system in signal preprocessing and performing preliminary data processing or analysis. This can enhance the functionality of the main acquisition system and provide more accurate signal conditioning and faster data processing capabilities.

[0087] The other parts of this embodiment are the same as any one of the embodiments 1-4 above, so they will not be described again.

[0088] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present utility model shall fall within the protection scope of the present utility model.

Claims

1. A general-purpose data acquisition and preprocessing simulation control daughter card, connected to an external ADC acquisition system; characterized in that, Includes main control module, power conversion unit, clock unit, and interface unit; The input terminal of the power conversion unit is connected to an external power source, and the output terminal of the power conversion unit is connected to the main control module, the clock unit, and the interface unit. The output of the clock unit is connected to the main control module; The interface unit is connected to the main control module; The power conversion unit is used to convert the input external power supply into multiple operating voltages; The clock unit is used to generate a reference clock; The interface unit is used to implement a network interface and an RS322 interface with the main control module; The main control module connects to an external ADC acquisition system via a connector to control the ADC chip and configure its registers, and performs preprocessing simulation and data processing analysis on the data acquired from the ADC chip.

2. The general-purpose data acquisition preprocessing simulation control sub-card according to claim 1, characterized in that, The main control module includes a ZYNQ chip, a DDR chip, an eMMC chip, and a FLASH chip; The Bank502 interface on the PS side of the ZYNQ chip is connected to the DDR chip; The Bank501 interface of the ZYNQ chip is connected to the EMMC chip; The Bank500 interface of the ZYNQ chip is connected to the FLASH chip.

3. A general-purpose data acquisition, preprocessing, simulation control sub-card according to claim 1, characterized in that, The power conversion unit includes an LTM4644 chip; The LTM4644 chip receives a 12V input and outputs 1.0V, 1.2V, 1.8V, and 3.3V.

4. A general-purpose data acquisition preprocessing simulation control sub-card according to claim 2, characterized in that, The clock unit includes a first crystal oscillator unit, a second crystal oscillator unit, and a clock driver chip; The output terminal of the first crystal oscillator unit is connected to the ZYNQ chip; The output of the second crystal oscillator unit is connected to the clock driver chip; The clock driver chip is connected to the PHY chip and to the ZYNQ chip via the SPI bus.

5. A general-purpose data acquisition preprocessing simulation control sub-card according to claim 2, characterized in that, The interface unit includes a network interface, an RS232 serial port, and an external connector; The ZYNQ chip's PS terminal RGMII interface connects to the PHY chip to enable network communication. The ZYNQ chip's PS terminal UART interface is connected to the MAX3232 chip to achieve RS232 serial communication. The network interface and RS232 serial port are connected to the PC, and the ADC chip configuration and control command issuance, data acquisition reception and analysis are completed through the PC. The ZYNQ chip is connected to an external ADC acquisition system via an external connector.

6. A general-purpose data acquisition preprocessing simulation control sub-card according to claim 2, characterized in that, The ZYNQ chip includes an external interface; The external interfaces include SPI interface, LVTTL discrete line interface, 16-bit parallel port, LVDS interface and JESD204B interface.

7. The universal data acquisition preprocessing simulation control sub-card according to claim 2, 4, 5, or 6, characterized in that, The ZYNQ chip is an XC7Z030-2FFG676I chip.

Images