Film layer interconnection structure, array substrate and liquid crystal display device
Patent Information
- Application Number
- CN202520116360.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-17
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-01-17
AI Technical Summary
The existing LCD panel manufacturing process is complex, with high on-resistance through-holes and the risk of functional loss, affecting production efficiency and cost.
Through-holes are set between functional film layers and filled with implanted material by ion implantation. The doped material is controlled to achieve film layer conductivity and reduce on-resistance.
Simplify the process flow, reduce on-resistance, improve production efficiency and product yield, and reduce costs.
Smart Images
Figure CN223842266U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of testing technology for through-hole connections in liquid crystal displays, and particularly to a film interconnect structure, an array substrate, and a liquid crystal display device. Background Technology
[0002] After a long period of development, LCD panel manufacturing has become a consumer product closely related to people's lives, penetrating into all aspects of our lives. LCD display manufacturing technology has also become increasingly mature. How to continuously reduce the manufacturing cost of LCD panels remains a key technology area that major panel manufacturers are vying to research.
[0003] In current LCD panel manufacturing, the integration of functional circuits requires the integration of multiple layers of conductive lines, with insulating layers used to isolate each layer. The interconnection process between these layers is as follows: First, the first functional circuit layer is deposited, followed by coating, exposure, development, etching, and film removal to complete the patterning of the first functional circuit. Next, an insulating film, typically silicon nitride, silicon oxide, or an organic film, is deposited, and vias are created by repeating the above steps. Finally, the second functional circuit layer is fabricated, thus achieving connection and conductivity between the first and second functional circuit layers through vias.
[0004] Problems with existing technology:
[0005] 1. The complex process flow is not conducive to improving production efficiency and reducing production costs:
[0006] 2. Vias are usually sloped. The slope of the second circuit layer will increase the on-resistance at that position. If the production process fluctuates and undercut occurs, it will directly lead to the loss of conduction function and result in a loss of product yield. Utility Model Content
[0007] Existing LCD panels have high on-resistance between interlayer vias, and there is also a risk of functional loss.
[0008] To address the aforementioned issues, a film interconnect structure, an array substrate, and a liquid crystal display device are proposed. By setting through holes in two functional film layers and filling them with implanted material through ion implantation, the two functional film layers become conductive. By controlling the dopant of the implanted material, the on-resistance can be reduced.
[0009] In a first aspect, a film interconnect structure includes:
[0010] First membrane layer pattern;
[0011] Second film layer pattern;
[0012] Spacer layer;
[0013] Through hole;
[0014] Injecting material;
[0015] The spacer layer is used to isolate or insulate the first film pattern from the second film pattern. The via is formed at the connection position between the first film pattern and the second film pattern. The implanted material is injected into the via by ion implantation, so that the first film pattern and the second film pattern are connected.
[0016] In conjunction with the film interconnect structure described in the first aspect of this utility model, in a first possible embodiment, the first film pattern is a common electrode layer, the spacer layer is a planarization layer, the second film pattern is an SD layer, the first film pattern is fabricated on the planarization layer, the second film pattern is fabricated in the planarization layer, and the via passes through the planarization layer.
[0017] In conjunction with the film interconnect structure described in the first aspect of this utility model, in a second possible embodiment, the first film pattern is a common electrode layer, the spacer layer includes a planarization layer, an isolation layer and an insulating layer, the second film pattern is a gate layer, the first film pattern is formed on the planarization layer, the planarization layer is formed on the isolation layer, the isolation layer is formed on the insulating layer, the second film pattern is formed in the insulating layer, the insulating layer is formed on a glass substrate, and the via passes through the planarization layer, the isolation layer and the insulating layer.
[0018] In conjunction with the first or second possible implementation of the first aspect of this utility model, and in the third possible implementation, the injected substance is one or more of phosphine and borane.
[0019] In conjunction with the second possible implementation of the first aspect of this utility model, in the fourth possible implementation, the insulating layer is amorphous silicon, polycrystalline silicon, silicon nitride, or silicon oxide.
[0020] In a second aspect, an array substrate includes the film interconnect structure described in the first aspect, wherein it further includes:
[0021] passivation layer;
[0022] Pixel electrode layer;
[0023] The common electrode layer is fabricated in the passivation layer, and the pixel electrode layer is fabricated on the passivation layer.
[0024] Thirdly, a liquid crystal display device includes the array substrate described in the second aspect.
[0025] The present invention provides a film interconnect structure, array substrate, and liquid crystal display device. By setting through holes in two functional film layers and filling them with implanted material through ion implantation, the two functional film layers are made conductive. By controlling the dopant of the implanted material, the on-resistance can be reduced. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a schematic diagram of a specific embodiment of the fabrication process of a film interconnect structure in the prior art;
[0028] Figure 2 This is a schematic diagram of a specific embodiment of the fabrication process of the film interconnect structure in this application;
[0029] Figure 3 This is a schematic diagram of a specific embodiment of an array substrate fabricated using the film interconnect structure fabrication process described in this application. Detailed Implementation
[0030] The technical solutions of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, other embodiments obtained by those skilled in the art without creative effort are all within the scope of protection of this utility model.
[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0032] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0033] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0035] Existing LCD panels have high on-resistance between interlayer vias, and there is also a risk of functional loss.
[0036] like Figure 1 , Figure 1 This is a schematic diagram of a specific embodiment of the fabrication process for a film-layer interconnect structure in the prior art. First, a functional circuit of the first film layer pattern M1 is formed. Then, after coating, exposure, development, etching, and film removal, the first film layer pattern M1 is completed. Next, an insulating film, typically silicon nitride, silicon oxide, or an organic film, is deposited, and vias are created by repeating the above steps. Finally, the functional circuit of the second film layer pattern M2 is fabricated, thus achieving connection and conductivity between the first and second layer functional circuits through vias. In the above scheme, the via connection material structure is formed, and the doping material is difficult to control. In some extreme cases, the vias often exhibit a ramp-like shape. The ramp-like shape of the second film layer pattern M2 will lead to increased conductivity at that location. If fluctuations occur during the production process and undercut occurs, it will directly lead to loss of conductivity, resulting in a loss of product yield.
[0037] To address the above problems, a film interconnect structure, an array substrate, and a liquid crystal display device are proposed.
[0038] In a first aspect, a film interconnect structure includes a first film pattern M1, a second film pattern M2, a spacer layer, vias, and implanted material. The spacer layer isolates or insulates the first film pattern M1 and the second film pattern M2. The vias are formed at the connection points between the first film pattern M1 and the second film pattern M2. The implanted material is injected into the vias vias by ion implantation, thereby connecting the first film pattern M1 and the second film pattern M2. By setting vias in the two functional film layers and filling them with implanted material by ion implantation, the two functional film layers are made conductive. By controlling the doping of the implanted material, the on-resistance can be reduced.
[0039] In this embodiment, the spacer layer can be multiple layers or a single layer, such as... Figure 2 , Figure 2 This is a schematic diagram of a specific embodiment of the film interconnect structure fabrication process in this application. After the functional circuit of the first film pattern M1 is fabricated, an interlayer insulating layer is deposited. The materials include, but are not limited to, amorphous silicon, polycrystalline silicon, silicon nitride, and silicon oxide. After the interlayer insulating layer is deposited, via patterns are created by coating, exposure, and development to expose the locations where conductivity is required. Then, ion implantation is performed to inject relevant substances into the locations where conductivity is required, thereby changing the physical properties of the locations and achieving conductivity. The implanted substances include, but are not limited to, phosphine and borane. In this embodiment, not only can interlayer conductivity be achieved, but the on-resistance can also be controlled by controlling the amount of ion doping.
[0040] In one specific embodiment, the first film pattern M1 is a common electrode layer, the spacer layer is a planarization layer, and the second film pattern M2 is an SD layer. The first film pattern M1 is fabricated on the planarization layer, the second film pattern is fabricated in the planarization layer, and the vias pass through the planarization layer.
[0041] In another specific embodiment, the first film pattern M1 is a common electrode layer, the spacer layer includes a planarization layer, an isolation layer and an insulating layer, the second film pattern M2 is a gate layer, the first film pattern M1 is fabricated on the planarization layer, the planarization layer is fabricated on the isolation layer, the isolation layer is fabricated on the insulating layer, the second film pattern is fabricated in the insulating layer, the insulating layer is fabricated on the glass substrate, and the via passes through the planarization layer, the isolation layer and the insulating layer.
[0042] Preferably, the injected substance is one or more of phosphine and borane.
[0043] Preferably, the insulating layer is amorphous silicon, polycrystalline silicon, silicon nitride, or silicon oxide.
[0044] Secondly, an array substrate, such as Figure 3 , Figure 3 This is a schematic diagram of a specific embodiment of an array substrate fabricated using the film interconnect structure fabrication process described in this application; it includes the film interconnect structure of the first aspect, wherein it further includes a passivation layer and a pixel electrode layer; the common electrode layer is fabricated in the passivation layer, and the pixel electrode layer is fabricated on the passivation layer.
[0045] Thirdly, a liquid crystal display device includes an array substrate as described in the second aspect.
[0046] The present invention discloses a film interconnect structure, an array substrate, and a liquid crystal display device. By setting through holes in two functional film layers and filling them with implanted material through ion implantation, the two functional film layers are made conductive. By controlling the dopant of the implanted material, the on-resistance can be reduced.
[0047] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model shall be included within the protection scope of the present utility model.
Claims
1. A film interconnect structure, characterized in that, include: First membrane layer pattern; Second film layer pattern; Spacer layer; Through hole; Injecting material; The spacer layer is used to isolate or insulate the first film pattern from the second film pattern. The via is formed at the connection position between the first film pattern and the second film pattern. The implanted material is injected into the via by ion implantation, so that the first film pattern and the second film pattern are connected.
2. The film interconnect structure according to claim 1, characterized in that, The first film pattern is a common electrode layer, the spacer layer is a planarization layer, the second film pattern is an SD layer, the first film pattern is formed on the planarization layer, the second film pattern is formed in the planarization layer, and the via passes through the planarization layer.
3. The film interconnect structure according to claim 1, characterized in that, The first film pattern is a common electrode layer, the spacer layer includes a planarization layer, an isolation layer and an insulating layer, the second film pattern is a gate layer, the first film pattern is formed on the planarization layer, the planarization layer is formed on the isolation layer, the isolation layer is formed on the insulating layer, the second film pattern is formed in the insulating layer, the insulating layer is formed on a glass substrate, and the via passes through the planarization layer, the isolation layer and the insulating layer.
4. The film interconnect structure according to claim 2 or 3, characterized in that, The injected substance is one or more of phosphine and borane.
5. The film interconnect structure according to claim 3, characterized in that, The insulating layer is amorphous silicon, polycrystalline silicon, silicon nitride, or silicon oxide.
6. An array substrate comprising the film interconnect structure according to any one of claims 1-5, characterized in that, Also includes: passivation layer; Pixel electrode layer; The common electrode layer is fabricated in the passivation layer, and the pixel electrode layer is fabricated on the passivation layer.
7. A liquid crystal display device, characterized in that, Includes the array substrate as described in claim 6.