Display panel, display module and display device

Abstract

The utility model provides a display panel, a display module and a display device. Relates to the technical field of display. The display panel comprises a display area and a non-display area, the non-display area comprises a plurality of scanning driving circuits and a plurality of control driving circuit binding pins, and the scanning driving circuits and the control driving circuit binding pins are arranged on different sides of the display area respectively; the control driving circuit binding pins comprise first pins, the first pins are used for outputting first driving signals, the first pins are electrically connected with the scanning driving circuits through first signal lines, and the same first driving signals received by different scanning driving circuits are output by the same first pin. The same first pin is used for transmitting the same first driving signal to different scanning driving circuits, so that the number of the first pins in the binding pins of the control driving circuit is effectively reduced, the size of the control driving circuit is reduced, the production cost of a product is reduced, meanwhile, the frame width of the product can be reduced, and the display effect is improved.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and more specifically to a display panel, a display module, and a display device. Background Technology

[0002] Currently, display panels are driven using GOA (Gate On Array) circuits. The GOA circuit, under the control of the control circuit, transmits drive signals to the pixel circuits of the display panel, which then display image information. To ensure display quality and symmetrical aesthetics, the GOA circuits are positioned on both sides of the active area (AA) of the display panel. The control circuit has pins of the same type at both ends for electrical connection to the GOA circuits on both sides, enabling control of the GOA circuits. However, some of these pins transmit the same signals, and a larger number of pins increases the size of the control circuit, increasing production costs and potentially widening the bezel, thus affecting display quality.

[0003] Therefore, a new technical solution is urgently needed to solve the above-mentioned technical problems. Utility Model Content

[0004] The utility model description section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This utility model description section is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, this utility model proposes a display panel, comprising:

[0006] Display area and non-display area, with the non-display area surrounding the display area;

[0007] The display area includes pixel circuitry;

[0008] The non-display area includes multiple scan drive circuits and multiple control drive circuit binding pins. The scan drive circuits are electrically connected to the pixel circuits. Some pins of the control drive circuit binding pins are electrically connected to the scan drive circuits, and some pins of the control drive circuit binding pins are electrically connected to the pixel circuits. The scan drive circuits and control drive circuit binding pins are respectively located on different sides of the display area.

[0009] The control drive circuit is bound to a first pin, which is used to output a first drive signal. The first pin is electrically connected to the scan drive circuit through a first signal line. The same first drive signal received by different scan drive circuits is output from the same first pin.

[0010] The first driving signal includes a first scan DC voltage signal, a second scan DC voltage signal, a low-level power supply signal, a DC high voltage signal, a DC low voltage signal, and an initialization frame start signal.

[0011] In some implementations, the control drive circuit bonding pins include:

[0012] The second pin is used to output the second drive signal. The second pin is electrically connected to the scan drive circuit through the second signal line. The number of the second signal lines is equal to the number of the second pins. The second drive signal includes the frame start signal.

[0013] The second signal line portion surrounds the first signal line.

[0014] In some implementations, the control drive circuit bonding pins include:

[0015] The third pin is used to output the third drive signal. The third pin is electrically connected to each scan drive circuit through the third signal line. The third drive signal includes a clock signal.

[0016] The third signal line portion surrounds the first signal line.

[0017] In some implementations, the third signal line surrounds the second signal line or the second signal line surrounds the third signal line.

[0018] In some implementations, the multiple scan drive circuits include cascaded n-stage first sub-circuits and m-stage second sub-circuits, where n and m are both natural numbers greater than 0;

[0019] The first sub-circuit of the first stage is electrically connected to the first signal line, and the first sub-circuit of the nth stage is electrically connected to the second sub-circuit of the first stage through the fourth signal line. The fourth signal line is used to transmit the first driving signal.

[0020] The second sub-circuit of the m-th stage is electrically connected to the second signal line;

[0021] The first sub-circuit and the second sub-circuit are arranged on adjacent sides of the display area. The size of each first sub-circuit in the first direction is larger than the size of the pixel circuit in the first direction, and the size of each second sub-circuit in the second direction is larger than the size of the pixel circuit in the first direction. The multiple pixel circuits are arranged in an array, the first direction is the column arrangement direction of the pixel circuits, and the second direction is the row arrangement direction of the pixel circuits.

[0022] In some implementations, when n-level first sub-circuits are provided on both opposite sides of the display area, m-level second sub-circuits electrically connected to the first sub-circuits on different sides are arranged along the second direction, and the m-level second sub-circuits electrically connected to the first sub-circuits on different sides are located on the same side of the display area.

[0023] Adjacent pixel circuits in each row of pixel circuits are electrically connected to different scan drive circuits. Adjacent pixel circuits in each row of pixel circuits are electrically connected to some pins of the control drive circuit through the same fifth signal line. The fifth signal line is used to transmit data signals.

[0024] In some implementations, the number of stages of the first sub-circuit is equal to a first value divided by a second value, and the number of stages of the second sub-circuit is equal to a third value divided by a second value, wherein the first value is the square of the number of rows of the pixel circuit, the second value is the sum of half the number of columns of the pixel circuit and the number of rows of the pixel circuit, and the third value is half the product of the number of columns of the pixel circuit and the number of rows of the pixel circuit.

[0025] In some implementations, the scan drive circuit includes:

[0026] The third sub-circuit is divided into two groups, and the two groups of third sub-circuits are respectively set on opposite sides of the display area. The size of each third sub-circuit in the first direction is equal to the size of the pixel circuit in the first direction, where the first direction is the column arrangement direction of the pixel circuit.

[0027] The pixel circuits of adjacent rows are electrically connected to the third sub-circuits of different groups, and each row of pixel circuits is electrically connected to the first-level third sub-circuit.

[0028] In some embodiments, one end of the first group of third sub-circuits is electrically connected to the first signal line, and the other end of the first group of third sub-circuits is electrically connected to the second group of third sub-circuits via the sixth signal line; or,

[0029] One end of the third sub-circuit of the first group is electrically connected to the first signal line, and the third sub-circuit of the second group is electrically connected to the first signal line through the seventh signal line. The seventh signal line and the first signal line are electrically connected through the first node, and part of the seventh signal line surrounds the third sub-circuit of the first group.

[0030] In some implementations, the line width of the seventh signal line is greater than that of the first signal line.

[0031] Secondly, a display module is also proposed, including:

[0032] The display panel as described above;

[0033] A control drive circuit is provided, wherein the control drive circuit is connected to the control drive circuit of the display panel via a pin bonding connection.

[0034] Thirdly, a display device is also proposed, comprising:

[0035] The display panel as described above; and / or,

[0036] The display module as described above.

[0037] According to the above technical solution, by using the same first pin to transmit the same first driving signal to different scanning driving circuits, the number of first pins in the control driving circuit's bound pins can be effectively reduced, thereby reducing the size of the control driving circuit, lowering the product's production cost, and also reducing the product's bezel width and improving the display effect.

[0038] Other advantages, objectives and features of this invention will be partly apparent from the following description, and partly understood by those skilled in the art through study and practice of this invention. Attached Figure Description

[0039] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit this specification. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0040] Figure 1 A schematic block diagram of a display panel provided for an embodiment of this application;

[0041] Figure 2 A schematic structural block diagram of a display panel provided for an embodiment of this application;

[0042] Figure 3 A schematic diagram illustrating the cascaded relationship of multiple scanning drive circuits provided in an embodiment of this application;

[0043] Figure 4 A schematic structural block diagram of another display panel provided in an embodiment of this application;

[0044] Figure 5 A schematic structural block diagram of another display panel provided in an embodiment of this application;

[0045] Figure 6 A schematic structural block diagram of another display panel provided in an embodiment of this application;

[0046] Figure 7 A schematic structural block diagram of a display panel provided for an embodiment of this application;

[0047] Figure 8A schematic block diagram of a display module provided in an embodiment of this application;

[0048] Figure 9 This is a schematic block diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0049] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. The technical solutions of the embodiments of this application will now be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them.

[0050] Figure 1 This is a schematic block diagram of a display panel provided in an embodiment of this application. For example, as shown... Figure 1 As shown, symmetrical GOA circuits are arranged on the left and right sides of the display area AA, and a control drive circuit is arranged on the lower side of the display area AA. The control drive circuit is electrically connected to the GOA circuit through multiple pins, which are used to transmit corresponding signals. For example, as shown... Figure 1 As shown, the transmitted signals may include a first scan DC voltage signal VDS, a second scan DC voltage signal VSD, a low-level power signal VGL, a DC high-voltage signal GCH, a DC low-voltage signal GCL, frame start signals STV0-STV4, and clock signals CLK1-CLK8, where STV0 can represent the initialization frame start signal. To ensure cascading and alternating left and right driving, the corresponding pins of the four frame start signals STV1-STV4 and the eight clock signals CLK1-CLK8 used to transmit different timing relationships can be divided into two groups and arranged on the left and right sides of the control drive circuit. For example, it can be as follows: Figure 1As shown, the pins corresponding to STV1 and STV3 are located on the left side of the control drive circuit, and the pins corresponding to STV2 and STV4 are located on the right side. Similarly, the pins corresponding to CLK1, CLK3, CLK5, and CLK7 are located on the left side, and the pins corresponding to CLK2, CLK4, CLK6, and CLK8 are located on the right side. The pins corresponding to the remaining signals are repeatedly located on both sides of the control drive circuit. In this case, the number of pins electrically connected to the GOA on the control drive circuit is 24. However, there are six identical pins on both sides of the control drive circuit used to transmit the same signal to the left and right GOA circuits. To further reduce the size and cost of the control drive circuit, these six identical pins can be removed from one side of the control drive circuit, reducing the number of pins electrically connected to the GOA on the control drive circuit from 24 to 18.

[0051] According to a first aspect of this application, a display panel is proposed. Figure 2 This is a schematic structural block diagram of a display panel provided in an embodiment of this application. For example, as shown... Figure 2 As shown, the display panel may include a display area 100 and a non-display area 200, with the non-display area 200 surrounding the display area 100. The display area 100 may include pixel circuitry 110. The non-display area 200 may include multiple scan drive circuits 210 and multiple control drive circuit bonding pins 220. The scan drive circuits 210 and the control drive circuit bonding pins 220 may be respectively disposed on different sides of the display area 100. For example, the scan drive circuits 210 may be disposed as follows: Figure 2 On the left side of the display area 100 shown, the control drive circuit bonding pin 220 can be set as follows: Figure 2 The lower side of the display area 100 is shown. It should be noted that in some embodiments, if the control drive circuit bonding pin is located on the lower side of the display area, the scan drive circuit can be located on one of the left, right, or top sides of the display area, or simultaneously on both sides of the display panel in three combinations: left and right, left and top, and right and top. Some pins of the control drive circuit bonding pin are electrically connected to the scan drive circuit for transmitting control signals to the scan drive circuit. The scan drive circuit is electrically connected to the pixel circuit, and transmits scan signals to the pixel circuit under the action of the control signals. Some pins of the control drive circuit bonding pin are also electrically connected to the pixel circuit for transmitting data signals to the pixel circuit, which can display image information under the action of the scan signals and data signals.

[0052] It should be noted that, Figure 2The electrical connection between the control drive circuit bonding pin 220 and the scan drive circuit 210 and pixel circuit 110 shown is merely illustrative and does not imply a limitation on the actual number of pins in the control drive circuit bonding pin 220 that are electrically connected to the scan drive circuit 210 and pixel circuit 110.

[0053] For example, such as Figure 2 As shown, the control drive circuit bonding pin 220 may include a first pin A, which is used to output a first drive signal. The first drive signal may include a first scan DC voltage signal VDS, a second scan DC voltage signal VSD, a low-level power signal VGL, a DC high-voltage signal GCH, a DC low-voltage signal GCL, and an initialization frame start signal STV0. The first pin is electrically connected to the scan drive circuit via a first signal line, and the same first drive signal received by different scan drive circuits is output from the same first pin. It should be noted that, in order to... Figure 2 Concisely, only one pin of the first pin A is shown, representing a first signal line L1 that is electrically connected to the scan drive circuit 210. In reality, each pin of the first pin A is connected to... Figure 2 The lowest scan drive circuit 210 among the multiple scan drive circuits 210 shown is electrically connected via a first signal line L1. For example, the multiple scan drive circuits 210 are electrically connected in a cascaded manner. This lowest scan drive circuit can be considered as the first-level scan drive circuit, meaning it can receive the first drive signal from the first pin L1. For the other scan drive circuits 210, they can receive the first drive signal from the next higher-level scan drive circuit 210 through the cascaded relationship. In other words, the first pin A is only electrically connected to the first-level scan drive circuit among the multiple scan drive circuits 210, and since the multiple scan drive circuits 210 are cascaded, the first drive signal received by the multiple scan drive circuits 210, such as the first scan DC voltage signal VDS, is all output from the same first pin A.

[0054] As mentioned earlier, in Figure 1In the illustrated embodiment, the number of pins electrically connected to the GOA on the control drive circuit is 24. However, six identical pins exist on both the left and right sides of the control drive circuit for transmitting the same signal to the left and right GOA circuits, including VDS, VSD, GCH, GCL, STV0, and VGL. To further reduce the size of the control drive circuit and lower costs, these six identical pins can be removed from one side of the control drive circuit, reducing the number of pins electrically connected to the GOA from 24 to 18. Thus, by using the same first pin to transmit the same first drive signal to different scan drive circuits, the number of first pins in the control drive circuit's pin-binding structure can be effectively reduced, thereby reducing the size of the control drive circuit, lowering product manufacturing costs, and also reducing the product's bezel width, improving display performance.

[0055] In some implementations, the control drive circuit bonding pin may include a second pin for outputting a second drive signal. Figure 3 This is a schematic diagram illustrating the cascaded relationship of multiple scan driving circuits provided in an embodiment of this application. For example, as shown... Figure 2 and Figure 3 As shown, the second driving signal may include frame start signals STV1, STV2, STV3, and STV4. The second pin B is electrically connected to the scan driving circuit 210 via second signal lines L2, and the number of second signal lines L2 is equal to the number of second pins B. It should be noted that, in order to... Figure 2 The diagram is concise, showing only one pin of the second pin B that is electrically connected to the scan drive circuit 210 via a single second signal line L2. In reality, each pin of the second pin B is electrically connected to a corresponding number of scan drive circuits 210 via the second signal line L2. Figure 3It can be seen that the pin in the second pin used to transmit the frame start signal STV1 is electrically connected to the input terminal Input of the scan driver circuit GOA-1. The output terminal GOUT of the scan driver circuit GOA-1 is used to transmit the scan signal Gate-1 to the pixel circuit, and also to transmit the frame start signal to the input terminal Input of the cascaded scan driver circuit GOA-5. Similarly, the pin in the second pin used to transmit the frame start signal STV2 is electrically connected to the input terminal Input of the scan driver circuit GOA-2. The output terminal GOUT of the scan driver circuit GOA-2 is used to transmit the scan signal Gate-2 to the pixel circuit, and also to transmit the frame start signal to the input terminal Input of the cascaded scan driver circuit GOA-6. The pin in the second pin used to transmit the frame start signal STV3 is electrically connected to the input terminal Input of the scan driver circuit GOA-3. The output terminal GOUT of the scan driver circuit GOA-3 is used to transmit the scan signal Gate-3 to the pixel circuit, and also to transmit the frame start signal to the input terminal Input of the cascaded scan driver circuit GOA-7. The second pin, used for transmitting the frame start signal STV4, is electrically connected to the input terminal Input of the scan driver circuit GOA-4. The output terminal GOUT of the scan driver circuit GOA-4 is used to transmit the scan signal Gate-4 to the pixel circuit and also to transmit the frame start signal to the input terminal Input of the cascaded scan driver circuit GOA-8. The Reset pin on each scan driver circuit is used to receive a reset signal. Similarly, the a+4 level scan driver circuits can receive the frame start signal from the a level scan driver circuit through a cascaded relationship, where a is a natural number greater than 0. In the above embodiment, the second pin is electrically connected to the four scan driver circuits respectively through four second signal lines. For example, as shown... Figure 2 As shown, the lower half of the second signal line is arranged around the first signal line, that is, there is no intersection between the first signal line and the second signal line to avoid signal interference.

[0056] For example, in some implementations, such as Figure 2 As shown, the control drive circuit bonding pins may include a third pin, which is used to output a third drive signal. For example, as... Figure 3 As shown, the third drive signal may include clock signals CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8. To make... Figure 2 Simplicity, in Figure 2 Only the third pin, used to transmit the clock signal CLK1, is shown. Combined with... Figure 2 and Figure 3The third pin is electrically connected to each scan driver circuit via a third signal line. For example, the pin used to transmit the clock signal CLK1 is electrically connected to the clock signal input CLK of scan driver circuit GOA-1. The pin used to transmit the clock signal CLK2 is electrically connected to the clock signal input CLK of scan driver circuit GOA-2. The pin used to transmit the clock signal CLK3 is electrically connected to the clock signal input CLK of scan driver circuit GOA-3. The pin used to transmit the clock signal CLK4 is electrically connected to the clock signal input CLK of scan driver circuit GOA-4. The pin used to transmit the clock signal CLK5 is electrically connected to the clock signal input CLK of scan driver circuit GOA-5. The pin used to transmit the clock signal CLK6 is electrically connected to the clock signal input CLK of scan driver circuit GOA-6. The pin used to transmit the clock signal CLK7 is electrically connected to the clock signal input CLK of scan driver circuit GOA-7. The third pin, used to transmit the clock signal CLK8, is electrically connected to the clock signal input terminal CLK of the scan driver circuit GOA-8. Because... Figure 2 and Figure 3 This illustration uses a scenario where the scan drive circuit requires 8 clock signals. Therefore, for the (b+8)th level scan drive circuit, the third signal line can be electrically connected to the pin in the third pin used to transmit the clock signal CLKb, where b is a natural number greater than 0. In the above embodiment, the third pin is electrically connected one-to-one with the scan drive circuit. For example,... Figure 2 As shown, the lower half of the third signal line is arranged around the first signal line, that is, there is no intersection between the first signal line and the third signal line to avoid signal interference.

[0057] exist Figure 2 In the illustrated embodiment, the third signal line is arranged around the second signal line. In some embodiments, the routing can also be configured such that the second signal line surrounds the third signal line. Both the second and third signal lines are partially arranged around the first signal line, and the relationship between the second and third signal lines can be reasonably set according to the panel layout and the actual location of the scanning drive circuit to be connected. During the routing design, the crossing between signal lines should be minimized to avoid signal interference.

[0058] Figure 4 This is a schematic structural block diagram of another display panel provided in an embodiment of this application. Exemplary examples include... Figure 4As shown, multiple scan drive circuits may include cascaded n-stage first sub-circuit 211 and m-stage second sub-circuit 212, where n and m are both natural numbers greater than 0. The first-stage first sub-circuit 211 is electrically connected to one end of a first signal line L1, and the other end of the first signal line L1 is electrically connected to a first pin. The n-stage first sub-circuit 211 is electrically connected to the first-stage second sub-circuit 212 via a fourth signal line L4, which is used to transmit a first drive signal. Since the first and second sub-circuits are cascaded, and each sub-circuit in the first and second sub-circuits is also cascaded, after the first-stage first sub-circuit receives the first drive signal from the first pin, the remaining sub-circuits in the first sub-circuit can receive the first drive signal from the previous stage first sub-circuit based on the cascading relationship. This first drive signal is the same as the first drive signal transmitted by the first pin. That is, after receiving the first drive signal from the first pin, the first sub-circuit of the first stage transmits this first drive signal to the first sub-circuit of the second stage. The first sub-circuit of the second stage then transmits the received first drive signal to the first sub-circuit of the third stage, and so on. The first sub-circuit of the nth stage can receive the first drive signal from the first sub-circuit of the (n-1)th stage. Then, the first sub-circuit of the nth stage can transmit the first drive signal to the second sub-circuit of the first stage via the fourth signal line. Similarly, the second sub-circuit of the first stage can transmit the first drive signal to the second sub-circuit of the second stage, and so on. The second sub-circuit of the mth stage can receive the first drive signal from the second sub-circuit of the (m-1)th stage. Therefore, based on the cascading relationship of the sub-circuits in the scan drive circuit, the first drive signal received by the first sub-circuit of the nth stage and the second sub-circuit of the mth stage, such as the first scan DC voltage signal VDS, can both be output from the same first pin. Figure 4 It can be seen that the first pin only needs to be electrically connected to the first stage sub-circuit of the first sub-circuit 211 in the scan driving circuit to realize the transmission of the first driving signal between the first pin and the scan driving circuit, reducing wiring setup, optimizing panel space layout, and effectively reducing signal interference. For example, as shown... Figure 4 As shown, the m-th stage second sub-circuit 212 is electrically connected to one end of the second signal line L2, and the other end of the second signal line L2 is electrically connected to the second pin. As described above, the second signal line is used to transmit the second driving signal. The second driving signal is introduced from the m-th stage second sub-circuit side of the scan driving circuit, and then, according to the cascading relationship, the transmission of the second driving signal in the scan driving circuit is completed. It should be noted that the above embodiment is only used to illustrate that the first driving signal and the second driving signal are introduced from different sides of the scan driving circuit. For ease of drawing, it is taken as an example that both the first and second signal lines are one, illustrating the connection relationship between the first pin and the second pin and the scan driving circuit respectively.

[0059] For example, such as Figure 4 As shown, the first sub-circuit 211 is disposed on the left side of the display area, and the second sub-circuit 212 is disposed on the upper side of the display area. That is, the first sub-circuit 211 and the second sub-circuit 212 are disposed on adjacent sides of the display area. Exemplarily, the dimensions of each level of the first sub-circuit in the first direction y are the same, and the dimensions of each level of the second sub-circuit in the second direction x are the same. In some embodiments, the dimension of each level of the first sub-circuit in the first direction y may be equal to the dimension of each level of the second sub-circuit in the second direction x. Figure 4 As shown, multiple pixel circuits are arranged in an array, and the first direction y can be as follows: Figure 4 The column arrangement direction of the pixel circuit shown, the second direction x can be as follows: Figure 4 The row arrangement direction of the pixel circuits is shown. For example, as shown... Figure 4 As shown, taking the nth-level first sub-circuit 211 as an example, the size of the nth-level first sub-circuit 211 in the first direction can be represented as H, and the size of the pixel circuit 110 in the first direction y can be represented as h, where H > h. For example, as shown... Figure 4 As shown, taking the first-stage second sub-circuit 212 as an example, the dimension of the first-stage second sub-circuit 212 in the first direction can be expressed as d, where d > h.

[0060] The second driving signal is introduced from one side of the scanning driving circuit. Since this application reduces the size of the control driving circuit by decreasing the number of pins bonded to it, the scanning driving circuit drives the pixel circuit in a single-sided manner; that is, the scanning driving circuit only provides a scanning signal to one side of the pixel circuit. Furthermore, the size parameters of the scanning driving circuit are also limited by high-resolution requirements and narrow bezels. While ensuring that the size of each scanning driving circuit level remains unchanged in the second direction, the size of each scanning driving circuit level in the first direction is increased. That is, while ensuring that the width of each scanning driving circuit level remains unchanged, the height of each scanning driving circuit level is increased. It should be noted that after increasing the size of each scanning driving circuit level in the first direction, the number of scanning driving circuit levels that can be placed on one side of the display area decreases accordingly. The excess scanning driving circuits that cannot be placed can be placed on other sides of the display area, so that these two parts of the scanning driving circuit are located on adjacent sides of the display area. That is, the scanning driving circuit can be divided as described above. Figure 4 The first and second sub-circuits are shown. It should be noted that the second sub-circuit can be considered as the first sub-circuit rotated 90° counterclockwise; that is, the dimension of the second sub-circuit in the first direction y is equal to the dimension of the first sub-circuit in the second direction x, and vice versa. This ensures that the effective area of ​​the scan drive circuit remains unchanged, guaranteeing its normal driving function.

[0061] In some implementations, the number of stages of the first sub-circuit is equal to a first value divided by a second value, and the number of stages of the second sub-circuit is equal to a third value divided by a second value, wherein the first value is the square of the number of rows of the pixel circuit, the second value is the sum of half the number of columns of the pixel circuit and the number of rows of the pixel circuit, and the third value is half the product of the number of columns of the pixel circuit and the number of rows of the pixel circuit.

[0062] For example, the resolution of the display panel can be set to X×Y, where X represents the number of rows of the pixel circuit, which is equal to the number of scan signals. Y represents the number of columns of the pixel circuit, which is equal to the number of data signals. For example, the second sub-circuit can be placed in half of the upper area of ​​the display area, that is, the size of this area in the second direction can be 0.5×h×Y. The first sub-circuit can be placed in the left area of ​​the display area, that is, the size of this area in the first direction can be h×X. By adding these two sizes and dividing by the number of rows of the pixel circuit X, the size of each level of the first sub-circuit in the first direction can be obtained, which is also the size of each level of the second sub-circuit in the second direction. The calculation result can be expressed by formula (1): Then, by dividing the dimension h×X of the left-side region in the first direction by the aforementioned formula (1), the number of stages of the first sub-circuit can be obtained. The calculation process can be expressed as follows: After organizing the calculation results, the number of stages of the first sub-circuit can be obtained. By dividing half of the upper region's dimension 0.5 × h × Y in the second direction by the aforementioned formula (1), the number of stages of the second sub-circuit can be obtained. The calculation process can be expressed as follows: After organizing the calculation results, the number of stages of the second sub-circuit can be obtained.

[0063] Therefore, the number of stages of the first and second sub-circuits can be obtained through the above calculation process. It should be noted that the number of stages of the first and second sub-circuits is related to the size of the area used to house the scan driving circuit for the excess portion. In the above embodiment, the area used to house the scan driving circuit for the excess portion is designed to be half of the upper area of ​​the display area. Therefore, the size of the area used to house the scan driving circuit for the excess portion is the size of half of the upper area of ​​the display area in the second direction. In practical applications, the size of the area used to house the scan driving circuit for the excess portion can be adjusted according to different panel design schemes, thereby adjusting the number of stages of the first and second sub-circuits.

[0064] Figure 5 This is a schematic structural block diagram of another display panel provided in an embodiment of this application. For example, as shown... Figure 5As shown, n-level first sub-circuits are arranged on opposite sides of the display area, i.e., the left and right sides. The m-level second sub-circuits, electrically connected to the first sub-circuits on different sides, are arranged along a second direction. For example, as shown... Figure 5 As shown, the first sub-circuit 211 located on the left and right sides of the display area is electrically connected to the m-level second sub-circuit 212, respectively. For description and understanding, the first sub-circuit 211 on the left side of the display area is called the left first sub-circuit, the m-level second sub-circuit 212 electrically connected to the first sub-circuit 211 on the left side of the display area is called the left second sub-circuit, the first sub-circuit 211 on the right side of the display area is called the right first sub-circuit, and the m-level second sub-circuit 212 electrically connected to the first sub-circuit 211 on the right side of the display area is called the right second sub-circuit. The m-level second sub-circuits electrically connected to the first sub-circuit 211 on different sides are located on the same side of the display area. That is, both the left second sub-circuit and the right second sub-circuit are located on the upper side of the display area. Furthermore, both the left second sub-circuit and the right second sub-circuit include m-level sub-circuits, which are arranged sequentially along the row arrangement direction of the pixel circuits.

[0065] For example, such as Figure 5 As shown, the first pin is electrically connected to the first-stage first sub-circuit 211 in the left first sub-circuit via the first signal line L1 to transmit a first drive signal to the first-stage first sub-circuit. According to the cascading relationship, the first drive signal can be transmitted to the nth-stage first sub-circuit 211 in the left first sub-circuit. The nth-stage first sub-circuit 211 in the left first sub-circuit is electrically connected to the first-stage second sub-circuit 212 in the left second sub-circuit via the fourth signal line L4, and transmits the first drive signal to the first-stage second sub-circuit 212 in the left second sub-circuit. According to the cascading relationship, the first drive signal can be transmitted to the mth-stage second sub-circuit 212 in the left second sub-circuit. The mth-stage second sub-circuit 212 in the left second sub-circuit is electrically connected to the first-stage second sub-circuit 212 in the right second sub-circuit via the eighth signal line L8, and transmits the first drive signal to the first-stage second sub-circuit 212 in the right second sub-circuit. According to the cascading relationship, the first drive signal can be transmitted to the mth-stage second sub-circuit 212 in the right second sub-circuit. The m-th stage second sub-circuit 212 in the right second sub-circuit is electrically connected to the n-th stage first sub-circuit 211 in the right first sub-circuit via the fourth signal line L4, and transmits the first drive signal to the n-th stage first sub-circuit 211 in the right first sub-circuit. According to the cascading relationship, the first drive signal can be transmitted to the first stage first sub-circuit 211 in the right first sub-circuit. The second pin is electrically connected to the m-th stage second sub-circuit 212 in the left second sub-circuit and the first stage second sub-circuit 212 in the right second sub-circuit via the second signal line L2.

[0066] In some implementations, the linewidth of the second signal line electrically connected to the right second sub-circuit is greater than the linewidth of the second signal line electrically connected to the left second sub-circuit. This balances the load and reduces the deviation in the second drive signal received by the left and right scanning drive circuits.

[0067] In some implementations, adjacent pixel circuits in each row of pixel circuits are electrically connected to different scan drive circuits. Adjacent pixel circuits in each row of pixel circuits are also electrically connected to a portion of the control drive circuit's bound pins via the same fifth signal line, which is used to transmit data signals.

[0068] For example, the following explanation uses a single-row pixel circuit as an example. Figure 5 As shown, pixel circuit 1 and pixel circuit 2 in pixel circuit 110 are adjacent pixel circuits. Pixel circuit 1 is electrically connected to the nth level first sub-circuit 211 in the left first sub-circuit, and pixel circuit 2 is electrically connected to the nth level first sub-circuit 211 in the right first sub-circuit. Pixel circuit 1 and pixel circuit 2 are electrically connected to one end of the same fifth signal line L5. The other end of this fifth signal line L5 is electrically connected to a portion of the pins of the control drive circuit. It should be noted that... Figure 4 compared to, Figure 5 The number of scan drive circuits in the display area is doubled, and correspondingly, the number of scan signals is also doubled. While maintaining the same number of pixel circuits in the display area (i.e., preserving the original resolution), the number of fifth signal lines used to transmit data signals is halved. That is, adjacent pixel circuits in each row are electrically connected to the same fifth signal line. For example, as shown... Figure 5 As shown in the response signal timing diagram, the nth stage first sub-circuit 211 in the left first sub-circuit can transmit the scan signal G1 to the pixel circuits 1, 3, ..., N-1 electrically connected to it. Under the action of the scan signal G1, pixel circuit 1 writes the data signal S1 transmitted by the fifth signal line L5. Pixel circuit 3 writes the data signal S3 transmitted by the fifth signal line L5. And so on, pixel circuit N-1 can write the data signal S3 transmitted by the fifth signal line L5. N-1According to the signal timing relationship, when the scan signal G1 is an active level signal, the scan signal G2 is an inactive level signal. An active level signal enables the pixel circuit to conduct and write the corresponding data signal; conversely, an inactive level signal prevents the pixel circuit from conducting. After pixel circuits 1, 3, ..., N-1 write their corresponding data signals, the scan signal G1 becomes inactive, and the nth-level first sub-circuit 211 in the right first sub-circuit transmits the scan signal G2 to the pixel circuits 2, 4, ..., N electrically connected to it. Under the action of the scan signal G2, pixel circuit 2 writes the data signal S2 transmitted by the fifth signal line L5. Pixel circuit 4 writes the data signal S4 transmitted by the fifth signal line L5. And so on, pixel circuit N can write the data signal S transmitted by the fifth signal line L5.

[0069] In summary, the driving method for pixel circuits is... Figure 4 The corresponding 1G1D is transformed into Figure 5 The diagram shows 2G1D. 1G1D indicates that only one row of pixel circuits is active at any given time, with all data signals transmitted to that row. 2G1D indicates that only one row of pixel circuits is active at any given time, with data signal lines from the same column transmitting data signals to two pixel circuits located in two separate columns. This achieves multiplexing of data signal lines connecting adjacent pixel circuits, reducing panel traces while maintaining the panel's resolution and display quality.

[0070] Figure 6 This is a schematic structural block diagram of another display panel provided in an embodiment of this application. For example, as shown... Figure 6 As shown, the scanning drive circuit includes multiple levels of third sub-circuits 213. The third sub-circuits 213 are divided into two groups, and the two groups of third sub-circuits 213 are respectively arranged on opposite sides of the display area, for example, in... Figure 6 The left and right sides of the display area are shown. Each side's third sub-circuit 213 includes k levels of third sub-circuits. The size of each level of third sub-circuit in the first direction is equal to the size of the pixel circuit in the first direction. That is, the size of each level of third sub-circuit in the column arrangement direction of the pixel circuit is equal to the size of a row of pixel circuits in the column arrangement direction of the pixel circuit. Adjacent rows of pixel circuits are electrically connected to different groups of third sub-circuits, and each row of pixel circuits is electrically connected to a level of third sub-circuit. For example, for ease of description and understanding, the group of third sub-circuits located on the left side of the display area is called the left third sub-circuit, and the group of third sub-circuits located on the right side of the display area is called the right third sub-circuit. Figure 6As shown, the first-level third sub-circuit 213 in the right third sub-circuit can be electrically connected to the first row of pixel circuits. The second-level third sub-circuit 213 in the left third sub-circuit can be electrically connected to the second row of pixel circuits, wherein the first row of pixel circuits and the second row of pixel circuits are adjacent row pixel circuits. Figure 6 The display panel shown is driven by the 1G1D method as described above. Since the third sub-circuit is divided into two groups and set on both sides of the display area, the driving method can be specifically driven by the dual-side scanning driving circuit alternately, which is equivalent to single-side driving.

[0071] In some implementations, one end of the first group of third sub-circuits is electrically connected to the first signal line, and the other end of the first group of third sub-circuits is electrically connected to the second group of third sub-circuits via the sixth signal line. The left third sub-circuit can be considered as the first group of third sub-circuits, and the right third sub-circuit as the second group of third sub-circuits. For example,... Figure 6 As shown, the first-stage third sub-circuit 213 in the left third sub-circuit is electrically connected to the first pin via the first signal line L1, allowing the first pin to transmit a first drive signal to the first-stage third sub-circuit 213 in the left third sub-circuit via the first signal line L1. According to the cascading relationship, the first drive signal can be transmitted to the k-th stage third sub-circuit 213 in the left third sub-circuit. The k-th stage third sub-circuit 213 in the left third sub-circuit is electrically connected to the k-th stage third sub-circuit 213 in the right third sub-circuit via the sixth signal line L6, to transmit the first drive signal to the k-th stage third sub-circuit 213 in the right third sub-circuit. According to the cascading relationship, the first drive signal can be transmitted to the first-stage third sub-circuit 213 in the right third sub-circuit. The k-th level third sub-circuit 213 in the left third sub-circuit is electrically connected to the second pin through the second signal line L2, and the k-th level third sub-circuit 213 in the right third sub-circuit is electrically connected to the second pin through the second signal line L2, so that the second pin transmits the second driving signal to the two sets of third sub-circuits respectively. According to the cascading relationship, the second driving signal can be transmitted to the first level third sub-circuit 213 in the left third sub-circuit and the first level third sub-circuit 213 in the right third sub-circuit.

[0072] In some implementations, one end of the first group of third sub-circuits is electrically connected to the first signal line, and the second group of third sub-circuits is electrically connected to the first signal line via a seventh signal line, wherein the seventh signal line and the first signal line are electrically connected via a first node, and a portion of the seventh signal line surrounds the first group of third sub-circuits.

[0073] Figure 7 This is a schematic structural block diagram of a display panel provided in an embodiment of this application. For example, as shown... Figure 7As shown, the first-stage third sub-circuit 213 in the left third sub-circuit is electrically connected to the first pin via the first signal line L1. The k-stage third sub-circuit 213 in the right third sub-circuit is electrically connected to the seventh signal line L7. The seventh signal line is electrically connected to the first signal line L1 via the first node P1, allowing the first pin to transmit the first drive signal to the first-stage third sub-circuit 213 in the left third sub-circuit via the first signal line L1, and to the k-stage third sub-circuit 213 in the right third sub-circuit via the seventh signal line L7. According to the cascading relationship, the first drive signal can be transmitted to the k-stage third sub-circuit 213 in the left third sub-circuit and the first-stage third sub-circuit 213 in the right third sub-circuit. The transmission method of the second drive signal is the same as... Figure 6 The connection methods shown are the same and will not be repeated here. See also Figure 7 Since both the seventh signal line L7 and the first signal line L1 are used to transmit the first drive signal, the seventh signal line L7 is connected by a winding method, and the length of the seventh signal line L7 is greater than the length of the first signal line L1. Therefore, in order to balance the load and reduce the deviation of the third sub-circuits on the left and right sides from receiving the first drive signal, in some embodiments, the line width of the seventh signal line is greater than the line width of the first signal line, so as to compensate for the load difference.

[0074] It should be noted that this application uses the example where the first, second, and third pins are all located on the left side of the display panel. Therefore, in the corresponding embodiment, the routing of multiple signal lines is to detour around the left side of the display area. In practical applications, the routing method can be set according to the position of the aforementioned pins on the display panel. The accompanying drawings in this application do not imply a specific limitation on the routing of signal lines.

[0075] Therefore, the first driving signal for the second group of third sub-circuits can be provided through the above two routing schemes, which enriches the panel design layout scheme and provides more routing options.

[0076] A second aspect of this application also proposes a display module. Figure 8 This is a schematic block diagram of a display module provided in an embodiment of this application. For example, as shown... Figure 8 As shown, the display module 800 may include the display panel 810 and the control driving circuit 820 as described above. The control driving circuit 820 may be an IC (integrated circuit) chip. After obtaining the display panel according to the above technical solution, the IC chip can be placed on the bonding pins of the control driving circuit of the display panel according to the pin correspondence, and then the IC chip can be bonded to the display panel using a bonding process.

[0077] A third aspect of this application also proposes a display device. Figure 9This is a schematic block diagram of a display device provided in an embodiment of this application. For example, as shown... Figure 9 As shown, the display device 900 may include both the display panel 810 and the display module 800 as described above. In some embodiments, the display device 900 may further include one or both of the display panel 810 and the display module 800.

[0078] For example, the display device in this application embodiment can be applied to scenarios such as vehicle display, computer, medical display, television, smart wearable display, etc. The smart wearable device may include AR (augmented reality) device and VR (virtual reality) device, etc., and this application embodiment does not make specific limitations.

[0079] Those skilled in the art can understand the specific details and beneficial effects of the display module and display device by reading the above description of the display panel, and will not be repeated here for the sake of brevity.

[0080] For ease of description, the term "connection" may be used herein to describe the relationship between one or more elements or features shown in the figure and other elements or features. It should be understood that "connection" may include direct connections or indirect connections via other elements or features, and this document is intended to encompass all such cases.

[0081] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, parts, components, and / or combinations thereof.

[0082] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0083] This utility model has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the utility model to the described embodiments. Furthermore, those skilled in the art will understand that this utility model is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this utility model, all of which fall within the scope of protection claimed by this utility model. The scope of protection of this utility model is defined by the appended claims and their equivalents.

Claims

1. A display panel, characterized in that, include: A display area and a non-display area, wherein the non-display area surrounds the display area; The display area includes pixel circuitry; The non-display area includes multiple scan driving circuits and multiple control driving circuit binding pins. The scan driving circuits are electrically connected to the pixel circuits. Some pins of the control driving circuit binding pins are electrically connected to the scan driving circuits, and some pins of the control driving circuit binding pins are electrically connected to the pixel circuits. The scan driving circuits and the control driving circuit binding pins are respectively located on different sides of the display area. The control drive circuit includes a first pin, which is used to output a first drive signal. The first pin is electrically connected to the scan drive circuit through a first signal line. The same first drive signal received by different scan drive circuits is output from the same first pin. The first driving signal includes a first scan DC voltage signal, a second scan DC voltage signal, a low-level power supply signal, a DC high voltage signal, a DC low voltage signal, and an initialization frame start signal.

2. The display panel according to claim 1, characterized in that, The control drive circuit bonding pins include: The second pin is used to output a second driving signal. The second pin is electrically connected to the scan driving circuit through a second signal line. The number of the second signal lines is equal to the number of the second pins. The second driving signal includes a frame start signal. The second signal line portion surrounds the first signal line.

3. The display panel according to claim 2, characterized in that, The control drive circuit bonding pins include: The third pin is used to output a third driving signal. The third pin is electrically connected to each of the scan driving circuits through a third signal line. The third driving signal includes a clock signal. The third signal line portion surrounds the first signal line.

4. The display panel according to claim 3, characterized in that, The third signal line surrounds the second signal line or the second signal line surrounds the third signal line.

5. The display panel according to claim 3 or 4, characterized in that, The plurality of said scanning drive circuits include cascaded n-stage first sub-circuits and m-stage second sub-circuits, where n and m are both natural numbers greater than 0; The first sub-circuit of the first stage is electrically connected to the first signal line, and the first sub-circuit of the nth stage is electrically connected to the second sub-circuit of the first stage through the fourth signal line, wherein the fourth signal line is used to transmit the first driving signal; The second sub-circuit of the m-th stage is electrically connected to the second signal line; The first sub-circuit and the second sub-circuit are disposed on adjacent sides of the display area. The size of the first sub-circuit at each level is larger than the size of the pixel circuit in the first direction in the first direction, and the size of the second sub-circuit at each level is larger than the size of the pixel circuit in the first direction in the second direction. The plurality of pixel circuits are arranged in an array, the first direction is the column arrangement direction of the pixel circuit, and the second direction is the row arrangement direction of the pixel circuit.

6. The display panel according to claim 5, characterized in that, When n-level first sub-circuits are provided on both sides of the display area, the m-level second sub-circuits electrically connected to the first sub-circuits on different sides are arranged along the second direction, and the m-level second sub-circuits electrically connected to the first sub-circuits on different sides are located on the same side of the display area. Adjacent pixel circuits in each row are electrically connected to different scan drive circuits. Adjacent pixel circuits in each row are electrically connected to a portion of the pins of the control drive circuit via the same fifth signal line, which is used to transmit data signals.

7. The display panel according to claim 5, characterized in that, The number of stages of the first sub-circuit is equal to the first value divided by the second value, and the number of stages of the second sub-circuit is equal to the third value divided by the second value. The first value is the square of the number of rows of the pixel circuit, the second value is the sum of half the number of columns of the pixel circuit and the number of rows of the pixel circuit, and the third value is half the product of the number of columns of the pixel circuit and the number of rows of the pixel circuit.

8. The display panel according to claim 3 or 4, characterized in that, The scanning drive circuit includes: The third sub-circuit is divided into two groups, and the two groups of third sub-circuits are respectively arranged on opposite sides of the display area. The size of each level of the third sub-circuit in the first direction is equal to the size of the pixel circuit in the first direction, wherein the first direction is the column arrangement direction of the pixel circuit. The pixel circuits in adjacent rows are electrically connected to the third sub-circuits in different groups, and the pixel circuits in each row are electrically connected to the first-level third sub-circuit.

9. The display panel according to claim 8, characterized in that, One end of the third sub-circuit of the first group is electrically connected to the first signal line, and the other end of the third sub-circuit of the first group is electrically connected to the third sub-circuit of the second group through the sixth signal line. or, One end of the third sub-circuit of the first group is electrically connected to the first signal line, and the third sub-circuit of the second group is electrically connected to the first signal line through a seventh signal line, wherein the seventh signal line and the first signal line are electrically connected via a first node, and the seventh signal line partially surrounds the third sub-circuit of the first group.

10. The display panel according to claim 9, characterized in that, The line width of the seventh signal line is greater than that of the first signal line.

11. A display module, characterized in that, include: The display panel as described in any one of claims 1 to 10; A control drive circuit is provided, wherein the control drive circuit is connected to the control drive circuit of the display panel via a pin bonding connection.

12. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 10; And / or, The display module as described in claim 11.

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