Message dispersion self-calibration module for digital metering system

Abstract

The utility model discloses a message dispersion self-calibration module for a digital metering system. The message dispersion self-calibration module comprises an FPGA and DSP communication interface, a pulse input and output interface, an Ethernet interface, a clock signal interface and a power supply module, the pulse input and output interface, the Ethernet interface and the clock signal interface are respectively connected with the FPGA and DSP communication interface; the FPGA and DSP communication interface is connected with the remote calibration local module; the clock signal interface is connected with the Beidou / GPS receiver; the pulse input and output interface performs clock output, clock input and 4kHz input; the Ethernet interface is used for carrying out message input and message output; and the power supply module is used for supplying power to the message dispersion self-calibration module. And calibration of the message dispersion of the standard metering equipment is realized.

Description

Technical Field

[0001] This utility model relates to the field of power equipment calibration, specifically to a message dispersion self-calibration module for a digital metering system. Background Technology

[0002] In routine metrology work, standards can generally only be calibrated through user-sent-inspection or on-site testing by calibration units. Regardless of the mode, it consumes a lot of manpower and resources. Especially for legal metrology institutions, due to the limitations of traditional calibration modes, they are often unable to complete the periodic calibration of all metrological standards within their jurisdiction. Sending them for inspection can only be done in rotation on an annual basis, resulting in a long inspection cycle for standards. Moreover, in the traditional calibration mode, standards are easily affected by factors such as vibration, rain, temperature and humidity during transportation, which can cause the measurement values ​​to drift or even be damaged.

[0003] Currently, the message dispersion test principle for digital metering equipment mainly refers to DL / T 281-2012 "Merging Unit Test Specification" and DL / T 282-2012 "Merging Unit Technical Conditions," with the merging unit being the primary test object. Most electronic instrument transformer calibrators and merging unit testers on the market support message dispersion testing, but most control the MAC via DSP or CPU processors, resulting in low real-time message capture performance and limiting their ability to measure devices with lower accuracy, such as merging units. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, this utility model provides a message dispersion self-calibration module for a digital metering system, comprising: an FPGA and DSP communication interface, a pulse input / output interface, an Ethernet interface, a clock signal interface, and a power supply module;

[0005] The pulse input / output interface, Ethernet interface, and clock signal interface are respectively connected to the FPGA and DSP communication interfaces;

[0006] The FPGA and DSP communication interface connects to the remote calibration local module.

[0007] The clock signal interface connects to the BeiDou / GPS receiver;

[0008] The pulse input / output interface provides clock output, clock input, and 4kHz input.

[0009] Ethernet interface, used for message input and message output;

[0010] The power supply module is used to power the message dispersion self-calibration module.

[0011] Furthermore, the BeiDou / GPS receiver outputs a high-precision 1PPS signal to the FPGA and DSP communication interface through the clock signal interface, and the FPGA and DSP communication interface generates a 100M high-stability clock.

[0012] Furthermore, it features a highly stable clock, whose stability is consistent with that of the BeiDou / GPS satellite positioning system clock.

[0013] Furthermore, the remote calibration local module is used to send self-calibration control commands to the message dispersion self-calibration module.

[0014] It also includes: calibrating the message dispersion of the calibrated device by using a high-stability clock and real-time acquisition of message input and output from the Ethernet interface.

[0015] This utility model provides a message dispersion self-calibration module for digital metering systems, which can capture messages in real time and calibrate the message dispersion of 0.02 level standard equipment. Attached Figure Description

[0016] Figure 1 This is a block diagram of the overall scheme for self-calibration of message dispersion of the digital metering system involved in this utility model embodiment. Detailed Implementation

[0017] Many specific details are set forth in the following description to provide a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0018] like Figure 1 As shown,

[0019] The message dispersion self-calibration module includes: an FPGA and DSP communication interface, a pulse input / output interface, an Ethernet interface, a clock signal interface, and a power supply module; the pulse input / output interface, Ethernet interface, and clock signal interface are respectively connected to the FPGA and DSP communication interface; the FPGA and DSP communication interface is connected to the remote calibration local module; the clock signal interface is connected to the BeiDou / GPS receiver; the pulse input / output interface performs clock output, clock input, and 4kHz input; the Ethernet interface is used for message input and message output.

[0020] The Beidou / GPS receiver outputs a high-precision 1PPS signal to the FPGA and DSP communication interface through the clock signal interface, and the FPGA and DSP communication interface generates a 100M high-stability clock.

[0021] The system includes a network interface, a clock signal interface connected to the FPGA and DSP communication interface, and a power supply module. The clock signal interface connects to the Beidou / GPS receiver, and the FPGA and DSP communication interface communicates with the remote calibration local module. Message input and output are performed via the Ethernet interface, and clock output, clock input, and 4kHz input are performed via the pulse input / output interface.

[0022] Ethernet interface, used for message input and message output;

[0023] The power supply module is used to power the message dispersion self-calibration module.

[0024] Furthermore, the BeiDou / GPS receiver outputs a high-precision 1PPS signal to the FPGA and DSP communication interface through the clock signal interface, and the FPGA and DSP communication interface generates a 100M high-stability clock.

[0025] Furthermore, it features a highly stable clock, whose stability is consistent with that of the BeiDou / GPS satellite positioning system clock.

[0026] Furthermore, the remote calibration local module is used to send self-calibration control commands to the message dispersion self-calibration module.

[0027] It also includes: calibrating the message dispersion of the calibrated device by using a high-stability clock and real-time acquisition of message input and output from the Ethernet interface.

[0028] Utilizing the high-precision 1PPS signal output from a BeiDou / GPS receiver, the FPGA digital phase-locked loop (PLL) is used to frequency-double the internal high-stability crystal, outputting a 100MHz high-stability clock with stability consistent with the BeiDou clock; the relative error of the high-stability clock is 1.1 × 10⁻⁶. -7 The discreteness of the message header is set within the range of -250μs to 250μs, the measurement uncertainty is 1μs, and the relative error is 1μs / 500μs = 2 × 10⁻⁶. -3 The stability of the high-stability clock is much higher than that of the measurement relative error, meeting the test requirements. This high-stability clock signal is used to drive the MAC to send or receive sampled value messages, and simultaneously drive the clock input or clock output. When an SV message header is sent or received, the current time stamp is recorded using hardware time stamping, and a message header synchronization signal is output. The absolute value of the maximum difference between the period of the message header synchronization signal and the theoretical period of the sampled value message is measured; this is the dispersion of the message header, tested for 10 minutes. When there is clock input or output, the current time stamp is recorded using hardware time stamping. By controlling the delay time of the second pulse and the message sampled value header, a message with an adjustable delay time is output. Similarly, by measuring the hardware time stamp of the second pulse and the message sampled value header, the transmission delay time of the message is measured.

[0029] To better ensure compatibility with equipment from various provincial metrology centers, the message dispersion self-calibration device of the digital metrology system should include the following five functions:

[0030] (1) The device outputs sampled value messages to the device under test according to the set dispersion parameters, and calibrates the message dispersion test function of the device under test.

[0031] (2) The device receives the sampled value message from the device under test and measures the dispersion of the message in real time to calibrate the message transmission dispersion of the device under test.

[0032] (3) The device outputs a synchronization clock and a sampled value message simultaneously according to the set message transmission delay time parameter, thereby calibrating the message transmission delay time test function of the device under test.

[0033] (4) The device outputs a synchronization clock and a sampled value message simultaneously according to the set message transmission delay time parameter, thereby calibrating the message transmission delay time test function of the device under test.

[0034] (5) The device receives the sampled value message and message header synchronization signal of the device under test to calibrate the time stamp accuracy of the message of the device under test.

[0035] Furthermore, the FPGA uses Actel's ProASIC3 A3P1000 device, which is based on a flash memory architecture and supports the implementation of a soft ARM7 processor. It has 1 million system gates, 24,576 logic resources, one PLL, 32 4068-bit ARM blocks, 144kbits of dual-port SRAM, 300 user I / Os, and a maximum system clock frequency of 350MHz. In this embodiment, the A3P1000's clock frequency is designed to be 120MHz, controlling pulse signals and switching quantities, and using a high-speed parallel bus to interact with the DSP. The DSP selected is Analog Devices' Blakefin BF609 high-performance DSP processor. The FPGA is mainly used for tasks with extremely high real-time requirements, such as optical Ethernet, message transmission with varying discreteness, message header timing and synchronization pulse output, and synchronization clock processing. The BF609 is mainly used for tasks with lower real-time requirements, such as data display, parameter configuration, calibration process control, and communication tasks.

[0036] Message dispersion calibration:

[0037] The electronic instrument transformer testing platform is used to test the message dispersion performance of the merging unit output. In this experiment, a remote clock error calibration device simulates the SV message output by the merging unit, and the electronic instrument transformer testing platform measures the dispersion of this SV message. By setting the test mode and parameters of the remote clock error calibration device on a remote server, it is made to output SV messages with dispersions of 0μs, 5μs, and 10μs, respectively.

[0038] The maximum error between the maximum value and the preset value of all test results is 0.125μs, which is much less than the required 3μs, indicating that the electronic instrument transformer testing platform has passed the test. Furthermore, the data variation shows a maximum variation of 0.125μs, directly demonstrating that the SV message jitter output by the time error remote calibration device is very small, achieving the expected target.

[0039] Those skilled in the art will understand that embodiments of this invention can be provided as methods, systems, or computer program products. Therefore, this invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0040] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0041] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0042] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of this utility model and not to limit it. Although the utility model has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this utility model without departing from the spirit and scope of this utility model. Any modifications or equivalent substitutions should be covered within the scope of the claims of this utility model.

Claims

1. A message dispersion self-calibration module for a digital metering system, characterized in that, include: FPGA and DSP communication interface, pulse input / output interface, Ethernet interface, clock signal interface, and power supply module; The pulse input / output interface, Ethernet interface, and clock signal interface are respectively connected to the FPGA and DSP communication interfaces; The FPGA and DSP communication interface connects to the remote calibration local module. The clock signal interface connects to the BeiDou / GPS receiver; The pulse input / output interface provides clock output, clock input, and 4kHz input. Ethernet interface, used for message input and message output; The power supply module is used to power the message dispersion self-calibration module.

2. The module according to claim 1, characterized in that, The Beidou / GPS receiver outputs a high-precision 1PPS signal to the FPGA and DSP communication interface through the clock signal interface, and the FPGA and DSP communication interface generates a 100M high-stability clock.

3. The module according to claim 2, characterized in that, A highly stable clock, whose stability is consistent with that of the BeiDou / GPS satellite positioning system clock.

4. The module according to claim 1, characterized in that, The remote calibration local module is used to send self-calibration control commands to the message dispersion self-calibration module.

5. The module according to claim 1, characterized in that, Also includes: Based on a highly stable clock and real-time acquisition of Ethernet interface message input and output, the message dispersion calibration of the calibrated device is completed.

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