Communication protocol adapter based on FPGA and communication system

Abstract

The utility model discloses a communication protocol adapter based on an FPGA and a communication system. The communication system comprises a communication protocol adapter and a plurality of serial communication electronic devices. The communication protocol adapter comprises an FPGA chip, an Ethernet data transceiving unit and a serial data transceiving unit. And the serial communication electronic equipment is used as a Modbus slave station and is connected with the serial data transceiving unit which is used as a communication protocol adapter of the Modbus master station in a daisy chain manner. And the Ethernet data transceiving unit of the communication protocol adapter is connected with the Ethernet. A UDP data processing module and a Modbus transceiving control module which are connected are defined in the FPGA chip through a hardware description language, so that the FPGA chip can realize conversion between a UDP communication protocol and a Modbus communication protocol between the Ethernet data transceiving unit and the serial data transceiving unit. Compared with the mode of adopting a general processor, the FPGA chip mode adopted by the utility model has the advantages of low cost, low power consumption, low delay, high reliability, strong anti-interference capability and the like.

Description

Technical Field

[0001] This utility model relates to an adapter for converting communication protocols between Modbus and Ethernet. Background Technology

[0002] In the field of industrial control communication, high real-time performance is required. Ethernet, due to its packet-based transmission characteristics, has relatively poor real-time performance. However, with the development of network technology and the emergence of high-speed Ethernet such as Gigabit Ethernet, the problem of poor real-time performance has been gradually mitigated by its transmission speed, making it possible for Ethernet to enter the field of industrial control communication. Therefore, in control systems composed of different controlled electronic devices, some electronic devices use serial communication, while others use Ethernet communication. Thus, forming a unified network among these controlled electronic devices with different communication methods necessitates the conversion between different communication methods and protocols. Patent document CN1976354A discloses a general-purpose industrial protocol and Ethernet adapter based on a general-purpose processor. This adapter uses a general-purpose processor to execute a computer program to convert between the general-purpose industrial protocol and the Ethernet communication protocol. The pipelined operation of signals by the general-purpose processor results in poor signal real-time performance. Especially when there are many devices connected to the control system, the adapter's throughput performance often becomes a bottleneck for the control system's performance. The only way to improve this adapter throughput performance is often to use a high-performance processor, which often increases equipment costs. Summary of the Invention

[0003] The problem this invention aims to solve is the insufficient throughput, poor real-time performance, and high latency of general industrial protocols and Ethernet communication adapters implemented with general-purpose processors.

[0004] To solve the above problems, the present invention adopts the following solution:

[0005] According to the present invention, a communication protocol adapter based on FPGA includes an FPGA chip, an Ethernet data transceiver unit, and a serial data transceiver unit; the Ethernet data transceiver unit includes an Ethernet interface chip and an Ethernet communication interface; the serial data transceiver unit includes an RS485 transceiver and a serial communication interface; the FPGA chip is connected to the Ethernet interface chip and the RS485 transceiver, and is connected to the Ethernet communication interface and the serial communication interface respectively through the Ethernet interface chip and the RS485 transceiver.

[0006] Furthermore, the communication protocol adapter according to this utility model also includes a memory connected to the FPGA chip; the memory is an EPROM.

[0007] Furthermore, according to the communication protocol adapter of this utility model, both the Ethernet communication interface and the serial communication interface adopt RJ45 interface.

[0008] Furthermore, according to the communication protocol adapter of this utility model, there are multiple serial data transceiver units.

[0009] Furthermore, according to the communication protocol adapter of this utility model, the FPGA chip defines a connected UDP data processing module and a Modbus transceiver control module through a hardware description language.

[0010] Furthermore, according to the communication protocol adapter of this utility model, there are multiple serial data transceiver units; there are multiple Modbus transceiver control modules; each Modbus transceiver control module corresponds to each serial data transceiver unit.

[0011] A communication system according to the present invention includes the above-mentioned communication protocol adapter and several serial communication electronic devices; the communication protocol adapter is connected to an Ethernet network through the Ethernet data transceiver unit and is connected to each serial communication electronic device through the serial data transceiver unit.

[0012] Furthermore, according to the communication system of this utility model, the serial communication between the communication protocol adapter and each serial communication electronic device is based on the Modbus communication protocol; the communication protocol adapter acts as a Modbus master station; and each serial communication electronic device acts as a Modbus slave station.

[0013] Furthermore, according to the communication system of this utility model, each serial communication electronic device is connected to the communication protocol adapter in a daisy-chain manner.

[0014] The serial communication between the communication protocol adapter and each serial communication electronic device is based on the Modbus communication protocol; the communication protocol adapter, as a Modbus master, and each serial communication electronic device, as a Modbus slave, are connected in a daisy chain.

[0015] The technical effects of this invention are as follows: Compared with the use of a general-purpose processor, the use of an FPGA chip can significantly improve processing efficiency because of the hardware parallel processing capability of the FPGA chip, which can process Ethernet data frames and serial communication data frames in parallel. Furthermore, the FPGA chip processes data directly without the need for operating system scheduling and instruction decoding, resulting in lower latency. It also has lower power consumption and lower cost because it avoids unnecessary instruction execution and resource consumption of a general-purpose processor. In addition, the hardware implementation of the FPGA chip is more stable and reliable than software implementation, and it can better cope with electromagnetic interference, thereby improving the overall reliability of the system. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the overall structure of the industrial control network system according to an embodiment of this utility model.

[0017] Figure 2 This is a schematic diagram of the circuit structure of the communication protocol adapter according to an embodiment of this utility model.

[0018] In the above figures,

[0019] 100 is a communication protocol adapter, and 200 is a serial communication electronic device;

[0020] 11 is the FPGA chip, 110 is the UDP data processing module, 111 is the Gigabit Ethernet TEMAC module, and 112 is the UDP-IP chip.

[0021] The protocol stack module, 113 is the UDP command parsing module, and 114 is the status register module;

[0022] 12 is the Ethernet data transceiver unit, 121 is the Ethernet interface chip, and 122 is the Ethernet communication interface;

[0023] 13 is the serial data transceiver unit, 131 is the RS485 transceiver, and 132 is the serial communication interface.

[0024] 14 is the memory. Detailed Implementation

[0025] The present invention will now be described in further detail with reference to the accompanying drawings.

[0026] Figure 1 An industrial control network system is illustrated, comprising a communication protocol adapter 100, several serial communication electronic devices 200, and several Ethernet communication electronic devices arranged on a local area network (LAN) 300. The Ethernet communication electronic devices on the LAN 300 are connected to form the LAN 300 via network cables. The communication protocol adapter 100 connects to the LAN 300 and simultaneously connects to each of the serial communication electronic devices 200. The communication protocol adapter 100 and the serial communication electronic devices 200 constitute the communication system of this invention. That is, the communication system of this embodiment is a subsystem of the aforementioned industrial control network system. The Ethernet communication electronic devices on the LAN 300 are not within the scope of this invention and will not be described in detail.

[0027] The communication protocol adapter 100 includes at least an FPGA chip 11, an Ethernet data transceiver unit 12, and a serial data transceiver unit 13. The Ethernet data transceiver unit 12 includes an Ethernet interface chip 121 and an Ethernet communication interface 122. The serial data transceiver unit 13 includes an RS485 transceiver 131 and a serial communication interface 132. The FPGA chip 11 is connected to the Ethernet interface chip 121 and the RS485 transceiver 131, and is connected to the Ethernet communication interface 122 and the serial communication interface 132 respectively through the Ethernet interface chip 121 and the RS485 transceiver 131. Here, the RS485 transceiver means that the serial communication is based on the RS485 standard.

[0028] The communication protocol adapter 100 is connected to an Ethernet network, i.e., a local area network 300, via an Ethernet data transceiver unit 12, and to each serial communication electronic device 200 via a serial data transceiver unit 13. In this embodiment, the connection between the serial communication electronic devices 200 and the communication protocol adapter 100 adopts a daisy-chain configuration, i.e., the communication protocol adapter 100 is connected to the first serial communication electronic device 200, the first serial communication electronic device 200 is connected to the second serial communication electronic device 200, and so on. Those skilled in the art will understand that the connection between the serial communication electronic devices 200 and the communication protocol adapter 100 can also adopt a bus configuration.

[0029] In this embodiment, the FPGA chip 11 is the domestic FPGA chip PH1A100 from Anlu Company; the Ethernet interface chip 121 is a gigabit Ethernet PHY chip; and the RS485 transceiver 131 is the MAX3491 chip from Maxim Integrated.

[0030] In this embodiment, the communication protocol adapter 100 communicates with the Ethernet network based on the UDP / IP protocol, and the serial communication with each serial communication electronic device 200 is based on the Modbus communication protocol. When the communication protocol adapter 100 and each serial communication electronic device 200 perform serial communication based on the Modbus communication protocol, the communication protocol adapter 100 acts as the Modbus master station, and each serial communication electronic device 200 acts as a Modbus slave station. Therefore, referring to... Figure 2In this embodiment, the FPGA chip 11 defines a connected UDP data processing module 110 and a Modbus transceiver control module 119 using a hardware description language. The UDP data processing module 110 processes UDP / IP data packets and includes a gigabit TEMAC module 111, a UDP-IP protocol stack module 112, a UDP command parsing module 113, and a status register 114. In this embodiment, the logic circuits of the gigabit TEMAC module 111 and the UDP-IP protocol stack module 112 are hard-core IP modules generated by the IP Generator in the Anlu FPGA software. The gigabit TEMAC module 111 uses TEMAC_CORE, and the UDP-IP protocol stack module 112 uses udp_ip_protocal_stack. The UDP command parsing module 113 parses UDP packets according to private command definitions and performs corresponding processing according to the commands. Some status data from the processing performed by the UDP command parsing module 113 is stored in the status register module 114. The Modbus transceiver control module 119 is connected to the UDP command parsing module 113. The Modbus transceiver control module 119 reassembles UDP / IP data frames into Modbus data frames according to commands from the UDP command parsing module 113 and sends them to the RS485 transceiver 131, or reads Modbus data frames from the RS485 transceiver 131 and sends them to the UDP command parsing module 113. The status register module 114 uses 8 address lines to implement 256 internal status registers. The host computer can access these 256 internal status registers via the UDP / IP protocol, thereby enabling basic status queries and configuration of the communication protocol adapter 100.

[0031] In this embodiment, there are two serial data transceiver units 13. That is, there are two RS485 transceivers 131 and two serial communication interfaces 132. Each serial communication electronic device 200 is divided into two groups, and each group of serial communication electronic devices 200 is connected to one serial data transceiver unit 13. Correspondingly, to fully utilize the parallel processing capability of the FPGA chip 11, there are two Modbus transceiver control modules 119 in the FPGA chip 11. Each Modbus transceiver control module 119 is responsible for data reading, writing, or transmitting and receiving data for one serial data transceiver unit 13. Those skilled in the art will understand that multiple serial data transceiver units 13 can also be configured as needed, such as 3, 4, 5, etc. Each serial data transceiver unit 13 is configured with a corresponding Modbus transceiver control module 119.

[0032] In this embodiment, both the serial communication interface 132 and the Ethernet communication interface 122 are RJ45 interfaces. Those skilled in the art will understand that the serial communication interface 132 can also be other interfaces such as DB9.

[0033] Furthermore, in this embodiment, the communication protocol adapter 100 is also equipped with a memory 14. The memory 14 is connected to the FPGA chip 11. The memory 14 is used to store pre-configuration information, such as IP / MAC address information and other information that needs to be pre-configured. The FPGA chip 11 loads this pre-configuration information during power-on initialization. The memory 14 can be an EPROM or Flash, preferably an EEPROM.

Claims

1. A communication protocol adapter based on FPGA, characterized in that, It includes an FPGA chip, an Ethernet data transceiver unit, and a serial data transceiver unit; the Ethernet data transceiver unit includes an Ethernet interface chip and an Ethernet communication interface; the serial data transceiver unit includes an RS485 transceiver and a serial communication interface; the FPGA chip is connected to the Ethernet interface chip and the RS485 transceiver, and is connected to the Ethernet communication interface and the serial communication interface respectively through the Ethernet interface chip and the RS485 transceiver.

2. The communication protocol adapter according to claim 1, characterized in that, It also includes a memory connected to the FPGA chip; the memory is an EPROM.

3. The communication protocol adapter according to claim 1, characterized in that, Both the Ethernet communication interface and the serial communication interface use RJ45 interfaces.

4. The communication protocol adapter according to claim 1, characterized in that, There are multiple serial data transceiver units.

5. The communication protocol adapter according to claim 1, characterized in that, The FPGA chip contains a connected UDP data processing module and a Modbus transceiver control module defined using a hardware description language.

6. The communication protocol adapter according to claim 5, characterized in that, There are multiple serial data transceiver units; there are multiple Modbus transceiver control modules; each Modbus transceiver control module corresponds to each serial data transceiver unit.

7. A communication system, characterized in that, It includes a communication protocol adapter as described in any one of claims 1 to 6 and a plurality of serial communication electronic devices; the communication protocol adapter is connected to an Ethernet network through the Ethernet data transceiver unit and is connected to each serial communication electronic device through the serial data transceiver unit.

8. The communication system according to claim 7, characterized in that, The serial communication between the communication protocol adapter and each serial communication electronic device is based on the Modbus communication protocol; the communication protocol adapter acts as a Modbus master station. Each serial communication electronic device acts as a Modbus slave.

9. The communication system according to claim 7, characterized in that, Each serial communication electronic device is connected to the communication protocol adapter in a daisy-chain manner.

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