High-definition multi-path image processing device
By separating the SoC and FPGA and using a combination of video receiver, encoder and decoder, the problems of high cost and strong platform dependence in the prior art are solved, and flexible selection and efficient multi-channel high-quality image processing are achieved.
Patent Information
- Application Number
- CN202520003646.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-01-02
AI Technical Summary
In existing technologies, the integration design of FPGA and SoC is costly and highly platform-dependent, resulting in high prices and difficulty in flexible selection, as well as a decrease in overall speed and performance and an increase in system load.
By separating the SoC and FPGA, and using a combination of video receiver, video encoder, processor and encoder/decoder, signal transmission is achieved through PCIe interface and Ethernet PHY transceiver, directly outputting or compressing video signals, thus avoiding the use of additional converters.
It enables developers to flexibly choose between FPGA and SoC, reduce costs, improve processing performance, increase overall speed, reduce system load, and is suitable for multi-channel high-definition image processing.
Smart Images
Figure CN223843829U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a high-definition multi-channel image processing device, and more particularly to a device that separates the system-on-chip (SoC) and field-programmable gate array (FPGA), especially allowing developers to flexibly select the required FPGA and SoC, effectively reducing costs and improving processing performance, thereby increasing overall speed and reducing the system load of a personal computer (PC). Background Technology
[0002] Image signal processors included in digital imaging devices such as cameras and smartphones can perform image processing on raw images provided by image sensors and generate converted images. This includes converting the data format of the raw image into data formats such as red-green-blue (RGB) images and / or YUV images. The converted images can be compressed based on compression technologies such as the JPEG image compression standard (joint photographic experts group, JPEG), the MPEG video compression standard (moving picture experts group, MPEG), and H.264, and the converted images can be stored in memory and / or displayed on a display device.
[0003] The current technology for image signal processors integrates FPGAs into SoCs. However, the disadvantages of this integrated design are high integration costs, resulting in expensive prices, and strong platform dependence. Once the design is finalized, the product will depend on a specific model of SoC, making platform switching difficult and preventing developers from flexibly choosing the required FPGA and SoC. This is detrimental to the product's market competitiveness and urgently needs to be improved.
[0004] Furthermore, traditional image signal processors that convert raw signals into compressed signals require a separate transformer at the physical layer (PHY) output of an Ethernet transmitter to perform the conversion before outputting the image signal. Moreover, when used for Ethernet transmission, there are many packet headers, or additional headers are necessary, which reduces overall speed and performance because the increased time spent processing packet headers leads to a higher system load on the PC. If the raw signal is not converted into a compressed signal, as is the case with conventional techniques that directly perform software compression on the PC, PC performance will decrease. While a high-performance PC can be chosen, this requires higher costs. Therefore, it is essential to develop a new utility model that solves these image processing problems and addresses the shortcomings of existing technologies. Utility Model Content
[0005] The main purpose of this invention is to overcome the above-mentioned problems in the prior art and provide a high-quality multi-channel image processing device that allows developers to flexibly select the required FPGA and SoC, effectively reduces costs, improves processing performance, enhances overall speed, and thus reduces the system load of the PC.
[0006] To achieve the above objectives, the present invention provides a high-quality multi-channel image processing device comprising:
[0007] A video receiver is used to receive multiple raw video signals of 4K or higher resolution and perform format conversion processing to generate and output the converted raw video signals.
[0008] A video encoder, connected to the video receiver, is used to directly output the original video signal after the format conversion, or to encode it to generate and output the encoded original video signal.
[0009] A processor, connected to the video encoder, has a first Ethernet PHY transceiver for transmitting the format-converted raw video signal to a host computer via a high-speed serial computer extended bus standard (Peripheral Component Interconnect Express, PCIe) interface; and
[0010] An encoder-decoder, connected to the video encoder, has a second Ethernet PHY transceiver. The encoder-decoder is used to compress the encoded original video signal to generate a compressed original video signal, and transmits the network packet containing the compressed original video signal directly to the processor via the first and second Ethernet PHY transceivers in the form of network packets. The processor extracts the compressed original video signal from the packet and then transmits it to the host via the PCIe interface, where the host decompresses it.
[0011] In the above embodiments of this utility model, the video encoder is a Mobile Industry Processor Interface (MIPI) encoder.
[0012] In the above embodiments of this utility model, the encoder-decoder is a system-on-a-chip (SoC H.26X).
[0013] In the above embodiments of this utility model, the processor is an FPGA.
[0014] In the above embodiments of this utility model, the original video signal with a resolution of 4K or above is a High Definition Multimedia Interface (HDMI) signal, a Serial Digital Interface (SDI) signal, or a combination thereof.
[0015] In the above embodiments of this utility model, the original video signal after format conversion is in red-green-blue (RGB) format, YUV format, or I... 2 S (Inter-IC Sound) format.
[0016] In the above embodiments of this utility model, the encoded original video signal is in MIPI format or I... 2 S format.
[0017] In the above embodiments of this utility model, the host is a server or a PC host. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the block architecture of one embodiment of the present invention.
[0019] In the figure
[0020] 100-High-definition multi-channel image processing device;
[0021] 1-Video receiver;
[0022] 2-Video encoder;
[0023] 3-Processor;
[0024] 31 - First Ethernet PHY transceiver;
[0025] 32-PCIe interface;
[0026] 4-Encoder / Decoder;
[0027] 41 - Second Ethernet PHY transceiver;
[0028] 5-Host. Detailed Implementation
[0029] Please see Figure 1 As shown, this embodiment provides a high-quality multi-channel image processing device 100, which includes a video receiver 1, a video encoder 2, a processor 3, and an encoder-decoder 4.
[0030] The video receiver 1 is used to receive multiple raw video signals with a resolution of 4K or higher and perform format conversion processing to generate and output the converted raw video signals.
[0031] The video encoder 2 is connected to the video receiver 1 and is used to directly output the original video signal after the format conversion, or to encode it to generate and output the encoded original video signal.
[0032] The processor 3 is connected to the video encoder 2 and has a first Ethernet PHY transceiver 31. The processor 3 is used to transmit the original video signal after format conversion to a host 5 through a high-speed serial computer extended bus standard (Peripheral Component Interconnect Express, PCIe) interface 32.
[0033] The encoder-decoder 4 is connected to the video encoder 2 and has a second Ethernet PHY transceiver 41. The encoder-decoder 4 compresses the encoded original video signal to generate a compressed original video signal, and transmits the network packet containing the compressed original video signal directly to the processor 3 via the first Ethernet PHY transceiver 31 and the second Ethernet PHY transceiver 41 using network packets. The processor 3 extracts the compressed original video signal from the packet and transmits it to the host 5 via the PCIe interface 32, where the host 5 decompresses it. Thus, the disclosed apparatus constitutes a novel high-definition multi-channel image processing apparatus 100.
[0034] In a preferred embodiment of this utility model, the video encoder 2 is a Mobile Industry Processor Interface (MIPI) encoder.
[0035] In a preferred embodiment of the present invention, the processor 3 is a field programmable gate array (FPGA).
[0036] In a preferred embodiment of this utility model, the encoder-decoder 4 is a system chip (SoCH.26X).
[0037] In a preferred embodiment of this utility model, the host is a server or a computer (PC) host.
[0038] In use, the high-definition multi-channel image processing device 100 of this invention receives 4 to 8 channels of original video signals with a resolution of 4K or higher, such as High Definition Multimedia Interface (HDMI) signals, Serial Digital Interface (SDI) signals, or combinations thereof, through the video receiver 1 and performs format conversion, converting the original HDMI and / or SDI video signals into red-green-blue (RGB) format, YUV format, or I... 2 S (Inter-IC Sound) format, then the unencoded RGB, YUV, or I format is processed by MIPI's video encoder 2. 2 The raw S-format video signal is directly transmitted to the FPGA processor 3, which then transmits it to the host 5 via the PCIe interface 32. Additionally, the video encoder 2 can also convert RGB, YUV, or I-format video signals. 2 The original S-format video signal is further encoded into MIPI format, or I-format. 2The S-format video signal is then converted into a compressed original video signal by the SoC H.264 or H.265 encoder / decoder 4. This compressed original video signal is then transmitted via network packets using the high-definition multi-channel image processing device 100 of this invention through Ethernet technology. The device is equipped with a first Ethernet PHY transceiver 31 and a second Ethernet PHY transceiver 41, enabling data transmission between them. This eliminates the need for an additional converter; the high-definition multi-channel image processing device 100 can directly transmit the compressed original video signal via the first Ethernet PHY transceiver 31 and the second Ethernet PHY transceiver 41 to the processor 3. Once the processor 3 extracts the compressed original video signal from the packet, it can transmit it to the host 5 via the PCIe interface 32, thus enabling the device to process video signals of 4K and above.
[0039] Therefore, this invention separates the SoC and FPGA, allowing developers to flexibly choose the required FPGA and SoC, effectively reducing costs and improving processing performance, thereby increasing overall speed and reducing the PC's system load, enabling the device to perform multi-channel high-definition image processing.
[0040] In summary, the high-definition multi-channel image processing device of this invention effectively improves upon the shortcomings of existing devices. By separating the system-on-chip (SoC) and the field-programmable gate array (FPGA), developers can flexibly choose the required FPGA and SoC, effectively reducing costs and improving processing performance, thereby increasing overall speed and reducing the system load on the personal computer (PC). This allows the device to perform multi-channel high-definition image processing, making this invention more advanced, practical, and user-friendly, thus meeting the requirements for a utility model patent application. Therefore, a patent application is filed in accordance with the law.
[0041] The above-disclosed embodiments are merely preferred embodiments of this utility model and should not be construed as limiting the scope of protection of this utility model. Therefore, any simple equivalent changes and modifications made in accordance with the scope of the patent application and the content of the specification of this utility model shall fall within the scope of this utility model patent.
Claims
1. A high-definition multi-channel image processing device, characterized in that... include: A video receiver is used to receive multiple raw video signals of 4K or higher resolution and perform format conversion processing to generate and output the converted raw video signals. A video encoder, connected to the video receiver, is used to directly output the original video signal after the format conversion, or to encode it to generate and output the encoded original video signal. A processor, connected to the video encoder, has a first Ethernet PHY transceiver, the processor being used to transmit the format-converted raw video signal to a host computer via a high-speed serial computer expansion bus standard interface; and An encoder-decoder, connected to the video encoder, has a second Ethernet PHY transceiver. The encoder-decoder is used to compress the encoded original video signal to generate a compressed original video signal, and transmits the network packets containing the compressed original video signal directly to the processor via the first Ethernet PHY transceiver and the second Ethernet PHY transceiver in the form of network packets. The processor extracts the compressed original video signal from the packets and then transmits it to the host via the high-speed serial computer expansion bus standard interface, where the host decompresses it.
2. The high-quality multi-channel image processing apparatus according to claim 1, characterized in that, The video encoder is a mobile industry processor interface encoder.
3. The high-quality multi-channel image processing apparatus according to claim 1, characterized in that, The encoder / decoder is a system chip.
4. The high-quality multi-channel image processing apparatus according to claim 1, characterized in that, The processor is a field-programmable gate array (FPGA).
5. The high-quality multi-channel image processing apparatus according to claim 1, characterized in that, The original video signal with a resolution of 4K or higher is a high-definition multimedia interface signal, a serial digital interface signal, or a combination thereof.
6. The high-quality multi-channel image processing apparatus according to claim 1, characterized in that, The original video signal after format conversion is in RGB format, YUV format, or I... 2 S format.
7. The high-quality multi-channel image processing apparatus according to claim 1, characterized in that, The encoded original video signal is in MIPI format or I... 2 S format.
8. The high-quality multi-channel image processing apparatus according to claim 1, characterized in that, The host is a server or a computer host.