High-definition multi-path image processing structure

Abstract

The utility model discloses a high-definition multi-path image processing structure, which comprises a shell, at least one network interface arranged on the shell, a processor arranged in the shell, a video decoder arranged in the shell and connected with the network interface and the processor, and a processor arranged in the shell and connected with the network interface and the processor. And the video receiver is arranged in the shell and is connected with the video decoder and the processor. Therefore, the system chip (system-on-chip, SoC) and the field programmable gate array (field programmable gate array, FPGA) are separately arranged, so that the required FPGA and SoC can be flexibly selected for development, the cost can be effectively reduced, the processing efficiency can be improved, the overall speed can be improved, the system load of a personal computer (PC) is reduced, and the development cost of the system chip (system-on-chip, SoC) and the development cost of the system chip (system-on-chip, SoC) can be reduced. Therefore, the structure of the utility model can carry out multi-path high-quality image processing.

Description

Technical Field

[0001] This utility model relates to a high-quality multi-channel image processing structure, and more particularly to a structure that separates the system-on-chip (SoC) and the field-programmable gate array (FPGA). Specifically, it allows developers to flexibly select the required FPGA and SoC, effectively reducing costs and improving processing performance, thereby increasing overall speed and reducing the system load on a personal computer (PC). Background Technology

[0002] Image signal processors included in digital imaging devices such as cameras and smartphones can perform image processing on raw images provided by image sensors and generate converted images. This includes converting the data format of the raw image into data formats such as red-green-blue (RGB) images and / or YUV images. The converted images can be compressed and decompressed based on compression and decompression technologies such as the JPEG image compression standard (joint photographic experts group, JPEG), the MPEG video compression standard (moving picture experts group, MPEG), and H.264, and the converted images can be stored in memory and / or displayed on a display device.

[0003] Current technology for image signal processors integrates FPGAs into SoCs. However, this integrated design has the disadvantages of high cost, resulting in expensive products, and strong platform dependence. Once the design is finalized, the product becomes dependent on a specific SoC model, making platform switching difficult and preventing developers from flexibly choosing the required FPGA and SoC. This is detrimental to the product's market competitiveness and urgently needs improvement.

[0004] Furthermore, traditional image signal processors that convert raw signals into compressed signals require a separate transformer at the physical layer (PHY) output of an Ethernet transmitter to perform the conversion before outputting the image signal. Moreover, Ethernet transmission involves numerous packet headers, or necessitates additional headers, which reduces overall speed and performance due to the increased time spent processing packet headers, leading to a higher system load on the PC. If the raw signal is not converted to compressed signal, and conventional techniques allow for direct software decompression by the PC, PC performance will decrease. While a high-performance PC can be chosen, this incurs higher costs. Therefore, developing a new utility model that solves these image processing problems and addresses the shortcomings of existing technologies is essential. Utility Model Content

[0005] The main purpose of this invention is to overcome the above-mentioned problems in the prior art and provide a high-quality multi-channel image processing structure that allows developers to flexibly select the required FPGA and SoC, effectively reduce costs, improve processing performance, enhance overall speed, and thus reduce the system load of the PC.

[0006] To achieve the above objectives, the present invention provides a high-quality multi-channel image processing structure comprising:

[0007] A housing; at least one network interface disposed on the housing for receiving and outputting multiple raw video signals from network audio and video (AV over IP), wherein the raw video signals are uncompressed raw video signals or compressed raw video signals.

[0008] A processor, housed within the housing, has a first Ethernet PHY transceiver for transmitting a format-converted raw video signal to a host via a high-speed serial computer extended bus standard (Peripheral Component Interconnect Express, PCIe) interface;

[0009] A video decoder, housed in the housing and connected to the network interface and the processor, includes a second Ethernet PHY transceiver for decompressing the compressed original video signal to generate and output the decompressed original video signal. It also transmits the uncompressed or compressed original video signal, or the original video signal itself, directly to the processor via network packets through the first and second Ethernet PHY transceivers. The processor extracts the uncompressed or compressed original video signal from the packets and transmits it to the host computer via the PCIe interface for direct viewing, decompression, or storage. A video receiver, also housed in the housing and connected to the decoder and processor, receives the decompressed original video signal, performs format conversion processing, and generates and outputs the converted original video signal to the processor.

[0010] In the above embodiments of this utility model, the network interface is an RJ-45 interface or an Ethernet RJ-45 interface.

[0011] In the above embodiments of this utility model, the video decoder is a system-on-a-chip (SoC).

[0012] In the above embodiments of this utility model, the processor is a field-programmable gate array (FPGA).

[0013] In the above embodiments of this utility model, the original video signal of the network audio and video is a network audio and video (AVover IP) network transmission protocol or a combination thereof, which is a Network Device Interface (NDI), GigE Vision, Real-Time Streaming Protocol (RTSP), or Real-Time Messaging Protocol (RTMP).

[0014] In the above embodiments of this utility model, the host is a server or a computer (PC) host.

[0015] In the above embodiments of this utility model, the original video signal after format conversion is in red-green-blue (RGB) format, YUV format, or I... 2 S (Inter-IC Sound) format. Attached Figure Description

[0016] Figure 1 This is a structural schematic diagram of one embodiment of the present invention.

[0017] In the figure

[0018] 100-High-definition multi-channel image processing structure;

[0019] 1-Shell;

[0020] 2-Network interface;

[0021] 3-Processor;

[0022] 31 - First Ethernet PHY transceiver;

[0023] 32-PCIe interface;

[0024] 4-Video decoder;

[0025] 41 - Second Ethernet PHY transceiver;

[0026] 5-Video receiver;

[0027] 6-Host. Detailed Implementation

[0028] like Figure 1 As shown: The high-definition multi-channel image processing structure 100 of this embodiment includes a housing 1, at least one network interface 2, a processor 3, a video decoder 4, and a video receiver 5.

[0029] The network interface 2 is located on the housing 1 and is used to receive and output multiple raw video signals from network audio and video (AV over IP); wherein the raw video signal is an uncompressed raw video signal or a compressed raw video signal.

[0030] The processor 3 is located in the housing 1 and has a first Ethernet PHY transceiver 31. The processor is used to transmit a format-converted raw video signal to a host 6 through a high-speed serial computer extended bus standard (Peripheral Component Interconnect Express, PCIe) interface 32.

[0031] The video decoder 4 is located in the housing 1 and connected to the network interface 2 and the processor 3. It has a second Ethernet PHY transceiver 41, which is used to decompress the compressed original video signal to generate and output the decompressed original video signal. The uncompressed original video signal or the compressed original video signal is transmitted directly to the processor 3 via the first Ethernet PHY transceiver 31 and the second Ethernet PHY transceiver 41 using network packets. The processor 3 extracts the uncompressed or compressed original video signal from the packet and transmits it to the host 6 via the PCIe interface 32. The host 6 can then directly view the signal or decompress it for viewing or storage.

[0032] The video receiver 5 is housed in the housing 1 and connected to the processor 3 and the video decoder 4. It receives the decompressed original video signal, performs format conversion processing to generate and output the format-converted original video signal to the processor 3. Thus, the above-disclosed structure constitutes a novel high-definition multi-channel image processing structure 100.

[0033] In a preferred embodiment of this utility model, the video decoder 4 is a system-on-a-chip (SoC H.26X), such as SoC H.264 or SoC H.265.

[0034] In a preferred embodiment of this utility model, the original video signal of the network audio and video is a network audio and video (AVover IP) network transmission protocol or a combination thereof, such as Network Device Interface (NDI), GigE Vision, Real-Time Streaming Protocol (RTSP), or Real-Time Messaging Protocol (RTMP).

[0035] In a preferred embodiment of the present invention, the processor 3 is a field programmable gate array (FPGA).

[0036] In a preferred embodiment of this utility model, the host 6 is a server or a computer (PC) host.

[0037] When used, the high-quality multi-channel image processing structure 100 of this embodiment can be used by a network audio and video (AV over IP) transmission system. Through the network interface 2, the original video signals of 4 to 8 channels of network audio and video are transmitted to the SoC H.264 or SoC H.265 video decoder 4 via the Ethernet RJ-45 interface. This original video signal can be an uncompressed or compressed original video signal. The video decoder 4 uses network packets. Utilizing the high-definition multi-channel image processing structure 100 of this embodiment, it employs Ethernet technology and is equipped with a first Ethernet PHY transceiver 31 and a second Ethernet PHY transceiver 41 for data transmission. This allows the high-definition multi-channel image processing structure 100 of this embodiment to transmit data directly using the first Ethernet PHY transceiver 31 and the second Ethernet PHY transceiver 41 without the need for an additional converter. The network packet containing the uncompressed or compressed original video signal is then transmitted to the processor 3 of the FPGA. After the processor 3 extracts the uncompressed or compressed original video signal from the packet, it can transmit the uncompressed or compressed original video signal to the host 6 via the PCIe interface 32. The host 6 can then directly view the signal or decompress it for viewing or storage. Additionally, the video decoder 4 can also encode the compressed original video signal into a decompressed original video signal, such as the original HDMI 2.0 video signal. The video receiver 5 performs format conversion, transforming the original HDMI 2.0 video signal into red-green-blue (RGB) format, YUV format, or I... 2 After being formatted as S (Inter-ICSound), the signal is directly transmitted to the processor 3, which then transmits it to the host 6 via the PCIe interface 32. The host 6 can then directly view the signal, decompress it, and then view or store it. This enables the high-definition multi-channel image processing structure 100 of this embodiment to process network audio and video (AV over IP) transmission signals. Furthermore, the network interface 2 can also be an RJ-45 interface for use with other lines transmitting video signals.

[0038] Therefore, by separating the SoC and FPGA, the present invention allows developers to flexibly select the required FPGA and SoC, effectively reducing costs and improving processing performance, thereby increasing overall speed and reducing the system load of the PC. This allows the structure of this embodiment to perform multi-channel high-definition image processing.

[0039] In summary, this utility model is a high-definition multi-channel image processing structure that effectively improves upon various shortcomings of existing technologies. By separating the system-on-chip (SoC) and the field-programmable gate array (FPGA), developers can flexibly choose the required FPGA and SoC, effectively reducing costs and improving processing performance, thereby increasing overall speed and reducing the system load on the personal computer (PC). This allows the structure of this utility model to perform multi-channel high-definition image processing, making it more advanced, practical, and user-friendly, thus meeting the requirements for a utility model patent application. Therefore, this patent application is filed in accordance with the law.

[0040] The above-disclosed embodiments are merely preferred embodiments of this utility model and should not be construed as limiting the scope of protection of this utility model. Therefore, any simple equivalent changes and modifications made in accordance with the scope of the patent application and the content of the specification of this utility model shall fall within the scope of this utility model patent.

Claims

1. A high-quality multi-channel image processing structure, characterized in that... include: A shell; At least one network interface is provided on the housing for receiving and outputting multiple channels of network audio and video raw video signals, wherein the raw video signals are uncompressed raw video signals or compressed raw video signals. A processor, located in the housing, has a first Ethernet PHY transceiver, which is used to transmit a format-converted raw video signal to a host via a high-speed serial computer extended bus standard interface. A video decoder, housed within the housing and connected to the network interface and the processor, includes a second Ethernet PHY transceiver for decompressing the compressed original video signal to generate and output the decompressed original video signal. It also transmits the uncompressed or compressed original video signal, or the original video signal itself, directly to the processor via network packets through the first and second Ethernet PHY transceivers. The processor extracts the uncompressed or compressed original video signal from the packets and transmits it to the host computer via the high-speed serial computer expansion bus standard interface. The host computer can then directly view the signal, decompress it, or store it. A video receiver, housed in the housing and connected to the video decoder and the processor, is used to receive the decompressed original video signal and perform format conversion processing to generate and output the format-converted original video signal to the processor. The processor transmits the signal to the host computer via the high-speed serial computer expansion bus standard interface, where the host computer can directly view or store it.

2. The high-quality multi-channel image processing structure according to claim 1, characterized in that, The network interface is an RJ-45 interface or an Ethernet RJ-45 interface.

3. The high-quality multi-channel image processing structure according to claim 1, characterized in that, The video decoder is a system chip.

4. The high-quality multi-channel image processing structure according to claim 1, characterized in that, The processor is a field-programmable gate array.

5. The high-quality multi-channel image processing structure according to claim 1, characterized in that, The original video signal of the network audio and video is a network audio and video network transmission protocol or a combination thereof, which is a network device interface, Gigabit Ethernet vision, real-time streaming media protocol or real-time messaging protocol.

6. The high-quality multi-channel image processing structure according to claim 1, characterized in that, This host is a server or computer host.

7. The high-quality multi-channel image processing structure according to claim 1, characterized in that, The original video signal after this format conversion is in RGB, YUV, or I format. 2 S format.

Images