Wafer-level chip integrated structure

Abstract

The embodiment of the utility model discloses a wafer level chip integrated structure. The wafer-level chip integrated structure comprises a plurality of functional components; the plurality of functional components are arranged in an array; the functional component comprises a first functional chip, a second functional chip and a retiming unit; the second functional chips are arranged around the first functional chip in an array manner; the retiming unit is arranged between the second functional chips arranged in the array; the first functional chips are connected through a retiming unit; the retiming unit is used for regenerating and retiming the signal. According to the technical scheme provided by the embodiment of the utility model, the second functional chips are arranged around the first functional chip in the array manner, the re-timing units are arranged among the second functional chips arranged in the array manner to form the functional components, and the plurality of functional components are arranged in the array manner to form the wafer-level chip integrated structure, so that the chip performance is improved, the integration level is improved, and the production cost is reduced. And stable transmission of signals between the chips is ensured.

Description

Technical Field

[0001] This utility model relates to the field of chip manufacturing technology, and in particular to a wafer-level chip integration structure. Background Technology

[0002] In the current development of chip technology, as various electronic devices continue to increase their performance requirements for computing speed, storage capacity, and power consumption, chip integration faces many challenges.

[0003] In existing chip integration models, the connections between functional chips are complex, signal transmission is susceptible to interference, and signal delay is significant, greatly limiting the improvement of overall chip performance. At the same time, the limited wafer area makes it difficult to accommodate more high-performance chips, hindering breakthroughs in balancing integration and performance and failing to meet the growing market demand. For example, NVIDIA's B200 chip integrates 10 chips, resulting in low integration; Tesla's Dojo chip uses a fully isomorphic structure, but storage needs to cross Dual In-line Package (DIP) cards, leading to signal delay issues. Utility Model Content

[0004] This invention provides a wafer-level chip integration structure to solve the problems of unstable signal transmission, limited integration and insufficient performance in existing chip integration technologies, thereby improving chip performance and making efficient use of space.

[0005] According to one aspect of the present invention, a wafer-level chip integration structure is provided, the wafer-level chip integration structure comprising: multiple functional components; the multiple functional components are arranged in an array;

[0006] The functional components include a first functional chip, a second functional chip, and a retiming unit;

[0007] The second functional chip array is arranged around the first functional chip; the retiming unit is arranged between the second functional chips in the array.

[0008] The first functional chips are connected through a retiming unit; the retiming unit is used to regenerate and retime signals.

[0009] Optionally, the functional components also include an interface unit; the interface unit is disposed around the perimeter of the first functional chip;

[0010] The interface unit is used to enable communication between the first functional chips.

[0011] Optionally, the number of retiming units is the same as the number of interface units.

[0012] Optionally, the first functional chip includes a computing chip; the second functional chip includes a storage chip.

[0013] Optionally, the computing chip may include a central processing unit, a graphics processing unit, a data processing unit, or a digital signal processor;

[0014] Memory chips include dynamic random access memory, static random access memory, or read-only memory.

[0015] Optionally, the computing chip and the memory chip are interconnected by bonding.

[0016] Optionally, the retiming unit includes a retimer.

[0017] Optionally, the number of functional components is positively correlated with the area of ​​the wafer.

[0018] Optionally, at least four second functional chips arranged in an array are provided on each side of the first functional chip;

[0019] At least one retiming unit is provided on each side of the first functional chip.

[0020] Optionally, the wafer-level chip integration structure includes at least 16 functional components.

[0021] The technical solution of this utility model embodiment, in high-speed circuit system design, applies a retiming unit connected to the first functional chip to compensate for signal channel losses, eliminate jitter, regenerate and retime signals, and enhance signal integrity. Data is extracted and resynchronized through the clock data recovery circuit inside the retiming unit, improving the reliability and stability of signal transmission. In a wafer-level heterogeneous integrated structure, in addition to the first and second functional chips, the retiming unit is incorporated into the overall system design, ensuring that communication between the first functional chips is not affected by the layout of the second functional chip, thereby improving communication bandwidth.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1This is a schematic diagram of a wafer-level chip integration structure provided according to an embodiment of the present utility model;

[0025] Figure 2 This is a schematic diagram of the structure of a functional component in a wafer-level chip integration structure according to an embodiment of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] Figure 1 This is a schematic diagram of a wafer-level chip integration structure provided according to an embodiment of the present utility model. Figure 2 This is a schematic diagram of the structure of a functional component in a wafer-level chip integration structure according to an embodiment of the present invention. Figure 1 and Figure 2 As shown, the wafer-level chip integration structure includes: multiple functional components 100; the multiple functional components 100 are arranged in an array; each functional component 100 includes a first functional chip 101, a second functional chip 102, and a retiming unit 103; the second functional chips 102 are arranged in an array around the first functional chip 101; the retiming unit 103 is disposed between the arrayed second functional chips 102; the first functional chips 101 are connected to each other through the retiming unit 103; the retiming unit 103 is used to regenerate and retime signals.

[0029] In this embodiment of the invention, the first functional chip 101 is used to provide the computing power required for the application scenario. For example, the first functional chip 101 may be a computing chip. The second functional chip 102 is used to provide the high-bandwidth memory required for the application scenario. For example, the second functional chip 102 may be a storage chip. The second functional chips 102 are arranged in an array around the first functional chip 101, optimizing the layout. The first functional chip 101 and the second functional chip 102 are arranged adjacent to each other, satisfying the design rules of advanced packaging.

[0030] The first functional chips 101 need to communicate with each other to form a computing network. In existing technologies, to achieve communication between the first functional chips 101, it is necessary to cross the height of at least one second functional chip 102, typically with a height greater than 5 millimeters. This requires interfaces with strong driving capabilities, leading to a decrease in communication density and bandwidth. Furthermore, it results in long-distance wiring, reducing signal integrity and communication speed. In this embodiment of the invention, a retiming unit 103 is provided between the arrayed second functional chips 102 to connect the first functional chips 101, compensate for signal channel losses, eliminate jitter, regenerate and retime signals, enhance signal integrity, and extract and resynchronize data through the clock data recovery circuit inside the retiming unit 103, thereby improving the reliability and stability of signal transmission.

[0031] A functional component 100 is formed by arranging second functional chips 102 in an array around the first functional chip 101 and setting retiming units 103 between the arrayed second functional chips 102. Multiple functional components 100 are arranged in an array to form a wafer-level chip integration structure, increasing integration density and using a heterogeneous structure to solve the interconnection problem between heterogeneous chips.

[0032] The technical solution of this utility model embodiment, in high-speed circuit system design, applies a retiming unit connected to the first functional chip to compensate for signal channel losses, eliminate jitter, regenerate and retime signals, and enhance signal integrity. Data is extracted and resynchronized through the clock data recovery circuit inside the retiming unit, improving the reliability and stability of signal transmission. In a wafer-level heterogeneous integrated structure, in addition to the first and second functional chips, the retiming unit is incorporated into the overall system design, ensuring that communication between the first functional chips is not affected by the layout of the second functional chip, thereby improving communication bandwidth.

[0033] Based on the above-described technical solutions of the utility model embodiments, and referring to... Figure 1 and Figure 2The functional component 100 also includes an interface unit 104; the interface unit 104 is disposed around the first functional chip 101; the interface unit 104 is used to realize communication between the first functional chips 101.

[0034] In this embodiment of the invention, the interface unit 104 serves as a communication interface between the first functional chips 101 in different functional components 100. The first functional chips 101 in different functional components 100 are connected via a retiming unit 103, reducing long-distance wiring. One end of the retiming unit 103 is connected to the first functional chip 101 via the interface unit 104, enabling communication between the first functional chips 101 in different functional components 100. This improves communication efficiency between chips while ensuring signal integrity.

[0035] Based on the above-described technical solutions of the utility model embodiments, and referring to... Figure 1 and Figure 2 The number of retiming units 103 is the same as the number of interface units 104.

[0036] In this embodiment of the invention, interface units 104 are disposed around the first functional chip 101, and the first functional chips 101 communicate and connect with each other through the interface units 104 and the retiming units 103. Therefore, the number of retiming units 103 is the same as the number of interface units 104. While ensuring that the first functional chips 101 can communicate and connect with each other, the layout design is optimized, the integration density of the wafer-level chip is increased, chip performance is optimized, and power consumption and cost are reduced.

[0037] In an optional embodiment of this utility model, reference is made to... Figure 1 and Figure 2 The first functional chip 101 includes a computing chip; the second functional chip 102 includes a storage chip.

[0038] In this embodiment of the invention, the first functional chip 101 and the second functional chip 102 constitute a heterogeneous structure. The first functional chip 101 is used to provide the computing power required for the application scenario. The second functional chip 102 is used to provide the high-bandwidth memory required for the application scenario.

[0039] In optional embodiments of this invention, the computing chip includes a central processing unit, a graphics processing unit, a data processing unit, or a digital signal processor; the storage chip includes a dynamic random access memory, a static random access memory, or a read-only memory.

[0040] In this embodiment of the invention, the first functional chip 101 includes a computing chip, which includes, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), or a digital signal processor (DSP). The CPU is the core component of a computer system, responsible for executing instructions, performing arithmetic and logic operations, and controlling the overall operation of the computer. The GPU is mainly used for processing graphics data and has wide applications in image rendering, video decoding, and artificial intelligence. The DPU is a dedicated processor for processing data, which can share some of the workload of the CPU and improve data processing efficiency. The DSP is used for real-time processing of digital signals. The computing chip can also be a field-programmable gate array (FPGA) or a neuromorphic chip.

[0041] The second functional chip 102 includes a memory chip, which includes, but is not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), or read-only memory (ROM). DRAM is a volatile memory characterized by large capacity, low cost, and high speed. SRAM is also a volatile memory, but it is faster than DRAM. ROM is a non-volatile memory used to store fixed programs and data. The memory chip can also be flash memory, phase-change memory, resistive random access memory (RRAM), or magnetoresistive memory (MRMemory).

[0042] Based on the above-described technical solutions of the utility model embodiments, and referring to... Figure 1 and Figure 2 The computing chip and the memory chip are interconnected by bonding.

[0043] In this embodiment of the invention, the computing chip is a first functional chip 101, and the storage chip is a second functional chip 102. The computing chip and the storage chip are interconnected during the integrated circuit packaging process via bonding technology to achieve electrical connection and signal transmission between them. Bonding is a process of connecting different chips or electronic components together. Bonding methods include, but are not limited to, wire bonding, flip chip bonding, and through-silicon via bonding.

[0044] When a computing chip performs calculations, it needs to read data from a memory chip, process it, and then write the results back to the memory chip. Connecting the computing chip and the memory chip using bonding technology ensures fast and accurate data transfer between them, meeting the real-time data access requirements of the computing process. For example, when a computer runs a program, the central processing unit (CPU) continuously reads instructions and data from memory for processing and then stores the processing results back into memory.

[0045] The computing chip and the memory chip are interconnected via bonding, enabling signal synchronization and collaborative operation between them. For example, the transmission of clock signals allows the memory chip to prepare data at the appropriate time for the computing chip to read, ensuring stable operation of the entire system. In addition to transmitting data and signals, the computing chip can also distribute power to the memory chip via bonding wires, providing the necessary electrical energy for the memory chip's operation.

[0046] Based on the above-described technical solutions of the utility model embodiments, and referring to... Figure 1 and Figure 2 The retiming unit 103 includes a retimer.

[0047] In this embodiment of the invention, a retimer is used to connect the first functional chip 101 in different functional components 100. A retimer is an integrated circuit chip used to recover and retime high-speed signals. In high-speed data transmission systems, signals may experience signal attenuation and jitter after long-distance transmission or complex circuit board wiring. The retimer can receive these damaged signals, reshape and regenerate them, and then retransmit them according to the original clock or a new reference clock to ensure signal integrity and accuracy. The retimer first uses its internal clock recovery circuit to extract clock information from the input signal stream; then, based on the extracted clock, it resamples the signal to remove jitter and other adverse effects introduced during transmission; finally, it retimes the resampled signal according to the recovered clock or a high-quality external clock signal for output. Retimers are commonly used in board-level design and are readily available in the chip supply market, with controllable costs.

[0048] Based on the above-described technical solutions of the utility model embodiments, and referring to... Figure 1 and Figure 2 The number of functional components 100 is positively correlated with the area of ​​the wafer.

[0049] In this embodiment of the invention, the functional component 100 comprises a first functional chip 101, a second functional chip 102, and a retiming unit 103. The second functional chips 102 are arranged in an array around the first functional chip 101; the retiming unit 103 is disposed between the arrayed second functional chips 102; and multiple functional components 100 are arranged in an array to form a wafer-level chip integrated structure. The number of functional components 100 is related to the area of ​​the wafer. After the area of ​​the formed functional components 100 is determined, when a larger area wafer is used, the number of functional components 100 in the formed wafer-level chip integrated structure is greater; while when a smaller area wafer is used, the number of functional components 100 in the formed wafer-level chip integrated structure is less.

[0050] Based on the above-described technical solutions of the utility model embodiments, and referring to... Figure 1 and Figure 2 Each side of the first functional chip 101 shall be provided with at least four arrayed second functional chips 102; each side of the first functional chip 101 shall be provided with at least one retiming unit 103.

[0051] In this embodiment of the invention, the dimensions of the first functional chip 101, the second functional chip 102, and the retiming unit 103 are set according to a 12-nanometer process. For example, the wafer area is 40,000 square millimeters, wherein the dimensions of the first functional chip 101 are 24.0 mm * 31.0 mm, the dimensions of the second functional chip 102 are 10.7 mm * 6.4 mm, and the dimensions of the retiming unit 103 are 8.4 mm * 4.8 mm. The selection and design of the first functional chip 101, and the driving capability of the interface unit 104, do not require excessive design constraints, thereby achieving higher bandwidth.

[0052] Based on the above-described technical solutions of the utility model embodiments, and referring to... Figure 1 and Figure 2 The wafer-level chip integration structure includes at least 16 functional components 100.

[0053] For example, the size of the first functional chip 101 is set to 24.0mm*31.0mm, the size of the second functional chip 102 is 10.7mm*6.4mm, and the size of the retiming unit 103 is 8.4mm*4.8mm. Four arrays of the second functional chips 102 are arranged on each side of the first functional chip 101. A retiming unit 103 is arranged between the four arrays of the second functional chips 102 on each side of the first functional chip 101. Then, 16 functional components 100 can be integrated on a wafer with an area of ​​40,000 square millimeters. Each functional component 100 can be interconnected with adjacent functional components 100 on all four sides to form an integrated network with greater computing power.

[0054] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0055] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A wafer-level chip integration structure, characterized in that, include: Multiple functional components; the multiple functional components are arranged in an array; The functional components include a first functional chip, a second functional chip, and a retiming unit; The second functional chip array is arranged around the first functional chip; the retiming unit is disposed between the second functional chips arranged in the array; The first functional chips are connected to each other through the retiming unit; the retiming unit is used to regenerate and retime signals.

2. The wafer-level chip integration structure according to claim 1, characterized in that, The functional component further includes an interface unit; the interface unit is disposed around the first functional chip; The interface unit is used to enable communication between the first functional chips.

3. The wafer-level chip integration structure according to claim 2, characterized in that, The number of retiming units is the same as the number of interface units.

4. The wafer-level chip integration structure according to claim 1, characterized in that, The first functional chip includes a computing chip; the second functional chip includes a storage chip.

5. The wafer-level chip integration structure according to claim 4, characterized in that, The computing chip includes a central processing unit, a graphics processing unit, a data processing unit, or a digital signal processor; The memory chip includes dynamic random access memory, static random access memory, or read-only memory.

6. The wafer-level chip integration structure according to claim 4, characterized in that, The computing chip and the storage chip are interconnected by bonding.

7. The wafer-level chip integration structure according to claim 1, characterized in that, The retiming unit includes a retimer.

8. The wafer-level chip integration structure according to claim 1, characterized in that, The number of functional components is positively correlated with the area of ​​the wafer.

9. The wafer-level chip integration structure according to claim 1, characterized in that, At least four second functional chips arranged in an array are provided on each side of the first functional chip; At least one retiming unit is provided on each side of the first functional chip.

10. The wafer-level chip integration structure according to claim 1, characterized in that, The wafer-level chip integration structure includes at least 16 of the aforementioned functional components.

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