Array substrate and low-temperature polycrystalline silicon liquid crystal display panel

Abstract

The utility model discloses an array substrate and a low-temperature polycrystalline silicon liquid crystal display panel. The array substrate comprises an active layer, a grid insulating layer, a grid layer and an interlayer insulating layer, the gate insulation layer is manufactured on the active layer, the interlayer insulation layer is manufactured on the gate insulation layer, and the gate layer is manufactured on the gate insulation layer and located in the interlayer insulation layer; the active layer is of a multi-bending structure, and the gate layer forms at least three gates in a channel region corresponding to the active layer. According to the low-temperature polycrystalline silicon liquid crystal display panel, the active layer is designed into the multi-bending structure, so that the grid layer forms a plurality of grids in the corresponding channel region, the total length of the channel is increased, the current in the channel region can be adjusted more efficiently by using the multi-grid structure, the leakage current can be reduced, and the product image quality and the reliability of the low-temperature polycrystalline silicon liquid crystal display panel are improved.

Description

Technical Field

[0001] This utility model relates to the field of low-temperature polycrystalline silicon liquid crystal display panel technology, and in particular to an array substrate and a low-temperature polycrystalline silicon liquid crystal display panel. Background Technology

[0002] The LCD panel includes a color filter substrate, a thin film transistor array substrate, and a liquid crystal layer disposed between the two substrates. Its working principle is to control the rotation of liquid crystal molecules in the liquid crystal layer by applying a driving voltage on the two glass substrates, thereby refracting the light from the backlight module to produce an image.

[0003] Low Temperature Poly-silicon (LTPS) technology is a new generation of TFT substrate manufacturing technology. The biggest difference between it and traditional amorphous silicon (a-Si) technology is that LTPS-LCD has a faster response speed and advantages such as high brightness, high resolution and low power consumption.

[0004] Currently, the active layer of the array substrate of LTPS-LCD products includes a P-type substrate, an N-type channel region, and an N-type doped region. LTPS-LCD thin-film transistors are mostly dual-gate designs, with U-type or L-type active layers, and NMOS TFTs are predominant. The dual-gate design controls the on / off state of the TFT transistors. As the voltage Vds (the voltage difference between the drain and source) increases, the off-state leakage current also increases sharply, seriously affecting the image quality and reliability of the product. Utility Model Content

[0005] The thin-film transistors in existing low-temperature polycrystalline silicon liquid crystal panels adopt a dual-gate design, and their active layer adopts a U-shaped or L-shaped design. As the voltage difference between the drain and source increases, the off-state leakage current also increases sharply, which seriously affects the image quality and reliability of the product.

[0006] To address the aforementioned issues, an array substrate and a low-temperature polycrystalline silicon liquid crystal display panel are proposed. By designing the active layer as a multi-bend structure, multiple gates are formed in the gate layer at the corresponding channel regions, thereby increasing the total channel length. The multi-gate structure allows for more efficient regulation of the channel current and reduces leakage current, thus improving the image quality and reliability of the low-temperature polycrystalline silicon liquid crystal display panel.

[0007] In a first aspect, an array substrate includes:

[0008] Active layer;

[0009] Gate insulating layer;

[0010] Gate layer;

[0011] Interlayer insulation layer;

[0012] The gate insulating layer is formed on the active layer, the interlayer insulating layer is formed on the gate insulating layer, and the gate layer is formed on the gate insulating layer and located in the interlayer insulating layer;

[0013] The active layer has a multi-bend structure, and the gate layer forms at least three gates in the channel region corresponding to the active layer.

[0014] In conjunction with the array substrate described in the first aspect of this utility model, in a first possible embodiment, the active layer is an S-shaped bending structure, and the gate layer and the channel region corresponding to the S-shaped bending structure form three gates.

[0015] In conjunction with the first possible embodiment of the first aspect of this utility model, in the second possible embodiment, the active layer adopts a P-type substrate;

[0016] The P-type substrate is subjected to four N-type doping processes to form four N-type doped regions, and three N-type channel regions are formed between the four N-type doped regions.

[0017] In conjunction with the second possible embodiment of the first aspect of this utility model, in the third possible embodiment, the array substrate further includes:

[0018] SD layer;

[0019] The SD layer is fabricated on the interlayer insulating layer and is connected to the outermost N-type doped region through vias to form the source and drain, respectively.

[0020] In conjunction with the third possible embodiment of the first aspect of this utility model, in the fourth possible embodiment, the array substrate further includes:

[0021] Buffer layer;

[0022] Light-shielding layer;

[0023] Glass substrate;

[0024] The light-shielding layer is formed on the glass substrate, the buffer layer is formed on the light-shielding layer, and the active layer is formed on the buffer layer.

[0025] In a second aspect, a low-temperature polycrystalline silicon liquid crystal display panel includes the array substrate described in the first aspect.

[0026] The array substrate and low-temperature polycrystalline silicon liquid crystal display panel described in this utility model are designed with an active layer in a multi-bend structure, so that multiple gates are formed in the gate layer at the corresponding channel region position, thereby increasing the total length of the channel. The multi-gate structure can more efficiently regulate the channel region current, reduce leakage current, thereby improving the product image quality and reliability of the low-temperature polycrystalline silicon liquid crystal display panel. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic planar diagram of a specific embodiment of the active layer and gate layer in the prior art;

[0029] Figure 2 This is a schematic diagram of the film structure of a specific embodiment of the active layer and gate layer in the prior art;

[0030] Figure 3 This is a schematic plan view of a specific embodiment of the active layer and gate layer in this application;

[0031] Figure 4 This is a schematic diagram of the film structure of a specific embodiment of the active layer and gate layer in this application;

[0032] The numbers in the attached diagram represent the following parts: 100 – glass substrate, 200 – light-shielding layer, 300 – buffer layer, 400 – active layer, 500 – gate insulating layer, 600 – interlayer insulating layer, 710 – source, 720 – drain, 800 – gate layer. Detailed Implementation

[0033] The technical solutions of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, other embodiments obtained by those skilled in the art without creative effort are all within the scope of protection of this utility model.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0035] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0036] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0038] Existing low-temperature polycrystalline silicon (LTPS) LCD panels use a dual-gate design for their thin-film transistors, with the active layer 400 employing a U-shaped or L-shaped design. As the voltage difference between the drain 720 and source 710 increases, the off-state leakage current also increases sharply, severely impacting image quality and reliability. Figure 1 and Figure 2 , Figure 1 This is a schematic plan view of a specific embodiment of the active layer 400 and the gate layer 800 in the prior art. Figure 2 This is a schematic diagram of the film structure of a specific embodiment of the active layer 400 and the gate layer 800 in the prior art. In N-type TFT, the physical mechanism of leakage current generation is: thermal carrier effect and tunneling under the action of Vds electric field. Especially in high temperature environment, carrier divergence is more active and leakage current is larger.

[0039] To address the above problems, an array substrate and a low-temperature polycrystalline silicon liquid crystal display panel are proposed.

[0040] In a first aspect, an array substrate includes an active layer 400, a gate insulating layer 500, a gate layer 800, and an interlayer insulating layer 600. The gate insulating layer 500 is fabricated on the active layer 400, the interlayer insulating layer 600 is fabricated on the gate layer 800, and the gate layer 800 is fabricated on the gate insulating layer 500 and located within the interlayer insulating layer 600. The active layer 400 has a multi-bend structure, and the gate layer 800 forms at least three gates in the corresponding channel region of the active layer 400. By designing the active layer 400 as a multi-bend structure, the gate layer 800 forms multiple gates in the corresponding channel region, thereby increasing the total channel length. The multi-gate structure allows for more efficient regulation of the channel current, reducing leakage current, thereby improving the image quality and reliability of the low-temperature polysilicon liquid crystal display panel.

[0041] In a preferred embodiment, such as Figure 3 , Figure 3 This is a schematic plan view of a specific embodiment of the active layer 400 and the gate layer 800 in this application; the active layer 400 has an S-shaped bending structure, and the gate layer 800 and the channel region corresponding to the S-shaped bending structure form three gates.

[0042] Furthermore, the active layer 400 adopts a P-type substrate 100; the P-type substrate 100 is subjected to four N-type doping to form four N-type doped regions, and three N-type channel regions are formed between the four N-type doped regions.

[0043] In some implementations, a bending structure can be further added, such as... Figure 4 , Figure 4 This is a schematic diagram of the film structure of a specific embodiment of the active layer 400 and the gate layer 800 in this application. Figure 4 In this structure, there are more bends than in the S-shaped bend structure. It has 5 doped regions and 4 channel regions, which can divide the gate layer 800 into 4 gates.

[0044] Increasing the number of gates shortens the N-type doped region and further lengthens the channel, making it more difficult for leakage current to be generated between the source and drain 720, thus minimizing the leakage current between the source and drain 720.

[0045] Furthermore, the array substrate also includes an SD layer (not shown in the figure); the SD layer (not shown in the figure) is fabricated on the interlayer insulating layer 600 and is connected to the outermost N-type doped region through vias to form the source 710 and drain 720, respectively.

[0046] Furthermore, the array substrate also includes a buffer layer 300, a light-shielding layer 200, and a glass substrate 100; the light-shielding layer 200 is formed on the glass substrate 100, the buffer layer 300 is formed on the light-shielding layer 200, and the active layer 400 is formed on the buffer layer 300.

[0047] In a second aspect, a low-temperature polycrystalline silicon liquid crystal display panel includes an array substrate as described in the first aspect.

[0048] The present invention relates to an array substrate and a low-temperature polycrystalline silicon liquid crystal display panel. By designing the active layer 400 into a multi-bend structure, multiple gates are formed in the gate layer 800 at the corresponding channel region positions, thereby increasing the total channel length. The multi-gate structure can more efficiently regulate the channel region current, reduce leakage current, thereby improving the product image quality and reliability of the low-temperature polycrystalline silicon liquid crystal display panel.

[0049] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. An array substrate, characterized in that, include: Active layer; Gate insulating layer; Gate layer; Interlayer insulation layer; The gate insulating layer is formed on the active layer, the interlayer insulating layer is formed on the gate insulating layer, and the gate layer is formed on the gate insulating layer and located in the interlayer insulating layer; The active layer has a multi-bend structure, and the gate layer forms at least three gates in the channel region corresponding to the active layer.

2. The array substrate according to claim 1, characterized in that, The active layer has an S-shaped bend structure, and the gate layer and the channel region corresponding to the S-shaped bend structure form three gates.

3. The array substrate according to claim 2, characterized in that, The active layer uses a P-type substrate; The P-type substrate is subjected to four N-type doping processes to form four N-type doped regions, and three N-type channel regions are formed between the four N-type doped regions.

4. The array substrate according to claim 3, characterized in that, The array substrate further includes: SD layer; The SD layer is fabricated on the interlayer insulating layer and is connected to the outermost N-type doped region through vias to form the source and drain, respectively.

5. The array substrate according to claim 4, characterized in that, The array substrate further includes: Buffer layer; Light-shielding layer; Glass substrate; The light-shielding layer is formed on the glass substrate, the buffer layer is formed on the light-shielding layer, and the active layer is formed on the buffer layer.

6. A low-temperature polycrystalline silicon liquid crystal display panel, characterized in that, Includes the array substrate as described in any one of claims 1-5.

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