Novel array substrate and low-temperature polycrystalline silicon display device
By setting two rows of holes in the organic insulating layer near the edge of the source and drain metal layers, the problem of film bulging or cracking in low-temperature polycrystalline silicon thin-film transistors during high-temperature processes is solved, enabling effective escape of water vapor and ensuring the stability of the film layer.
Patent Information
- Application Number
- CN202520118227.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-18
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-01-18
AI Technical Summary
The film layer of low-temperature polycrystalline silicon thin-film transistors is prone to bulging or cracking during high-temperature processes, mainly due to the water absorption of the organic insulating film, which prevents moisture from being effectively discharged after it escapes.
Two rows of holes are made in the organic insulating layer, close to the edge of the source and drain metal layers and kept at a distance less than specified, to provide a path for water vapor to escape and prevent water vapor from continuing to escape after high temperature.
This effectively prevents bulging or rupture of the membrane layer, ensuring its stability and integrity.
Smart Images
Figure CN223844151U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of low-temperature polycrystalline silicon liquid crystal display panel technology, and in particular to a novel array substrate and a low-temperature polycrystalline silicon display device. Background Technology
[0002] Low Temperature Poly-silicon (LTPS) technology is a new generation of TFT substrate manufacturing technology. The biggest difference between it and traditional amorphous silicon (a-Si) technology is that LTPS-LCD has a faster response speed and advantages such as high brightness, high resolution and low power consumption.
[0003] To improve insulation and increase load capacity, low-temperature polycrystalline silicon thin-film transistors (LTSPs) often use organic insulating films (PLNs) as the dielectric for insulation protection. After the PLN is formed, two transparent conductive films (ITO) and one capacitor insulating layer are typically designed. The ITO has a certain water absorption capacity and is not water-resistant, while the capacitor insulating layer is generally made of silicon nitride, which has strong water-resistant properties. However, the PLN itself is prone to water absorption. After high temperatures, moisture escapes from the PLN, causing the subsequent layers to bulge or crack. Utility Model Content
[0004] The existing structural design of low-temperature polycrystalline silicon thin-film transistors has the problem that the film layer is easily pushed up, bulges, or cracks.
[0005] To address the aforementioned issues, a novel array substrate and low-temperature polysilicon display device are proposed. By creating two rows of holes during the perforation of the organic insulating layer, and ensuring that these two rows of holes are formed close to the edges of the source and drain metal layers with a distance less than a specified value, it is beneficial for the escape of moisture from the organic insulating layer. This prevents moisture from escaping from the organic insulating film after high temperatures, thus avoiding bulging or cracking of the film layer subsequently fabricated on the organic insulating film.
[0006] In a first aspect, a novel array substrate for fabricating low-temperature polycrystalline silicon display devices includes:
[0007] Source and drain metal layers;
[0008] Organic insulating layer;
[0009] Transparent conductive layer;
[0010] capacitor insulation layer;
[0011] Multiple holes;
[0012] The organic insulating layer is formed on the source and drain metal layers;
[0013] The plurality of holes are arranged in a row on the organic insulating layer and are close to the edge of the source and drain metal layer;
[0014] The transparent conductive layer is formed on the organic insulating layer, and the capacitor insulating layer is formed on the transparent conductive layer.
[0015] In conjunction with the novel array substrate described in the first aspect of this utility model, in a first possible embodiment, the number of rows of holes is two, and each row of holes is formed near the edge of the source and drain metal layer.
[0016] In conjunction with the first possible implementation of the first aspect of this utility model, in the second possible implementation, the distance between each row of holes and the edge of the source / drain metal layer is equal, and the distance is less than a predetermined value.
[0017] In conjunction with the second possible embodiment of the first aspect of this utility model, in the third possible embodiment, the array substrate further includes:
[0018] Pixel electrode layer;
[0019] The pixel electrode layer is formed on the capacitor insulating layer.
[0020] In conjunction with the third possible embodiment of the first aspect of this utility model, in the fourth possible embodiment, the array substrate further includes:
[0021] Isolation layer;
[0022] Gate layer;
[0023] Interlayer insulation layer;
[0024] The source and drain metal layers are formed on the isolation layer;
[0025] The insulating layer is formed on the interlayer insulating layer;
[0026] The gate layer is fabricated within the interlayer insulating layer.
[0027] In conjunction with the fourth possible embodiment of the first aspect of this utility model, in the fifth possible embodiment, the array substrate further includes:
[0028] Buffer layer, light-shielding layer and glass substrate;
[0029] The interlayer insulating layer is formed on the buffer layer, the buffer layer is formed on the light-shielding layer, and the light-shielding layer is formed on the glass substrate.
[0030] In a second aspect, a low-temperature polycrystalline silicon display device includes the novel array substrate described in the first aspect.
[0031] The present invention provides a novel array substrate and a low-temperature polycrystalline silicon display device. By setting two rows of holes when drilling holes in the organic insulating layer, and making these two rows of holes close to the edge of the source and drain metal layers and keeping the distance between them less than a specified value, it is beneficial for the escape of water vapor in the organic insulating layer. This avoids water vapor escaping from the organic insulating film after high temperature, which could cause the film layer subsequently made on the organic insulating film to bulge or crack. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 This is a schematic plan view of a specific embodiment of the perforation of an organic insulating layer in the prior art;
[0034] Figure 2 This is a planar view of the bulge of the film layer on an array substrate in the prior art;
[0035] Figure 3 This is a cross-sectional view of the bulge of the film layer on an array substrate in the prior art;
[0036] Figure 4 This is a schematic plan view of a specific embodiment of the perforation in the organic insulating layer of this application;
[0037] Figure 5 This is a schematic diagram of the film layer structure of a specific embodiment of the novel array substrate in this application. Detailed Implementation
[0038] The technical solutions of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, other embodiments obtained by those skilled in the art without creative effort are all within the scope of protection of this utility model.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0040] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0041] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0043] Existing low-temperature polycrystalline silicon thin-film transistor designs suffer from the problem of the film layer easily being pushed up, bulging, or cracking, such as... Figure 1 , Figure 2 and Figure 3 , Figure 1 This is a schematic plan view of a specific embodiment of the perforation of an organic insulating layer (PLN) in the prior art. Figure 2 This is a planar view of the bulge of the film layer on an array substrate in the prior art. Figure 3 This is a cross-sectional view of the bulge of the film layer of the array substrate in the prior art; the existing design of the hole is generally designed in multiple rows, and the hole is far away from the edge of the source and drain metal layer (SD). Since there is no effective water vapor escape path, after the temperature is high, the water vapor escapes from the organic insulating film, pushing up the film layer made after the organic insulating film to bulge or crack.
[0044] To address the above problems, a novel array substrate and a low-temperature polysilicon display device are proposed.
[0045] Firstly, such as Figure 4 , Figure 4This is a schematic plan view of a specific embodiment of the perforation in the organic insulating layer (PLN) of this application; a novel array substrate for fabricating a low-temperature polycrystalline silicon display device includes a source / drain metal layer (SD), an organic insulating layer (PLN), a transparent conductive layer (ITO), a capacitor insulating layer, and multiple perforations; the organic insulating layer (PLN) is formed on the source / drain metal layer (SD); multiple perforations are arranged in rows on the organic insulating layer (PLN) and close to the edge of the source / drain metal layer (SD); the transparent conductive layer (ITO) is formed on the organic insulating layer (PLN), and the capacitor insulating layer is formed on the transparent conductive layer (ITO). By setting two rows of perforations when perforating the organic insulating layer (PLN), and making these two rows of perforations close to the edge of the source / drain metal layer (SD) and keeping the distance between them less than a specified value, it is beneficial for the escape of moisture in the organic insulating layer (PLN), thereby preventing moisture from escaping from the organic insulating film after high temperature, which could cause the film layer subsequently fabricated to bulge or crack.
[0046] In this embodiment, the perforations are arranged in two rows, with each row of perforations formed near the edge of the source-drain metal layer (SD). Considering the strong water absorption capacity of the organic insulating layer (PLN) and the transparent conductive layer (ITO), a high-temperature baking process is performed after the organic insulating layer (PLN) is formed to remove the water absorbed by the PLN. Similarly, a high-temperature baking process is performed after the transparent conductive layer (ITO) is formed to remove the water absorbed by both the organic insulating layer (PLN) and the transparent conductive layer.
[0047] In this embodiment, rows of holes are formed near the edge of the source-drain metal layer (SD) to provide an effective escape path for water vapor.
[0048] Furthermore, the distance between each row of perforations and the edge of the source-drain metal layer (SD) is equal and less than a specified value. In one specific embodiment, the specified value can be 2 μm. This smaller-than-specified value significantly reduces the distance water vapor needs to escape, which is beneficial for the rapid escape of water vapor.
[0049] Furthermore, such as Figure 5 , Figure 5 This is a schematic diagram of the film structure of a specific embodiment of the novel array substrate in this application. The array substrate also includes a pixel electrode layer; the pixel electrode layer is formed on a capacitor insulating layer.
[0050] Furthermore, the array substrate also includes an isolation layer, a gate layer, and an interlayer insulating layer; the source-drain metal layer (SD) is formed on the isolation layer; the isolation layer is formed on the interlayer insulating layer; and the gate layer is fabricated in the interlayer insulating layer.
[0051] Furthermore, the array substrate also includes a buffer layer, a light-shielding layer, and a glass substrate; the interlayer insulating layer is formed on the buffer layer, the buffer layer is formed on the light-shielding layer, and the light-shielding layer is formed on the glass substrate.
[0052] In a second aspect, a low-temperature polycrystalline silicon display device includes a novel array substrate as described in the first aspect.
[0053] The present invention discloses a novel array substrate and a low-temperature polysilicon display device. By setting two rows of holes when drilling holes in the organic insulating layer (PLN), and making the two rows of holes close to the edge of the source and drain metal layer (SD) and the distance between them is less than a specified value, it is beneficial for the escape of moisture in the organic insulating layer (PLN). This avoids moisture escaping from the organic insulating film after high temperature, which could cause the film layer made after the organic insulating film to bulge or crack.
[0054] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.
Claims
1. A novel array substrate for fabricating low-temperature polycrystalline silicon display devices, characterized in that, include: Source and drain metal layers; Organic insulating layer; Transparent conductive layer; capacitor insulation layer; Multiple holes; The organic insulating layer is formed on the source and drain metal layers; The plurality of holes are arranged in a row on the organic insulating layer and are close to the edge of the source and drain metal layer; The transparent conductive layer is formed on the organic insulating layer, and the capacitor insulating layer is formed on the transparent conductive layer.
2. The novel array substrate according to claim 1, characterized in that, The number of holes is two rows, and each row of holes is made near the edge of the source and drain metal layer.
3. The novel array substrate according to claim 2, characterized in that, The distance between each row of holes and the edge of the source / drain metal layer is equal, and the distance is less than a specified value.
4. The novel array substrate according to claim 3, characterized in that, The array substrate further includes: Pixel electrode layer; The pixel electrode layer is formed on the capacitor insulating layer.
5. The novel array substrate according to claim 4, characterized in that, The array substrate further includes: Isolation layer; Gate layer; Interlayer insulation layer; The source and drain metal layers are formed on the isolation layer; The insulating layer is formed on the interlayer insulating layer; The gate layer is fabricated within the interlayer insulating layer.
6. The novel array substrate according to claim 5, characterized in that, The array substrate further includes: Buffer layer, light-shielding layer and glass substrate; The interlayer insulating layer is formed on the buffer layer, the buffer layer is formed on the light-shielding layer, and the light-shielding layer is formed on the glass substrate.
7. A low-temperature polycrystalline silicon display device, characterized in that, Includes the novel array substrate as described in any one of claims 1-6.