Arrangement positioning device for chip packaging
By designing an arrangement and positioning device for chip packaging, the problem of arrangement and positioning in the chip packaging process was solved, enabling rapid arrangement and positioning of chips and improving processing and testing efficiency.
Patent Information
- Application Number
- CN202520309888.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-02-25
AI Technical Summary
In the current chip packaging process, it is difficult to achieve efficient arrangement and positioning, which affects the efficiency of subsequent processing and testing.
A chip packaging alignment and positioning device is designed, including a chip positioning carrier, a chip alignment board and a chip top pressure plate. The device utilizes structures such as alignment slots, protrusions and compression springs to achieve rapid chip alignment and positioning.
It enables rapid arrangement and positioning of chip packages, improving the efficiency of subsequent processing and testing.
Smart Images
Figure CN223844259U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of chip processing technology, and specifically relates to an arrangement and positioning device for chip packaging. Background Technology
[0002] Chip packaging is the process of assembling integrated circuits into a final chip product, which is generally called a chip package. After forming, existing chip packages often undergo multiple testing stages. In automated chip testing, chips are often arranged and positioned.
[0003] Therefore, it is necessary to design a device that facilitates the arrangement and positioning of chip packages. Utility Model Content
[0004] To address the aforementioned problems in the existing technology, this solution provides an arrangement and positioning device for chip packaging.
[0005] The technical solution adopted in this utility model is as follows:
[0006] A chip packaging alignment and positioning device includes a chip positioning carrier, a chip alignment plate, and a chip top plate.
[0007] A plurality of arrangement slots are provided on the upper surface of the chip arrangement board, and the arrangement slots are arranged in an array; the depth of the arrangement slots is less than the height of the chip package, so that when the chip package is placed in the arrangement slot in reverse, the pins of the chip package extend above the upper surface of the chip arrangement board; a bottom ejection hole is provided at the bottom of each arrangement slot, and the bottom ejection hole penetrates the lower surface of the chip arrangement board.
[0008] The lower surface of the chip positioning carrier is provided with a chip connection layer, and the chip positioning carrier can cover the chip arrangement board so that the pins of the chip package are connected to the chip connection layer.
[0009] The chip top plate is located below the chip arrangement plate. Several protrusions are provided on the upper surface of the chip top plate. The position and number of the protrusions correspond one-to-one with the lower ejection holes. The protrusions can eject the chip package from the arrangement slot and press it onto the chip interconnect layer.
[0010] As an alternative or supplement to the above solution: the upper surface of the chip top plate is provided with several compression springs; after the chip positioning carrier, chip arrangement plate and chip top plate are overlapped, when there is no external pressure, the compression springs abut against the lower surface of the chip arrangement plate, and the upper end of the protrusion is placed in the lower ejection hole without extending into the arrangement groove.
[0011] As an alternative or supplement to the above solution: the length of the protrusion is greater than the length of the compression spring, so that when the external force presses down on the chip arrangement plate, the upper end of the protrusion extends into the arrangement groove and presses down on the chip package.
[0012] As an alternative or supplement to the above solution: when the chip package has through-hole pins, the chip connection layer is a foam layer.
[0013] As an alternative or supplement to the above solution: when the chip package pins are surface mount pins, the chip connection layer is a double-sided adhesive layer.
[0014] As an alternative or supplement to the above scheme: the lower ejector hole is a tapered hole structure with a smaller upper part and a larger lower part.
[0015] As an alternative or supplement to the above solution: the edge of the chip positioning carrier is provided with a first alignment hole, and the edge of the chip arrangement plate is provided with a first alignment pin. The first alignment pin can be inserted into the corresponding first alignment hole to achieve alignment between the chip positioning carrier and the chip arrangement plate.
[0016] As an alternative or supplement to the above solution: the edge of the chip array plate is provided with a second alignment hole, and the edge of the chip top plate is provided with a second alignment pin. The second alignment pin can be inserted into the corresponding second alignment hole to achieve alignment between the chip top plate and the chip array plate; the positions of the second alignment pin and the first alignment pin are staggered.
[0017] The beneficial effects of this utility model are as follows: In this solution, the arrangement slots on the chip arrangement board make it easy for operators to quickly arrange scattered chip packages, and then the chip package is connected and positioned by the chip positioning carrier, which facilitates the picking and testing of chip packages in subsequent processing steps. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this scheme or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.
[0019] Figure 1 This is a schematic diagram of the chip packaging arrangement and positioning device in this solution;
[0020] Figure 2 This is a partial structural diagram of the cross-section of the positioning device in this scheme.
[0021] In the figure: 1-Chip positioning carrier; 11-First alignment hole; 12-Upper ejection hole; 2-Chip connection layer; 3-Chip alignment board; 31-Alignment slot; 32-Lower ejection hole; 33-Second alignment hole; 4-First alignment pin; 5-Chip top pressure plate; 51-Protrusion; 52-Compression spring; 6-Second alignment pin; 7-Chip package. Detailed Implementation
[0022] The technical solutions in this embodiment will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in this solution without creative effort are within the protection scope of this solution.
[0023] like Figures 1 to 2 As shown, this embodiment designs an arrangement and positioning device for chip packaging 7, including components such as chip positioning carrier 1, chip arrangement board 3 and chip top pressure plate 5.
[0024] A plurality of arrangement slots 31 are provided on the upper surface of the chip arrangement plate 3, and the arrangement slots 31 are arranged in an array. The depth of the arrangement slots 31 is less than the height of the chip package 7, so that when the chip package 7 is placed in the arrangement slots 31 in reverse, the pins of the chip package 7 extend above the upper surface of the chip arrangement plate 3. A bottom ejection hole 32 is provided at the bottom of each arrangement slot 31, and the bottom ejection hole 32 penetrates the lower surface of the chip arrangement plate 3.
[0025] The lower surface of the chip positioning carrier 1 is provided with a chip connection layer 2. The chip positioning carrier 1 can cover the chip arrangement board 3 so that the pins of the chip package 7 can be connected to the chip connection layer 2. When the pins of the chip package 7 are through-hole pins, the chip connection layer 2 is a foam layer, which facilitates the insertion connection between the pins of the chip package 7 and the foam layer. When the pins of the chip package 7 are surface mount pins, the chip connection layer 2 is a double-sided adhesive layer, which facilitates the bonding connection between the pins of the chip package 7 and the double-sided adhesive layer. In addition, the chip connection layer 2 can be peeled off from the chip positioning carrier 1 and replaced with a new chip connection layer 2. The replacement frequency depends on the actual needs.
[0026] The chip top plate 5 is positioned below the chip arrangement plate 3. A plurality of protrusions 51 are provided on the upper surface of the chip top plate 5, with each protrusion 51 corresponding to a lower ejection hole 32 in position and number. The protrusions 51 can eject the chip package 7 from the arrangement slot 31 and press it firmly onto the chip bonding layer 2. A plurality of compression springs 52 are provided on the upper surface of the chip top plate 5. When the chip positioning carrier plate 1, the chip arrangement plate 3, and the chip top plate 5 are overlapped, without external pressure, the compression springs 52 press against the lower surface of the chip arrangement plate 3, and the upper ends of the protrusions 51 are placed in the lower ejection holes 32 without extending into the arrangement slot 31. The lower ejection holes 32 are tapered structures, smaller at the top and larger at the bottom, facilitating the insertion of the protrusions 51 into the lower ejection holes 32.
[0027] The length of the protrusion 51 is greater than the length of the compression spring 52, so that when the external force presses down on the chip arrangement plate 3, the upper end of the protrusion 51 extends into the arrangement groove 31 and presses against the chip package 7.
[0028] The chip positioning carrier 1 has multiple first alignment holes 11 along its edge, and the chip arrangement plate 3 has multiple first alignment pins 4 along its edge. The first alignment pins 4 can be inserted into the corresponding first alignment holes 11 to align the chip positioning carrier 1 and the chip arrangement plate 3. The chip arrangement plate 3 has multiple second alignment holes 33 along its edge, and the chip pressure plate 5 has multiple second alignment pins 6 along its edge. The second alignment pins 6 can be inserted into the corresponding second alignment holes 33 to align the chip pressure plate 5 and the chip arrangement plate 3. The positions of the second alignment pins 6 and the first alignment pins 4 are staggered.
[0029] When using the chip packaging 7 alignment and positioning device in this solution:
[0030] First, the chip arrangement board 3 is manually placed into the raw material frame containing the chip package 7. The chip package 7 is evenly spread on the chip arrangement board 3 and the chip arrangement board 3 is manually shaken so that the chip package 7 falls into the arrangement slot 31. Then, the chip package 7 on the chip arrangement board 3 is manually inspected to ensure that each arrangement slot 31 has a chip package 7 and that the pins of the chip package 7 are facing upwards.
[0031] Next, the chip alignment plate 3 is placed on the chip top plate 5, so that the second alignment pin 6 is inserted into the second alignment hole 33, and each protrusion 51 is inserted into the corresponding lower ejection hole 32. Then, the chip positioning carrier plate 1 is placed on top of the chip alignment plate 3, so that the first alignment pin 4 is inserted into the first alignment hole 11. A downward pressure is applied to the chip alignment plate 3 and the chip positioning carrier plate 1, so that the protrusions 51 extend into the alignment groove 31 and press the chip package 7 tightly onto the chip positioning carrier plate 1, thereby connecting the pins of the chip package 7 to the chip connection layer 2.
[0032] Afterwards, remove the chip positioning carrier 1 and rotate it 180° so that the lower surface of the chip positioning carrier 1 faces upward. At this time, the chip packages 7 are evenly arranged in a rectangular array on the chip positioning carrier 1. After placing the chip positioning carrier 1 into the equipment of the testing stage, it is convenient to position the chip packages 7.
[0033] In addition, several upper ejection holes 12 are provided on the surface of the chip positioning carrier 1, and corresponding through holes are also provided on the chip connection layer 2. When the chip positioning carrier 1 is rotated 180 degrees and covered on the chip pressure plate 5, the second alignment pin 6 is inserted into the corresponding first alignment hole 11 and the protrusion 51 is inserted into the upper ejection hole 12. At this time, the chip connection layer 2 is in the upward position. The mold for accommodating the chip package 7 is placed on the chip connection layer 2. The chip positioning carrier 1 and the mold can be pressed to lift the chip package 7 using the protrusion 51 so that the chip package 7 can be installed into the mold.
[0034] The above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation; it is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom remain within the scope of this technology.
Claims
1. A chip packaging alignment and positioning device, characterized in that: It includes a chip positioning carrier (1), a chip arrangement board (3), and a chip top plate (5); A plurality of arrangement slots (31) are provided on the upper surface of the chip arrangement plate (3), and the arrangement slots (31) are arranged in an array; the depth of the arrangement slots (31) is less than the height of the chip package (7), so that when the chip package (7) is placed in the arrangement slots (31) in reverse, the pins of the chip package (7) extend above the upper surface of the chip arrangement plate (3); a bottom ejection hole (32) is provided at the bottom of each arrangement slot (31), and the bottom ejection hole (32) penetrates the lower surface of the chip arrangement plate (3); The lower surface of the chip positioning carrier (1) is provided with a chip connection layer (2), and the chip positioning carrier (1) can cover the chip arrangement board (3) so that the pins of the chip package (7) are connected to the chip connection layer (2). The chip top plate (5) is located below the chip arrangement plate (3). Several protrusions (51) are provided on the upper surface of the chip top plate (5). The position and number of the protrusions (51) correspond one-to-one with the lower ejection holes (32). The protrusions (51) can push the chip package (7) out of the arrangement slot (31) and press it onto the chip connection layer (2), thereby positioning the chip package onto the chip positioning carrier plate (1).
2. The chip packaging arrangement and positioning device according to claim 1, characterized in that: The upper surface of the chip top plate (5) is provided with several compression springs (52); after the chip positioning carrier (1), the chip arrangement plate (3) and the chip top plate (5) are overlapped, when there is no external pressure, the compression springs (52) abut against the lower surface of the chip arrangement plate (3), and the upper end of the protrusion (51) is placed in the lower ejection hole (32) without extending into the arrangement groove (31).
3. The chip packaging arrangement and positioning device according to claim 2, characterized in that: The length of the protrusion (51) is greater than the length of the compression spring (52), so that when the external force presses down on the chip arrangement plate (3), the upper end of the protrusion (51) extends into the arrangement groove (31) and presses down on the chip package (7).
4. The chip packaging arrangement and positioning device according to claim 1, characterized in that: When the pins of the chip package (7) are through-hole pins, the chip connection layer (2) is a foam layer.
5. The chip packaging arrangement and positioning device according to claim 1, characterized in that: When the pins of the chip package (7) are surface mount pins, the chip connection layer (2) is a double-sided adhesive layer.
6. The chip packaging arrangement and positioning device according to claim 1, characterized in that: The lower ejector hole (32) is a tapered hole structure with a smaller upper part and a larger lower part.
7. The chip packaging arrangement and positioning device according to any one of claims 1-6, characterized in that: The chip positioning carrier (1) has a first alignment hole (11) on its edge, and the chip arrangement plate (3) has a first alignment pin (4) on its edge. The first alignment pin (4) can be inserted into the corresponding first alignment hole (11) to achieve alignment between the chip positioning carrier (1) and the chip arrangement plate (3).
8. The chip packaging arrangement and positioning device according to claim 7, characterized in that: The edge of the chip arrangement plate (3) is provided with a second alignment hole (33), and the edge of the chip top plate (5) is provided with a second alignment pin (6). The second alignment pin (6) can be inserted into the corresponding second alignment hole (33) to achieve alignment between the chip top plate (5) and the chip arrangement plate (3). The second alignment pin (6) is offset from the first alignment pin (4).