Amplitude self-adaptive characteristic current generating system

Abstract

The utility model discloses an amplitude self-adaptive characteristic current generating system, which comprises a rectifying unit, a power MOS (Metal Oxide Semiconductor) tube and current limiting unit, an MOS tube driving unit, a first signal conditioning and isolating unit, a second signal conditioning and isolating unit and a processor unit, the processor unit is electrically connected with the first signal conditioning and isolating unit and the second signal conditioning and isolating unit through wires, the first signal conditioning and isolating unit is electrically connected with the MOS tube driving unit through wires, and the MOS tube driving unit and the second signal conditioning and isolating unit are electrically connected with the power MOS tube and current limiting unit through wires. The power MOS tube and the current limiting unit are electrically connected with the rectification unit through wires, the rectification unit is electrically connected with the MOS tube driving unit, and the rectification unit is electrically connected with the AC line interface. The utility model solves the technical problem that the identification success rate and the power consumption and the service life of a sending system product cannot be considered at the same time because the existing characteristic current generating system is configured with a single characteristic current with a fixed amplitude.

Description

Technical Field

[0001] This utility model relates to the field of power distribution network topology identification technology, and in particular to a characteristic current generation system with adaptive amplitude. Background Technology

[0002] Topology identification technology is a necessary technological foundation for advancing the construction of digital distribution networks. Topology identification technologies include big data methods and signal injection methods. Big data methods have high requirements for the power grid, requiring each user's load to be adequate and the line topology to be relatively simple. Furthermore, the identification results require multiple iterations, often taking days or even weeks to produce a correct result. Signal injection methods have lower requirements for the power grid, faster identification speed, and higher accuracy. However, the power frequency distortion method within signal injection, which controls the switching of loads on the power frequency line to generate a characteristic current of tens of amperes, has a significant impact on the power grid and is rarely used now. Currently, injecting a small characteristic current with a square wave envelope is commonly used. Given that the larger the transmitted current, the higher the power consumption and temperature rise of the transmitting module, existing characteristic current generation systems inject currents of fixed amplitude, which is the minimum value in the industry standard. With the increasing application of distributed power sources and the increasing amplitude of current noise generated by electrical equipment, the success rate of topology identification using a single-amplitude characteristic current transmission mode is showing a downward trend, while the false alarm rate is showing an upward trend. The fixed-amplitude characteristic current transmission mode has the drawback of a narrow range of applicability. If the characteristic current is fixed at a small amplitude, the recognition success rate will decrease under conditions of severe co-channel interference or distributed power supply operation. If the characteristic current is fixed at a large amplitude, the recognition success rate can be improved, but there will be problems with high power consumption, resulting in high heat generation and shortening product lifespan. In existing topology identification systems, the identification device is bound to a communication unit, and the transmitting device is bound to a communication unit. The identification process is that the communication unit of the identification device notifies the communication unit of the transmitting device, instructing the transmitting device to send a characteristic current. The identification device determines whether the transmitting device is in the same area or branch as the identification device based on whether it receives the characteristic current. If the identification device does not identify the characteristic current after notifying the transmitting device to send it, it will initiate a second notification. If the second notification is successful, it is determined that the transmitting device is in the same area or branch as the identification device; otherwise, it is determined that the transmitting device is not in the same area or branch as the identification device. The interval between the two notifications is between a few minutes and three or four hours. Therefore, there is an urgent need to propose an amplitude-adaptive characteristic current generation system to solve the technical problem that existing characteristic current generation systems are configured with a single fixed amplitude characteristic current, which leads to a trade-off between recognition success rate and power consumption and lifespan of the transmission system products. Utility Model Content

[0003] The main purpose of this invention is to propose an amplitude-adaptive characteristic current generation system, which aims to solve the technical problem that existing characteristic current generation systems are configured with a single fixed amplitude characteristic current, resulting in a tradeoff between recognition success rate and power consumption and lifespan of the transmission system.

[0004] To achieve the above objectives, this utility model provides an amplitude-adaptive characteristic current generating system, wherein the amplitude-adaptive characteristic current generating system includes:

[0005] The unit includes a rectifier unit, a power MOSFET and current limiting unit, a MOSFET driving unit, a first signal conditioning and isolation unit, a second signal conditioning and isolation unit, and a processor unit.

[0006] The processor unit is electrically connected to the first signal conditioning and isolation unit and the second signal conditioning and isolation unit via wires. The first signal conditioning and isolation unit is electrically connected to the MOS transistor driving unit via wires. The MOS transistor driving unit and the second signal conditioning and isolation unit are electrically connected to the power MOS transistor and the current limiting unit via wires. The power MOS transistor and the current limiting unit are electrically connected to the rectification unit via wires. The rectification unit is electrically connected to the MOS transistor driving unit and to the AC line interface.

[0007] In one preferred embodiment, the second signal conditioning and isolation unit includes a relay U1, a transistor V3, and a resistor R8;

[0008] The base of transistor V3 is connected to the processor unit; the collector of transistor V3 is connected to pin 2 of relay U1; pin 1 of relay U1 is connected to resistor R8; the other end of resistor R8 is connected to a DC power supply; pin 3 of relay U1 is connected to a power MOSFET and a current limiting unit; pin 4 of relay U1 is connected to a MOSFET driving unit and a power MOSFET and a current limiting unit, respectively; the emitter of transistor V3 is grounded.

[0009] In one preferred embodiment, the power MOSFET and current limiting unit include a MOSFET Q1, resistors R4, R5, and R6, a Zener diode VD1, and a capacitor C5. The drain of the MOSFET Q1 is connected to the rectifier unit and resistor R6. The gate of the MOSFET Q1 is connected to the other end of resistor R6, the cathode of the Zener diode VD1, and capacitor C5. The source of the MOSFET Q1 is connected to the MOSFET driving unit, resistors R4 and R5. The other end of resistor R4 is connected to the MOSFET driving circuit and the second signal conditioning and isolation unit. The other end of resistor R5 is connected to the second signal conditioning and isolation unit. The anode of the Zener diode VD1 and the other end of capacitor C5 are grounded.

[0010] In one preferred embodiment, the MOSFET driving unit includes a switching chip D3, a resistor R3, and a capacitor C1; pins 1, 2, and 4 of the switching chip D3 are grounded; pins 3 and 8 of the switching chip D3 are connected to the resistor R3, the other end of the resistor R3 is connected to the capacitor C1 and the power MOSFET and current limiting unit respectively, and the other end of the capacitor C1 is grounded; pin 5 of the switching chip D3 is connected to the first signal conditioning and isolation unit; pins 6 and 7 of the switching chip D3 are both connected to the second signal conditioning and isolation unit and the power MOSFET and current limiting unit respectively.

[0011] In one preferred embodiment, when the common contact and normally open contact of the relay U1 are open, the switch chip D3 has a built-in switch and a resistor R4 forming a series circuit. The minimum characteristic current amplitude flowing through the drain and source of the MOSFET Q1 is:

[0012] I low =(V z -V Q1gs(th) ) / R4

[0013] Among them, I low V is the minimum characteristic current amplitude flowing through the drain and source of MOSFET Q1. z V is the clamping voltage of the Zener diode VD1. Q1gs(th) R1 is the gate-source voltage difference that turns the drain and source on in MOSFET Q1, and R4 is the resistance value of resistor R4.

[0014] In one preferred embodiment, when the common contact and normally open contact of the relay U1 are short-circuited, the maximum characteristic current amplitude flowing through the drain and source of the MOSFET Q1 is:

[0015]

[0016] Among them, I high V represents the maximum characteristic current amplitude flowing through the drain and source of MOSFET Q1. z V is the clamping voltage of the Zener diode VD1. Q1gs(th) R1 is the gate-source voltage difference that enables the drain and source of the MOSFET Q1 to conduct. R4 is the resistance value of resistor R4, and R5 is the resistance value of resistor R5.

[0017] In one preferred embodiment, the first signal conditioning and isolation unit includes a capacitor C2, a resistor R9, a MOSFET V1, a resistor R7, an optocoupler D2, and a resistor R2; one end of the capacitor C2 is connected to the processor unit, and the other end of the capacitor C2 is connected to the resistor R9 and the gate of the MOSFET V1, respectively; the drain of the MOSFET V1 is connected to pin 2 of the optocoupler D2, pin 1 of the optocoupler D2 is connected to the resistor R7, the other end of the resistor R7 is connected to the power supply terminal, and pin 4 of the optocoupler D2 is connected to the resistor R2 and the MOSFET driving circuit, respectively; pin 3 of the optocoupler D2, the other end of the resistor R9, and the source of the MOSFET V1 are grounded.

[0018] In the above technical solution of this utility model, the amplitude-adaptive characteristic current generation system includes: a rectification unit, a power MOSFET and a current-limiting unit, a MOSFET driving unit, a first signal conditioning and isolation unit, a second signal conditioning and isolation unit, and a processor unit. The processor unit is electrically connected to the first and second signal conditioning and isolation units via wires. The first signal conditioning and isolation unit is electrically connected to the MOSFET driving unit via wires. The MOSFET driving unit and the second signal conditioning and isolation unit are electrically connected to the power MOSFET and the current-limiting unit via wires. The power MOSFET and the current-limiting unit are electrically connected to the rectification unit via wires. The rectification unit is electrically connected to the MOSFET driving unit and to the AC line interface. This utility model solves the technical problem that existing characteristic current generation systems, when configured with a single fixed amplitude characteristic current, cannot simultaneously achieve a high recognition success rate and manage the power consumption and lifespan of the transmitting system.

[0019] In this invention, the current amplitude control signal output by the processing unit is conditioned by the second signal conditioning and isolation unit and output to the power MOSFET and current limiting unit for current amplitude switching. This allows for precise control of the minimum and maximum amplitude characteristic current flowing through the drain and source of the MOSFET Q1. The system defaults to sending the characteristic current with a small amplitude. If the time since the last transmission is less than a first time threshold, a larger amplitude characteristic current is used. This solves the problems of low identification success rate in areas with high current frequency noise or distributed power supply, as well as the shortened product lifespan due to high power consumption in the area. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0021] Fig. 1 This is a first schematic diagram of an amplitude-adaptive characteristic current generation system according to an embodiment of the present invention;

[0022] Fig. 2 This is a second schematic diagram of an amplitude-adaptive characteristic current generation system according to an embodiment of the present invention.

[0023] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the implementation methods and with reference to the accompanying drawings. Detailed Implementation

[0024] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Furthermore, in this utility model, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0026] Furthermore, the technical solutions of the various embodiments of this utility model can be combined with each other, but only if they are based on the ability of a person skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0027] See Figs. 1-2 According to one aspect of the present invention, the present invention provides an amplitude-adaptive characteristic current generating system, wherein the amplitude-adaptive characteristic current generating system comprises:

[0028] The unit includes a rectifier unit, a power MOSFET and current limiting unit, a MOSFET driving unit, a first signal conditioning and isolation unit, a second signal conditioning and isolation unit, and a processor unit.

[0029] The processor unit is electrically connected to the first signal conditioning and isolation unit and the second signal conditioning and isolation unit via wires. The first signal conditioning and isolation unit is electrically connected to the MOS transistor driving unit via wires. The MOS transistor driving unit and the second signal conditioning and isolation unit are electrically connected to the power MOS transistor and the current limiting unit via wires. The power MOS transistor and the current limiting unit are electrically connected to the rectification unit via wires. The rectification unit is electrically connected to the MOS transistor driving unit and to the AC line interface.

[0030] Specifically, in this embodiment, the processor unit sends a PWM signal according to the instructions of the identification device, and simultaneously sends a current amplitude control signal based on whether it is a retransmission of characteristic current. The first signal conditioning and isolation unit receives the PWM signal sent by the processor unit, and after signal conditioning and optocoupler isolation, outputs it to the MOSFET driver unit. The MOSFET driver unit drives the power MOSFET and the current limiting unit according to the PWM signal of the first signal conditioning and isolation unit. The current amplitude control signal sent by the processor unit passes through the second signal conditioning and isolation unit and is input to the power MOSFET and the current limiting unit. The power MOSFET and the current limiting unit generate an adjustable characteristic current according to the PWM signal of the MOSFET driver unit and the current amplitude control signal. The rectifier unit converts the AC voltage of the distribution network into a pulsating DC voltage and provides it to the MOSFET driver unit, the power MOSFET and the current limiting unit, and simultaneously inputs the characteristic current generated by the power MOSFET and the current limiting unit into the distribution network.

[0031] Specifically, in this embodiment, the AC line interface is a 220V distribution network interface, which includes two contacts that are respectively connected to the live wire and the neutral wire of the distribution network. The AC line interface is both the power input interface of the entire circuit and the characteristic current output interface.

[0032] Specifically, in this embodiment, the rectifier unit is used to convert AC 220V power supply into pulsating DC to supply the power MOSFET, current limiting unit, and MOSFET drive unit, while converting the DC characteristic current generated by the power MOSFET and current limiting unit to AC 220V distribution network; the rectifier unit includes a resistor R1 and a rectifier bridge BR1; one end of the resistor R1 is connected to the live wire connection, the other end of the resistor R1 is connected to pin 2 of the rectifier bridge BR1, pin 1 of the rectifier bridge BR1 is connected to the neutral wire connection, pin 3 of the rectifier bridge BR1 is connected to the power MOSFET and current limiting unit, and pin 4 of the rectifier bridge BR1 is connected to the high-voltage ground; the resistor R1 is used for current limiting and protection of the subsequent circuits, and the rectifier bridge BR1 is used to realize the conversion between AC voltage and pulsating DC voltage, as well as current transmission.

[0033] Specifically, in this embodiment, the processor unit is used to output a pulse width modulation signal (PWM signal) with a specified frequency, duty cycle, and duration at a specified time according to the instructions received by the communication unit from the external identification device, and to output a current amplitude control signal according to the previous transmission time interval; the processor unit includes a processor D1, a crystal oscillator XL1, capacitors C3 and C4, and a DC power supply VDD; pin 11 of the processor D1 is connected to the second signal conditioning and isolation unit, and controls the second signal conditioning and isolation unit by generating a current amplitude control signal; pin 12 of the processor D1 is connected to the first signal conditioning and isolation unit, and controls the first signal conditioning and isolation unit by generating a PWM signal of a specific frequency; pin 13 of the processor unit D1 is connected to the DC power supply VDD, pin 33 of the processor D1 is connected to capacitor C3 and crystal oscillator XL1 respectively, and pin 34 of the processor D1 is connected to... Do not connect to capacitor C4 and crystal oscillator XL1. The other ends of crystal oscillator XL1, capacitor C3, and capacitor C4 are grounded. The DC power supply VDD is a 3.3V DC input, which meets the normal operation requirements of processor D1 and the voltage and current required for optocoupler D2 to conduct. The PWM signal and current amplitude control signal output by processor D1 have a high frequency close to VDD and a low level close to the reference ground voltage of the weak current system. Crystal oscillator XL1, capacitor C3, and capacitor C4 form the clock circuit of the processor unit. The clock circuit is used to improve the external clock of processor D1. After frequency division, it becomes the control signal for the coordinated operation of each unit of processor D1. If the clock circuit does not generate a clock to drive processor D1, it cannot complete the operation. In this utility model, processor D1 adopts a processor chip with built-in power line carrier communication function, model WTZ13. This utility model does not impose specific limitations and can be set according to needs.

[0034] Specifically, in this embodiment, the first signal conditioning and isolation unit includes a capacitor C2, a resistor R9, a MOSFET V1, a resistor R7, an optocoupler D2, and a resistor R2; one end of the capacitor C2 is connected to the processor unit, and the other end of the capacitor C2 is connected to the resistor R9 and the gate of the MOSFET V1, respectively. The drain of the MOSFET V1 is connected to pin 2 of the optocoupler D2, pin 1 of the optocoupler D2 is connected to the resistor R7, the other end of the resistor R7 is connected to the power supply terminal, and pin 4 of the optocoupler D2 is connected to the resistor R2 and the MOSFET driving circuit, respectively; pin 3 of the optocoupler D2, ... The other end of resistor R9 and the source of MOSFET V1 are grounded; the first signal conditioning and isolation unit is used to condition the PWM signal output by the processor unit and to electrically isolate the weak current system where the communication unit and processor unit are located from the strong current system where the AC line interface, rectifier unit, MOSFET drive unit, power MOSFET and current limiting unit are located; the capacitor C2, resistor R9 and MOSFET V1 realize the function of isolating DC signals; the resistor R7, optocoupler D2 and resistor R2 transmit the PWM signal generated by the weak current system to the strong current system through optocoupler, which meets the isolation safety requirements between the weak current system and the strong current system; When the PWM signal output by processor D1 changes from low to high, capacitor C2 charges, and the gate voltage of MOSFET V1 rises. When the voltage difference between the gate and source of MOSFET V1 exceeds the turn-on voltage of MOSFET V1, the drain and source of MOSFET V1 conduct. Consequently, the voltage across the LED inside optocoupler D2 exceeds the turn-on voltage, causing the LED to emit light. The collector and emitter of the phototransistor inside optocoupler D2 then conduct. Once the PWM signal has reached a stable high level, due to the presence of bleeder resistor R9, the voltage between the gate and source of MOSFET V1 gradually drops below the turn-on voltage. 2. The internal LED is turned off to prevent the PWM signal from remaining at a high level for a long time due to abnormal operation of the processor D1, which would burn out the power MOSFET Q1 and the current-limiting resistors R4 and R5. When the PWM signal output by the processor D1 changes from high level to low level, capacitor C2 discharges, and the gate voltage of MOSFET V1 drops. When the voltage difference between the gate and source of MOSFET V1 is less than the turn-on voltage of MOSFET V1, the drain and source of MOSFET V1 are turned off. Consequently, the voltage across the internal LED of optocoupler D2 is less than the turn-on voltage, and the internal LED of optocoupler D2 stops emitting light. The collector and emitter of the phototransistor inside optocoupler D2 are in an open circuit.

[0035] Specifically, in this embodiment, the MOS transistor driving unit includes a switch chip D3, a resistor R3, and a capacitor C1; pins 1, 2, and 4 of the switch chip D3 are connected to the reference ground of the high-voltage system; pins 3 and 8 of the switch chip D3 are connected to the resistor R3, the other end of the resistor R3 is connected to the capacitor C1, the power MOS transistor, and the current limiting unit, respectively, and the other end of the capacitor C1 is grounded; pin 5 of the switch chip D3 is connected to the first signal conditioning and isolation unit, and pin 5 of the switch chip D3 is a switch control pin, connected to the collector of the phototransistor built into the optocoupler D2; pins 6 and 7 of the switch chip D3 are respectively connected to the common contact of the output circuit of the relay U1 in the second signal conditioning and isolation unit, the power MOS transistor, and the current limiting unit; the MOS transistor driving unit is used to control the on / off state of the power MOS transistor according to the PWM signal output by the first signal conditioning and isolation unit; the switch chip D3 is an ETA7000 model switch chip, which is not specifically limited in this invention, and can be further customized as needed. The circuit is configured such that a built-in switch exists between pins 1, 2, and 4 and pins 6 and 7 of the switching chip D3. This switch is controlled by the voltage level of pin 5 of the switching chip D3. When the voltage between pin 5 and pins 1, 2, and 4 of the switching chip D3 is less than a threshold, the built-in switch exhibits a low-resistance state; when the voltage between pin 5 and pins 1, 2, and 4 of the switching chip D3 is greater than the threshold, the built-in switch exhibits a high-resistance state. Resistor R3 is a current-limiting resistor, and capacitor C1 is used for energy storage and filtering. Capacitor C1 and... Resistor R3 is used to provide power to switch chip D3; the switch inside switch chip D3, in conjunction with the gate voltage of MOSFET Q1, controls the on / off state between the source and drain of power MOSFET Q1; when the collector and emitter of the phototransistor inside optocoupler D2 are turned on, the voltage at the enable pin of switch chip D3 is lower than the threshold, and the switch inside switch chip D3 is in a low resistance state; when the collector and emitter of the phototransistor inside optocoupler D2 are open, the voltage at the enable pin of switch chip D3 is higher than the threshold, and the switch inside switch chip D3 is in a high resistance state.

[0036] Specifically, in this embodiment, the second signal conditioning and isolation unit includes a relay U1, a transistor V3, and a resistor R8; the base of the transistor V3 is connected to the processor unit; the collector of the transistor V3 is connected to pin 2 of the relay U1, pin 1 of the relay U1 is connected to the resistor R8, the other end of the resistor R8 is connected to a DC power supply, pin 3 of the relay U1 is connected to a power MOSFET and a current limiting unit, and pin 4 of the relay U1 is connected to both the MOSFET driver unit and the power MOSFET and current limiting unit; the emitter of the transistor V3 is grounded; the second signal conditioning and isolation unit is used to condition the current amplitude control signal output by the processor unit, and to condition the weak current system and AC line interface, rectifier unit, MOSFET driver unit, and power MOSFET and current limiting unit where the communication unit and processor unit are located. The unit is electrically isolated from the high-voltage system. Pin 3 of relay U1 is a normally open contact, and pin 4 is a common contact. When the current amplitude control signal level output by the processor unit is higher than the Vbe voltage threshold that turns on the collector and emitter of transistor V3, the collector and emitter of transistor V3 conduct. Power supply VCC supplies power to the input circuit of relay U1 through resistor R8 and transistor V3, causing the input circuit of relay U1 to operate and short-circuit the common and normally open contacts of the output circuit. When the current amplitude control signal level output by the processor unit is lower than the Vbe voltage threshold that turns on the collector and emitter of transistor V3, the input circuit of relay U1 stops operating and opens the common and normally open contacts of the output circuit. The relay's input circuit transmits the signal to the output circuit through a magnetic field, satisfying the electrical isolation requirements between low-voltage and high-voltage systems.

[0037] Specifically, in this embodiment, the power MOSFET and current limiting unit include a MOSFET Q1, resistors R4, R5, and R6, a Zener diode VD1, and a capacitor C5. The drain of the MOSFET Q1 is connected to the rectifier unit and resistor R6, the gate of the MOSFET Q1 is connected to the other end of resistor R6, the cathode of the Zener diode VD1, and capacitor C5, the source of the MOSFET Q1 is connected to the MOSFET driving unit, resistors R4 and R5, the other end of resistor R4 is connected to the MOSFET driving circuit and the second signal conditioning and isolation unit, and the other end of resistor R5 is connected to the second signal conditioning and isolation unit. The anode of the Zener diode VD1 and capacitor C5 are connected to the MOSFET driving circuit and the second signal conditioning and isolation unit. The other end of C5 is grounded; the power MOSFET and current limiting unit are used to switch the pulsating DC current on and off according to the PWM signal output by the MOSFET drive unit, and to switch the current amplitude according to the current amplitude control signal; the resistor R6 provides power to the gate of the power MOSFET Q1 and the Zener diode VD1; the capacitor C5 is used to filter the gate power supply of the power MOSFET Q1; the Zener diode VD1 is used to clamp the gate voltage of the power MOSFET Q1; the switch inside the switching chip D3, in conjunction with the gate voltage of the MOSFET Q1, controls the on / off state between the source and drain of the power MOSFET Q1; the resistors R4 and R5 limit the current flowing through the drain and source of the power MOSFET Q1.

[0038] Specifically, in this embodiment, when the common contact and normally open contact of the relay U1 are open, the internal switch of the switch chip D3 and the resistor R4 form a series circuit. When the internal switch of the switch chip D3 is closed, pulsating DC current flows through the drain and source of the MOS transistor Q1, the resistor R4, and the internal switch of the switch chip D3 to form a current. When the internal switch of the switch chip D3 is open, the MOS transistor Q1 and the resistor R4 cannot form a circuit, and the pulsating DC current will not form a current. During the period when the pulsating DC current forms a current, the current amplitude flowing through the drain and source of the MOS transistor Q1 is determined by the gate voltage of the MOS transistor Q1, the gate-source voltage difference that turns on the drain and source of the MOS transistor Q1, and the current-limiting resistor R4. The minimum characteristic current amplitude flowing through the drain and source of the MOS transistor Q1 is:

[0039] I low =(V z -V Q1gs(th) ) / R4

[0040] Among them, I low V is the minimum characteristic current amplitude flowing through the drain and source of MOSFET Q1. z V is the clamping voltage of the Zener diode VD1. Q1gs(th) R1 is the gate-source voltage difference that turns the drain and source on in MOSFET Q1, and R4 is the resistance value of resistor R4.

[0041] Specifically, in this embodiment, when the common contact and normally open contact of the relay U1 are short-circuited, the maximum characteristic current amplitude flowing through the drain and source of the MOS transistor Q1 is:

[0042]

[0043] Among them, I high V represents the maximum characteristic current amplitude flowing through the drain and source of MOSFET Q1. z V is the clamping voltage of the Zener diode VD1. Q1gs(th) R1 is the gate-source voltage difference that enables the drain and source of the MOSFET Q1 to conduct. R4 is the resistance value of resistor R4, and R5 is the resistance value of resistor R5.

[0044] Specifically, in this embodiment, the amplitude-adaptive characteristic current generation system further includes a communication unit. The output terminal of the communication unit is electrically connected to the input terminal of the processor unit. The communication unit establishes a communication channel between the processor unit and the external identification device through power line carrier, low-power wireless, or public wireless communication. The communication unit receives instructions from the identification device and transmits them to the processor unit to determine the transmission time, frequency, duty cycle, and duration of the characteristic current.

[0045] Specifically, in this embodiment, after activating the amplitude-adaptive characteristic current generation system, the system monitors the status of the identification device notification. Upon receiving the instruction from the identification device to send the characteristic current, it first obtains the time interval between the previous transmission and the current transmission. If the time interval between the previous transmission and the current transmission is greater than a first time threshold, the characteristic current is sent with the minimum amplitude. If the time interval between the previous transmission and the current transmission is less than or equal to the first time threshold, the characteristic current is sent with the maximum amplitude. After the transmission is completed, the system returns to the monitoring state. In this invention, the first time threshold is 4 hours. This invention does not impose a specific limitation and can be set according to specific needs.

[0046] Specifically, in this embodiment, when the PWM pulse weak signal output by the processor unit rises from a low level to a high level, the DC blocking capacitor C2 of the first signal conditioning and isolation unit charges, the MOS transistor V1 turns on, the built-in LED of the optocoupler D2 emits light, the collector and emitter of the built-in phototransistor are turned on, the enable pin voltage of the switching chip D3 drops to near 0V, and the built-in switch exhibits low resistance; the voltage difference between the gate and source of the power MOS transistor Q1 is greater than the conduction voltage threshold, the drain and source are turned on, and a corresponding characteristic current is generated as the processor outputs the pulsating PWM signal; when the PWM pulse weak signal output by the processor unit falls from a high level to a low level, the DC blocking capacitor C2 of the first signal conditioning and isolation unit discharges, the MOS transistor V1 turns off, and the built-in LED of the optocoupler D2 stops. The light emission is stopped, the collector and emitter of the built-in phototransistor are cut off, the voltage at the enable pin of the switching chip D3 increases, and the built-in switch presents high resistance; the drain and source of the power MOSFET Q1 are cut off, and the voltage difference between the gate and source of the power MOSFET Q1 is less than the conduction voltage threshold, so the characteristic current is stopped; if the PWM signal is kept at a fixed level for a long time, the charge stored in capacitor C2 will be discharged through resistor R9. When the voltage drops below the conduction threshold of MOSFET V1, the characteristic current will also stop being generated; the second signal conditioning and isolation unit can determine whether the current limiting resistor R5 is engaged based on the current amplitude control signal output by the processor unit; when the current amplitude control signal is low, the common contact and normally open contact of relay U1 are open, and the current limiting resistor R5 is not engaged; the built-in switch of the switching chip D3 and the current limiting resistor R4 form a series circuit. During the pulsating DC current generation period, the current amplitude flowing through the drain and source of power MOSFET Q1 is determined by the gate voltage of MOSFET Q1, the gate-source voltage difference that turns on the drain and source of Q1, and the resistance value of current-limiting resistor R4; the minimum characteristic current amplitude flowing through the drain and source of MOSFET Q1 is:

[0047] I low =(V z -V Q1gs(th) ) / R4

[0048] Among them, I low V is the minimum characteristic current amplitude flowing through the drain and source of MOSFET Q1. z V is the clamping voltage of the Zener diode VD1. Q1gs(th) R1 is the gate-source voltage difference that turns the drain and source on in MOSFET Q1, and R4 is the resistance value of resistor R4.

[0049] Correspondingly, when the current amplitude control signal is high, the common contact and normally open contact of relay U1 are short-circuited, and the current-limiting resistor R5 is engaged; the resistance value of the current-limiting resistor in the current path changes from the resistance value of resistor R4 to the parallel resistance value of resistors R4 and R5; the maximum characteristic current amplitude flowing through the drain and source of MOSFET Q1 is:

[0050]

[0051] Among them, I high V represents the maximum characteristic current amplitude flowing through the drain and source of MOSFET Q1. z V is the clamping voltage of the Zener diode VD1. Q1gs(th) R1 represents the gate-source voltage difference that enables the drain and source of MOSFET Q1 to conduct. R4 represents the resistance value of resistor R4, and R5 represents the resistance value of resistor R5.

[0052] By selecting the device parameters, it is possible to precisely control the small-amplitude and large-amplitude characteristic currents flowing through the drain and source of the MOS transistor Q1.

[0053] The above are merely preferred embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural transformations made based on the inventive concept of this utility model and the contents of this utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this utility model.

Claims

1. A magnitude adaptive feature current generation system, characterized by, It includes: The rectifier unit, power MOS tube and current limiting unit, MOS tube driving unit, first signal conditioning and isolation unit, second signal conditioning and isolation unit and processor unit; The processor unit is electrically connected with the first signal conditioning and isolation unit and the second signal conditioning and isolation unit through wires, the first signal conditioning and isolation unit is electrically connected with the MOS tube driving unit through wires, the MOS tube driving unit and the second signal conditioning and isolation unit are electrically connected with the power MOS tube and current limiting unit through wires, the power MOS tube and current limiting unit are electrically connected with the rectifier unit through wires, the rectifier unit is electrically connected with the MOS tube driving unit, and the rectifier unit is electrically connected with the AC line interface.

2. The amplitude adaptive feature current generation system of claim 1, wherein, The second signal conditioning and isolation unit includes a relay U1, a transistor V3 and a resistor R8; The base of the transistor V3 is connected with the processor unit; the collector of the transistor V3 is connected with the 2 pin of the relay U1, the 1 pin of the relay U1 is connected with the resistor R8, the other end of the resistor R8 is connected with the DC power supply, the 3 pin of the relay U1 is connected with the power MOS tube and current limiting unit, the 4 pin of the relay U1 is connected with the MOS tube driving unit and the power MOS tube and current limiting unit respectively; the emitter of the transistor V3 is grounded.

3. The amplitude adaptive feature current generation system of claim 2, wherein, The power MOS tube and current limiting unit includes a MOS tube Q1, a resistor R4, a resistor R5, a resistor R6, a voltage stabilizing diode VD1 and a capacitor C5; the drain of the MOS tube Q1 is connected with the rectifier unit and the resistor R6 respectively, the gate of the MOS tube Q1 is connected with the other end of the resistor R6, the cathode of the voltage stabilizing diode VD1 and the capacitor C5 respectively, the source of the MOS tube Q1 is connected with the MOS tube driving unit, the resistor R4 and the resistor R5 respectively, the other end of the resistor R4 is connected with the MOS tube driving circuit and the second signal conditioning and isolation unit respectively, the other end of the resistor R5 is connected with the second signal conditioning and isolation unit; the anode of the voltage stabilizing diode VD1 and the other end of the capacitor C5 are grounded.

4. The amplitude adaptive feature current generation system of claim 3, wherein, The MOS tube driving unit includes a switch chip D3, a resistor R3 and a capacitor C1; the 1, 2 and 4 pins of the switch chip D3 are grounded; the 3 and 8 pins of the switch chip D3 are connected with the resistor R3, the other end of the resistor R3 is connected with the capacitor C1 and the power MOS tube and current limiting unit respectively, the other end of the capacitor C1 is grounded; the 5 pin of the switch chip D3 is connected with the first signal conditioning and isolation unit; the 6 and 7 pins of the switch chip D3 are connected with the second signal conditioning and isolation unit and the power MOS tube and current limiting unit respectively.

5. The amplitude adaptive feature current generation system of claim 4, wherein, When the common contact and the normally open contact of the relay U1 are open, the built-in switch of the switch chip D3 and the resistor R4 form a series circuit, and the minimum characteristic current amplitude flowing through the drain and the source of the MOS tube Q1 is: I low = (V z - V Q1gs(th) ) / R4 where I low is the minimum characteristic current amplitude flowing through the drain and source of the MOS transistor Ql, V z is the clamping voltage of the zener diode VDl, V Q1gs(th) is the gate-source voltage difference that turns on the drain and source of the MOS transistor Ql, R4 is the resistance value of the resistor R4.

6. The amplitude adaptive feature current generation system of claim 4, wherein, When the common contact and the normally open contact of the relay U1 are short-circuited, the maximum characteristic current amplitude flowing through the drain and the source of the MOS tube Q1 is: where I high is the maximum characteristic current amplitude flowing through the drain and source of the MOS transistor Q1, V z is the clamping voltage of the voltage stabilizing diode VD1, V Q1gs(th) is the gate-source voltage difference which turns on the drain and source of the MOS transistor Q1, R4 is the resistance value of the resistor R4, and R5 is the resistance value of the resistor R5.

7. A magnitude adaptive feature current generation system according to any one of claims 1-6, characterized in that, The first signal conditioning and isolation unit comprises a capacitor C2, a resistor R9, a MOS tube V1, a resistor R7, an optical coupling isolator D2 and a resistor R2; one end of the capacitor C2 is connected with the processor unit, the other end of the capacitor C2 is connected with the resistor R9 and the gate of the MOS tube V1 respectively, the drain of the MOS tube V1 is connected with the 2 pin of the optical coupling isolator D2, the 1 pin of the optical coupling isolator D2 is connected with the resistor R7, the other end of the resistor R7 is connected with the power supply end, the 4 pin of the optical coupling isolator D2 is connected with the resistor R2 and the MOS tube driving circuit respectively; the 3 pin of the optical coupling isolator D2, the other end of the resistor R9 and the source of the MOS tube V1 are grounded.

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