Reverse-connection-free protection circuit for polar capacitor

Abstract

The utility model provides a non-reverse-connection protection circuit for a polar capacitor. The non-reverse-connection protection circuit comprises a triode Q1, a triode Q2, an MOS tube Q3, a diode D1, a diode D2, a diode D3, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a polar capacitor C1, a first power input end VIN1 and a second power input end VIN2. Compared with the prior art, charging and discharging of the polar capacitor are not affected during normal operation, breakdown of the polar capacitor is avoided during reverse connection, additional power reverse prevention is not needed, and the thermal problem of power reverse prevention is solved at the same time.

Description

[Technical Field]

[0001] This utility model relates to the field of circuit design technology, and in particular to a reverse connection protection circuit for polarized capacitors. [Background Technology]

[0002] Because electrolytic capacitors are polarized devices, reversing the polarity can lead to explosions and burnout. For low-power products, polarity protection for electrolytic capacitors is mostly achieved using reverse-biased diodes and MOSFETs. The unidirectional conductivity of the diodes and MOSFETs protects the electrolytic capacitor from polarity issues.

[0003] For high-power products, capacitor values ​​are typically large, with electrolytic capacitors being the most common type. Since electrolytic capacitors are polarized, polarity protection is essential. Current electrolytic capacitor polarity protection circuits generally employ reverse-biased diodes and MOSFETs. However, high-power products have very high input currents, resulting in high on-resistance for diodes and MOSFETs, leading to high power consumption and significant heat generation. This limits the availability of suitable diodes and MOSFETs. Furthermore, the presence of large-capacity capacitors in the circuit results in significant inrush current during power-on, placing even higher demands on the polarity protection devices for electrolytic capacitors.

[0004] Therefore, it is necessary to propose a new technical solution to address the above problems. [Utility Model Content]

[0005] One of the purposes of this utility model is to provide a reverse-connection protection circuit for polarized capacitors, which not only ensures that the charging and discharging of polarized capacitors is unaffected during normal operation and prevents breakdown of polarized capacitors when reverse connected, but also eliminates the need for additional power reverse protection and solves the thermal problem of power reverse protection.

[0006] According to one aspect of this utility model, a reverse-connection protection circuit for polarized capacitors is provided, comprising transistors Q1, Q2, Q3, diodes D1, D2, and D3, resistors R2, R3, R4, R5, R7, R8, R9, and R10, a polarized capacitor C1, a first power input terminal VIN_1, and a second power input terminal VIN_2. One end of resistor R7 is connected to the first power input terminal VIN_1, and the other end is connected to the second power input terminal VIN_2. The cathode of diode D1 is connected to the first power input terminal VIN_1 via resistor R2, and its anode is connected to the first connection terminal of transistor Q1. The control terminal of transistor Q1 is connected to the anode of diode D3 via resistor R8, and its second connection terminal is connected to the second power input terminal VIN_2. The cathode of diode D3 is connected to the first power input terminal VIN_1. One end of resistor R9 is connected to the control terminal of transistor Q1, and the other end is connected to the second power input terminal VIN_2; the cathode of diode D2 is connected to the first power input terminal VIN_1, and its anode is connected to the first connection terminal of transistor Q2; the control terminal of transistor Q2 is connected to the first connection terminal of transistor Q1 via resistor R5, and its second connection terminal is connected to the second power input terminal VIN_2 via resistor R10; the first connection terminal of MOSFET Q3 is connected to the first power input terminal VIN_1 via resistor R4, its control terminal is connected to the second connection terminal of transistor Q2, and its second connection terminal is connected to the second power input terminal VIN_2; one end of resistor R3 is connected to the first power input terminal VIN_1, and the other end is connected to the control terminal of MOSFET Q3; the anode of polarized capacitor C1 is connected to the first power input terminal VIN_1, and its cathode is connected to the first connection terminal of MOSFET Q3.

[0007] Furthermore, when the positive terminal of the power supply is connected to the first power input terminal VIN_1 and the negative terminal of the power supply is connected to the second power input terminal VIN_2, the MOSFET Q3 is turned on, the transistor Q1 is turned off, the transistor Q2 is turned off, and the diodes D1, D2, and D3 are all reverse-biased and cut off; when the negative terminal of the power supply is connected to the first power input terminal VIN_1 and the positive terminal of the power supply is connected to the second power input terminal VIN_2, the MOSFET Q3 is turned off, the transistor Q1 is turned on, the transistor Q2 is turned on, and the diodes D1, D2, and D3 are all forward-biased.

[0008] Furthermore, the resistance values ​​of resistors R3 and R10 are selected to satisfy the following condition: when the positive terminal of the power supply is connected to the first power input terminal VIN_1 and the negative terminal of the power supply is connected to the second power input terminal VIN_2, the voltage drop across resistor R10 is greater than the turn-on voltage threshold Vgs_th of MOSFET Q3, so that MOSFET Q3 is in the on state.

[0009] Furthermore, transistor Q1 is a PNP transistor, and its first connection terminal, second connection terminal, and control terminal are the collector, emitter, and base of the PNP transistor, respectively; transistor Q2 is an NPN transistor, and its first connection terminal, second connection terminal, and control terminal are the emitter, collector, and base of the NPN transistor, respectively; MOSFET Q3 is an NMOS transistor, and its first connection terminal, second connection terminal, and control terminal are the source, drain, and gate of the NMOS transistor, respectively.

[0010] Furthermore, the polarized capacitor C1 is an electrolytic capacitor.

[0011] Compared with the prior art, this utility model not only ensures that the charging and discharging of polarized capacitors are unaffected during normal operation and that polarized capacitors will not break down when reverse connected, but also eliminates the need for additional power reverse protection and solves the thermal problem of power reverse protection. [Attached Image Description]

[0012] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0013] Figure 1 This is a circuit diagram of a reverse-connection protection circuit for polarized capacitors in one embodiment of the present invention.

Detailed Implementation Methods

[0014] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that excludes other embodiments. Unless otherwise specified, the terms coupling, connection, linking, and interconnection used herein to indicate electrical connection mean direct or indirect connection. For example, A being connected to B includes both a direct electrical connection between A and B and a connection between A and B via electrical components or circuits.

[0016] In the description of this utility model, it should be understood that the terms "upper", "lower", "front", "back", "positive", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0017] Please refer to Figure 1 As shown, it is a circuit diagram of a reverse-connection protection circuit for polarized capacitors in one embodiment of the present invention. Figure 1 The reverse connection protection circuit shown for polarized capacitors includes transistors Q1, Q2, Q3, diodes D1, D2, and D3, resistors R2, R3, R4, R5, R7, R8, R9, and R10, a polarized capacitor C1, a first power input terminal VIN_1, and a second power input terminal VIN_2.

[0018] In this configuration, one end of resistor R7 is connected to the first power input terminal VIN_1, and the other end is connected to the second power input terminal VIN_2; the cathode of diode D1 is connected to the first power input terminal VIN_1 via resistor R2, and its anode is connected to the first connection terminal of transistor Q1; the control terminal of transistor Q1 is connected to the anode of diode D3 via resistor R8, and its second connection terminal is connected to the second power input terminal VIN_2; the cathode of diode D3 is connected to the first power input terminal VIN_1; one end of resistor R9 is connected to the control terminal of transistor Q1, and the other end is connected to the second power input terminal VIN_2; the cathode of diode D2 is connected to the first power input terminal VIN_1, and its anode is connected to the second power input terminal VIN_2. The first terminal of transistor Q1 is connected to the first terminal of transistor Q2; the control terminal of transistor Q2 is connected to the first terminal of transistor Q1 via resistor R5, and its second terminal is connected to the second power input terminal VIN_2 via resistor R10; the first terminal of MOSFET Q3 is connected to the first power input terminal VIN_1 via resistor R4, and its control terminal is connected to the second terminal of transistor Q2, which is also connected to the second power input terminal VIN_2; one end of resistor R3 is connected to the first power input terminal VIN_1, and the other end is connected to the control terminal of MOSFET Q3; the positive terminal of polarized capacitor C1 is connected to the first power input terminal VIN_1, and its negative terminal is connected to the first terminal of MOSFET Q3.

[0019] When the positive terminal of the power supply (not shown) is connected to the first power input terminal VIN_1 and the negative terminal of the power supply is connected to the second power input terminal VIN_2, MOSFET Q3 is turned on, transistor Q1 is turned off, transistor Q2 is turned off, and diodes D1, D2, and D3 are all reverse-biased and cut off. When the negative terminal of the power supply is connected to the first power input terminal VIN_1 and the positive terminal of the power supply is connected to the second power input terminal VIN_2, MOSFET Q3 is turned off, transistor Q1 is turned on, transistor Q2 is turned on, and diodes D1, D2, and D3 are all forward-biased, thus achieving reverse-bias protection for polarized capacitor C1.

[0020] exist Figure 1 In the specific embodiment shown, the polarized capacitor C1 is a large polarized capacitor, such as an electrolytic capacitor.

[0021] exist Figure 1In the specific embodiment shown, transistor Q1 is a PNP transistor, and the first connection terminal, the second connection terminal, and the control terminal of transistor Q1 are the collector, emitter, and base of the PNP transistor, respectively; transistor Q2 is an NPN transistor, and the first connection terminal, the second connection terminal, and the control terminal of transistor Q2 are the emitter, collector, and base of the NPN transistor, respectively; MOSFET Q3 is an NMOS transistor (N-Metal-Oxide-Semiconductor), and the first connection terminal, the second connection terminal, and the control terminal of MOSFET Q3 are the source, drain, and gate of the NMOS transistor, respectively.

[0022] The values ​​of resistors R3 and R10 are chosen to satisfy the following condition: when the positive terminal of the power supply is connected to the first power input terminal VIN_1 and the negative terminal of the power supply is connected to the second power input terminal VIN_2, the voltage drop across resistor R10 is greater than the turn-on threshold voltage Vgs_th of MOSFET Q3, thus ensuring that MOSFET Q3 is in the on state. The following details this process. Figure 1 The diagram illustrates the working principle of a reverse-connection protection circuit for polarized capacitors.

[0023] ■Parameter Definition

[0024] ●The forward voltage drop of diode D1 is U1_PN;

[0025] ●The forward voltage drop of diode D2 is U2_PN;

[0026] ●The forward voltage drop of diode D3 is U3_PN;

[0027] ●The voltage division between resistors R3 and R10 is Ur3_r10;

[0028] ●The turn-on voltage of MOSFET Q3 is Uq3_th;

[0029] ●The body diode voltage of MOSFET Q3 is Vq3_pn;

[0030] ● The charging current of polarized capacitor C1 is Iq3_dson;

[0031] ●The on-channel resistance of MOSFET Q3 is rq3_dson;

[0032] ●The base current of transistor Q1 is iq1_b;

[0033] ●The collector current of transistor Q1 is iq1_c;

[0034] ●The PN junction voltage of transistor Q1 is Vq1_pn;

[0035] ●The amplification factor of transistor Q1 is β1;

[0036] ● The saturation voltage of transistor Q1 is Vq1_sat;

[0037] ● The base current of transistor Q2 is iq2_b;

[0038] ● The collector current of transistor Q2 is iq2_c;

[0039] ● The PN junction voltage of transistor Q2 is Vq2_pn;

[0040] ● The amplification factor of transistor Q2 is β2;

[0041] ● The saturation voltage of transistor Q2 is Vq2_sat.

[0042] ■ When the first power input terminal VIN1 is at a high level and the second power input terminal VIN2 is at a low level, it is defined as the normal working state

[0043] 1. When the second power input terminal VIN2 is at a low level, the cathodes of diodes D1, D2, and D3 are all connected to the first power input terminal VIN1. The first power input terminal VIN1 is the input positive voltage, making diodes D1, D2, and D3 all in the reverse cut-off state. Diodes D1, D2, and D3 do not work. The breakdown voltage of the PN junctions of transistors Q1 and Q2 is about 5V. The non-conduction of diodes D1, D2, and D3 protects transistors Q1 and Q2 from being broken down;

[0044] 2. Since the emitter of transistor Q1 is connected to VIN2 = 0V, the PN junction voltage of transistor Q1 is Uq1_pn, that is, VIN2 < Uq1_pn, and transistor Q1 operates in the cut-off state;

[0045] 3. Through the analysis in 1 above, the cathodes of diodes D1 and D2 are connected to the first power input terminal VIN1 and are in a high-level state, that is, both diodes D1 and D2 operate in the reverse-biased cut-off state, so transistor Q2 operates in the cut-off state;

[0046] 4. Before the channel of MOS transistor Q3 is opened, the path is resistor R4, the body diode of MOS transistor Q3 to the second power input terminal VIN2. The source voltage of MOS transistor Q3 is clamped at the Vq3_pn voltage. However, due to the voltage division of resistor R3 and resistor R10 by MOS transistor Q3, the divided voltage is Ur3_r10 ≈ VIN1 * (R10 / (R3 + R10)), and the turn-on voltage of MOS transistor Q3 is Uq3_th. If Ur3_r10 > Uq3_th is designed, the channel of MOS transistor Q3 will be opened. At this time, the body diode of MOS transistor Q3 will be bypassed, forming a low-resistance state. The voltage changes from Vq3_pn to Iq3_dson * rq3_dson, and forms a series connection with the polar capacitor C1, and can normally supply power to the load terminal, that is, it satisfies the charge and discharge process of the polar capacitor C1;

[0047] 5. From the above analysis, when working in the normal state, the triode Q1 is turned off, the triode Q2 is powered off, the diodes D1, D2, and D3 are all reverse-biased and cut off, and only the MOS transistor Q3 is working (or conducting) normally, ensuring the normal charging and discharging of the polar capacitor C1.

[0048] ■ When the first power input terminal VIN1 is at a low level and the second power input terminal VIN2 is at a high level, it is defined as an abnormal working state.

[0049] 1. When the first power input terminal VIN1 = 0V, the path 1 is from the second power input terminal VIN2 through the PN junction of the MOS transistor Q1, the resistor R8, and the diode D3 to the first power input terminal VIN1. At this time, the triode Q1 has a base current, and the triode Q1 conducts. The designed base current is iq1_b ≈ ((VIN2 - Vq1_pn - U3_PN) / R8) - Vq1_pn / R9. Assuming the designed collector saturation current is iq1_sat ≈ ((VIN2 - Vq1_sat) - U3_PN) / R2, by analyzing iq1_c = iq1_b * β1 > iq1_sat, the triode Q1 works in the saturation state, and the collector of the triode Q1 is at a high potential; 2. Similarly, the collector voltage of the triode Q1 (VIN2 - Vq1_sat) > (U2_PN + Vq2_pn), the triode Q2 enters the conduction state, and the designed base current is iq2_b ≈ ((VIN2 - Vq1_sat - Vq2_pn - U2_PN) / R5) - (VIN2 - Vq1_sat – U1_PN) / R2. Assuming the designed collector saturation current is iq2_sat ≈ (VIN2 - Vq2_sat - U2_PN) / R10, ignoring the current flowing through the resistor R3, by analyzing iq2_c = iq2_b * β2 > iq2_sat, the triode Q2 works in the saturation state, and the collector potential of the triode Q2 is (Vq2_sat + U2_PN) < Uq3_th, so the channel between the source and drain of the MOS transistor Q3 is turned off. Since the cathode of the body diode is connected to a high potential and the anode is connected to a low potential through the resistor R4, the body diode works in the reverse-biased and cut-off state. Through the above analysis, the MOS transistor Q3 works in the cut-off state, and the polar capacitor C1 will not be in a state of reverse voltage operation;

[0050] 3. Through the above analysis, when working in the abnormal state, the triode Q1 conducts, the triode Q2 conducts, the diodes D1, D2, and D3 are all forward-biased and conducting, and the MOS transistor Q3 does not work (i.e., is turned off), ensuring that there will be no reverse voltage across the polar capacitor C1.

[0051] In summary, resistor R7 limits the current of U1; resistors R2, R4, R5, R8, and R10 limit the current of transistors Q1 and Q2 and the body diode of MOSFET Q3; resistor R3 divides the voltage with resistor R10 to provide the operating voltage of MOSFET Q3; resistor R9 ensures the absolute turn-off of transistor Q1; diodes D1, D2, and D3 protect the PN junctions of transistors Q1 and Q2 in abnormal conditions; and MOSFET Q3 interrupts the operation of capacitor C1.

[0052] In summary, the beneficial effects of the reverse connection protection circuit for polarized capacitors provided by this utility model are as follows:

[0053] 1) This utility model can ensure that the charging and discharging of polarized capacitors are not affected during normal operation, and that polarized capacitors will not break down when reverse connected;

[0054] 2) This utility model does not require additional power anti-reverse and solves the heat problem of power anti-reverse.

[0055] The reverse-connection protection circuit for polarized capacitors provided by this invention can be applied to the protection of polarized capacitors in high-power automotive and consumer products. In the absence of other polarity protection circuits, this reverse-connection protection circuit can achieve polarity protection for polarized capacitors (e.g., electrolytic capacitors) without causing significant temperature rise to other components of the product due to the addition of additional polarity protection circuits.

[0056] It should be noted that any modifications made by those skilled in the art to the specific embodiments of this utility model do not depart from the scope of the claims of this utility model. Accordingly, the scope of the claims of this utility model is not limited to the foregoing specific embodiments.

Claims

1. A reverse-connection protection circuit for polarized capacitors, characterized in that, It includes transistor Q1, transistor Q2, MOSFET Q3, diodes D1, D2, and D3, resistors R2, R3, R4, R5, R7, R8, R9, and R10, a polarized capacitor C1, a first power input terminal VIN_1, and a second power input terminal VIN_2. One end of resistor R7 is connected to the first power input terminal VIN_1, and the other end is connected to the second power input terminal VIN_2; the cathode of diode D1 is connected to the first power input terminal VIN_1 via resistor R2, and its anode is connected to the first connection terminal of transistor Q1; the control terminal of transistor Q1 is connected to the anode of diode D3 via resistor R8, and its second connection terminal is connected to the second power input terminal VIN_2; the cathode of diode D3 is connected to the first power input terminal VIN_1; one end of resistor R9 is connected to the control terminal of transistor Q1, and the other end is connected to the second power input terminal VIN_2; the cathode of diode D2 is connected to the first power input terminal VIN_1, and its anode is connected to the second power input terminal VIN_2. The first terminal of the transistor Q2 is connected to the first terminal of the transistor Q1 via resistor R5, and its second terminal is connected to the second power input terminal VIN_2 via resistor R10; the first terminal of the MOSFET Q3 is connected to the first power input terminal VIN_1 via resistor R4, and its control terminal is connected to the second terminal of the transistor Q2, which is also connected to the second power input terminal VIN_2; one end of resistor R3 is connected to the first power input terminal VIN_1, and the other end is connected to the control terminal of the MOSFET Q3; the positive terminal of the polarized capacitor C1 is connected to the first power input terminal VIN_1, and its negative terminal is connected to the first terminal of the MOSFET Q3.

2. The reverse connection protection circuit for polarized capacitors according to claim 1, characterized in that, When the positive terminal of the power supply is connected to the first power input terminal VIN_1 and the negative terminal of the power supply is connected to the second power input terminal VIN_2, the MOSFET Q3 is turned on, the transistor Q1 is turned off, the transistor Q2 is turned off, and the diodes D1, D2, and D3 are all reverse-biased and cut off. When the negative terminal of the power supply is connected to the first power input terminal VIN_1 and the positive terminal of the power supply is connected to the second power input terminal VIN_2, the MOSFET Q3 is turned off, the transistor Q1 is turned on, the transistor Q2 is turned on, and the diodes D1, D2, and D3 are all forward-biased.

3. The reverse connection protection circuit for polarized capacitors according to claim 2, characterized in that, The resistance values ​​of resistors R3 and R10 are selected to satisfy the following condition: when the positive terminal of the power supply is connected to the first power input terminal VIN_1 and the negative terminal of the power supply is connected to the second power input terminal VIN_2, the voltage drop across resistor R10 is greater than the turn-on voltage threshold Vgs_th of MOSFET Q3, so that MOSFET Q3 is in the on state.

4. The reverse connection protection circuit for polarized capacitors according to claim 2, characterized in that, The transistor Q1 is a PNP transistor, and the first connection terminal, the second connection terminal, and the control terminal of the transistor Q1 are the collector, emitter, and base of the PNP transistor, respectively. The transistor Q2 is an NPN transistor, and the first connection terminal, the second connection terminal, and the control terminal of the transistor Q2 are the emitter, collector, and base of the NPN transistor, respectively. The MOS transistor Q3 is an NMOS transistor, and the first connection terminal, the second connection terminal, and the control terminal of the MOS transistor Q3 are the source, drain, and gate of the NMOS transistor, respectively.

5. The reverse-connection protection circuit for polarized capacitors according to any one of claims 1-4, characterized in that, The polarized capacitor C1 is an electrolytic capacitor.

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