Chip packaging structure of isolation transmission device and millimeter wave isolator

Abstract

The utility model provides a chip packaging structure of an isolation transmission device, and a millimeter wave isolator. The millimeter wave isolator comprises an upper insulating layer, a chip insulating layer and a lower insulating layer which are sequentially stacked from top to bottom. The transmitting chip and the receiving chip are arranged in the chip insulating layer; the transmitting circuit and the receiving circuit are arranged on the upper insulating layer; the transmitting end signal pin and the receiving end signal pin are positioned on the lower insulating layer; the transmitting chip is respectively communicated with the transmitting circuit and the transmitting end signal pin through the transmitting end conductive column; and the receiving chip is respectively communicated with the receiving circuit and the receiving end signal pin through the receiving end conductive column. According to the utility model, the chip is arranged in the insulating material without additional packaging protection, so that the project period can be shortened, the cost is reduced, and the overall thickness of the structure is also reduced; and shortening of a signal communication path and optimization of a heat dissipation mode can be realized.

Description

Technical Field

[0001] This utility model relates to the field of wireless transmission technology, specifically to the chip packaging structure of an isolation transmission device and a millimeter-wave isolator. Background Technology

[0002] Most existing wireless transmission devices use, for example Figure 1 (a) The wire bonding process shown or as Figure 1 (b) Flip-chip technology for chip packaging. Both wire bonding and flip-chip technologies require mounting the communication chip onto a carrier board and then encapsulating it with molding compound for protection. This results in a longer processing cycle, larger size, and higher cost. Furthermore, transmitting / receiving signals requires vias or wiring to connect the chip to the transmitting / receiving circuitry, leading to longer signal paths and higher parasitic parameters. Additionally, for high-power transmission structures, the standard heat dissipation devices can only provide limited cooling capacity. Figure 1 As shown in (c), it is mounted on the upper surface of the package as an external structure, which results in a large heat dissipation device with a long upward heat dissipation path and high thermal resistance. In addition, the heat dissipation device is generally made of metal, which will also affect the performance of isolation transmission.

[0003] Therefore, there is a need for improvement in the chip packaging structure of existing wireless transmission devices in terms of external package, circuit connection path, and heat dissipation method. Utility Model Content

[0004] The technical problem to be solved by this utility model is to provide a chip packaging structure for an isolated transmission device and a millimeter-wave isolator. By optimizing the chip packaging structure, it is possible to reduce the packaging volume and cost, shorten the signal connection path, and optimize the heat dissipation method.

[0005] To solve the above-mentioned technical problems, the first technical solution adopted by this utility model is as follows:

[0006] The chip package structure of the isolated transmission device includes an upper insulating layer, a chip insulating layer, and a lower insulating layer stacked sequentially from top to bottom; it also includes a transmitter chip, a receiver chip, a transmitter circuit, a receiver circuit, transmitter signal pins, receiver signal pins, transmitter conductive posts, and receiver conductive posts;

[0007] The transmitting chip and the receiving chip are embedded in the chip insulating layer and respectively lead the signal out to the upper surface of the chip insulating layer; the transmitting circuit and the receiving circuit are disposed on the upper insulating layer; the transmitting end signal pin and the receiving end signal pin are located on the lower insulating layer; the transmitting chip is connected to the transmitting circuit and the transmitting end signal pin through the transmitting end conductive post; the receiving chip is connected to the receiving circuit and the receiving end signal pin through the receiving end conductive post.

[0008] Optionally, the upper insulating layer includes an interlayer insulating layer and an upper surface insulating layer; the chip insulating layer, the interlayer insulating layer, and the upper surface insulating layer are stacked sequentially from bottom to top.

[0009] The transmitting circuit and the receiving circuit are disposed in the upper surface insulating layer; the transmitting circuit is connected to the transmitting chip through the transmitting end conductive post penetrating the upper interlayer insulating layer; the receiving circuit is connected to the receiving chip through the receiving end conductive post penetrating the upper interlayer insulating layer.

[0010] Optionally, the transmitting signal pin and the receiving signal pin are located on the outer surface of the lower insulating layer; the transmitting chip is connected to the transmitting signal pin via transmitting conductive posts that sequentially pass through the upper interlayer insulating layer, the upper surface insulating layer, the upper interlayer insulating layer, the chip insulating layer, the lower interlayer insulating layer, and the lower surface insulating layer; the receiving chip is connected to the receiving signal pin via receiving conductive posts that sequentially pass through the upper interlayer insulating layer, the upper surface insulating layer, the upper interlayer insulating layer, the chip insulating layer, the lower interlayer insulating layer, and the lower surface insulating layer.

[0011] Optionally, the transmitting conductive post includes a first transmitting conductive short post, a second transmitting conductive short post, a transmitting conductive horizontal post, and a transmitting conductive long post; the transmitting chip is connected to the transmitting circuit through the first transmitting conductive short post penetrating the upper interlayer insulating layer; the transmitting chip is connected to the transmitting conductive horizontal post located in the upper surface insulating layer through the second transmitting conductive short post penetrating the upper interlayer insulating layer; the transmitting conductive horizontal post is connected to the transmitting signal pin through the transmitting conductive long post penetrating from the upper interlayer insulating layer to the lower surface insulating layer.

[0012] Optionally, the receiving end conductive post includes a first receiving end conductive short post, a second receiving end conductive short post, a receiving end conductive horizontal post, and a receiving end conductive long post; the receiving chip is connected to the receiving circuit through the first receiving end conductive short post penetrating the upper interlayer insulating layer; the receiving chip is connected to the receiving end conductive horizontal post located in the upper surface insulating layer through the second receiving end conductive short post penetrating the upper interlayer insulating layer; the receiving end conductive horizontal post is also connected to the receiving end signal pin through the receiving end conductive long post penetrating from the upper interlayer insulating layer to the lower surface insulating layer.

[0013] Optionally, it further includes a transmitter heat dissipation device and a receiver heat dissipation device; the transmitter heat dissipation device and the receiver heat dissipation device are disposed in the lower insulating layer; one end of the transmitter heat dissipation device is connected to the transmitter chip, and the other end is connected to the outer surface of the lower insulating layer; one end of the receiver heat dissipation device is connected to the receiver chip, and the other end is connected to the outer surface of the lower insulating layer.

[0014] Optionally, both the transmitter heat dissipation device and the receiver heat dissipation device are comb-shaped heat dissipation structures; the other end of the comb-shaped heat dissipation structure opposite to the comb tooth end is connected to the outer surface of the lower insulating layer.

[0015] Optionally, the upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer; the chip insulating layer, the first upper interlayer insulating layer, the second upper interlayer insulating layer, the third upper interlayer insulating layer, and the upper surface insulating layer are stacked sequentially from bottom to top;

[0016] The transmitting circuit and the receiving circuit are respectively disposed in different insulating layers in the upper insulating layer, and the chip insulating layer, the insulating layer where the transmitting circuit is located, and the insulating layer where the receiving circuit is located are also separated by different insulating layers; the transmitting circuit and the receiving circuit overlap in the stacking direction.

[0017] Optionally, the transmitting circuit is disposed in the second upper interlayer insulating layer, and the receiving circuit is disposed in the upper surface insulating layer.

[0018] The second technical solution adopted in this utility model is:

[0019] Millimeter-wave isolators include the chip package structure of the aforementioned isolation transmission device.

[0020] The beneficial effects of this utility model are as follows: The chip packaging structure provided by this utility model integrates the transmitting / receiving chip inside an insulating material and leads the signal to the surface, connecting it to the external transmitting / receiving circuit and the transmitting / receiving signal pins respectively through the conductive pillars between the layers. On the one hand, since the chip is integrated inside the insulating material, no additional packaging protection is required, which not only shortens the project cycle and reduces costs, but also reduces the overall thickness of the structure. On the other hand, the transmitting / receiving signals in the multi-level structure of this utility model adopt a straight-up-down connection method, which can shorten the signal connection path, thereby reducing power consumption and parasitic parameters to a certain extent. Furthermore, since the multi-level structure of this utility model integrates the chip in the middle layer, a double-sided layout design can be used to place the heat dissipation device and the transmitting / receiving circuit on the upper and lower surfaces of the chip's insulating layer respectively. This not only achieves the integration of the heat dissipation device, further reducing the structural volume, and transferring heat to the outside in a more direct way, thus optimizing the heat dissipation design, but also completely isolates the heat dissipation device from the transmitting / receiving circuit, ensuring that the isolated transmission performance of the signal is not interfered with. Attached Figure Description

[0021] Figure 1 (a)-(c) are schematic diagrams of the chip packaging structure of existing wireless transmission devices;

[0022] Figure 2 A schematic diagram of the hierarchical structure of the chip packaging structure provided in the embodiments of this utility model;

[0023] Figure 3 This is a schematic diagram of the hierarchical structure of the side-transmitter chip packaging structure provided in Embodiment 2 of this utility model;

[0024] Figure 4 This is a schematic diagram of the hierarchical structure of the face-to-face chip packaging structure provided in Embodiment 3 of this utility model;

[0025] Figure 5 Provided for the corresponding embodiment four of this utility model Figure 3 A schematic diagram of the hierarchical structure of chip packaging in high-power applications;

[0026] Figure 6 Provided for the corresponding embodiment four of this utility model Figure 4 A schematic diagram of the hierarchical structure of chip packaging in high-power applications;

[0027] Figure 7 A schematic diagram of the process flow for the chip packaging structure of the isolation transmission device for high-power scenarios provided in Embodiment 5 of this utility model;

[0028] Figure 8A simplified schematic diagram of the isolation transmission device in the millimeter-wave isolator provided in Embodiment Six of this utility model, which adopts the side-transmission chip packaging structure described in Embodiment Two;

[0029] Figure 9 This is a simplified schematic diagram of the isolation transmission device in the millimeter-wave isolator provided in Embodiment Six of this utility model, which adopts the surface-transmission chip packaging structure described in Embodiment Three.

[0030] Label Explanation:

[0031] 100. Upper insulating layer; 200. Chip insulating layer; 300. Lower insulating layer; 123. Insulating material;

[0032] 101. Interlayer insulation layer; 102. Top surface insulation layer;

[0033] 101-1, First upper interlayer insulation layer; 101-2, Second upper interlayer insulation layer; 101-3, Third upper interlayer insulation layer;

[0034] 301. Lower interlayer insulation layer; 302. Lower surface insulation layer;

[0035] 1. Transmitter chip; 2. Receiver chip; 3. Transmitter circuit; 4. Receiver circuit; 5. Transmitter signal pins; 6. Receiver signal pins; 7. Transmitter conductive post; 8. Receiver conductive post; 9. Transmitter heat dissipation device; 10. Receiver heat dissipation device;

[0036] 71. First transmitting end conductive short post; 72. Second transmitting end conductive short post; 73. Transmitting end conductive horizontal post; 74. Transmitting end conductive long post;

[0037] 81. First receiving end conductive short post; 82. Second receiving end conductive short post; 83. Receiving end conductive horizontal post; 84. Receiving end conductive long post. Detailed Implementation

[0038] To illustrate in detail the possible application scenarios, technical principles, implementable specific solutions, and achievable objectives and effects of this utility model, the following detailed description is provided in conjunction with the listed specific embodiments and accompanying drawings. The embodiments described herein are merely illustrative of the technical solutions of this utility model and are therefore intended to limit the scope of protection of this utility model.

[0039] In this document, the term "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The term "embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment, nor does it specifically limit its independence or connection with other embodiments. In principle, in this application, as long as there are no technical contradictions or conflicts, the technical features mentioned in each embodiment can be combined in any way to form corresponding implementable technical solutions.

[0040] Unless otherwise defined, the technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the use of related terms herein is merely for the purpose of describing particular embodiments and is not intended to limit this application.

[0041] In the description of this utility model, the term "and / or" is used to describe the logical relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A exists, B exists, and A and B exist simultaneously. Additionally, the character " / " generally indicates that the preceding and following objects have an "or" logical relationship.

[0042] In this invention, terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any actual quantity, hierarchy, or order between these entities or operations.

[0043] Without further limitations, the use of terms such as “comprising,” “including,” “having,” or other similar expressions in this invention is intended to cover non-exclusive inclusion, which does not exclude the presence of additional elements in a process, method, or product that includes the stated elements, such that a process, method, or product that includes a series of elements may include not only those defined elements but also other elements not expressly listed, or elements inherent to such a process, method, or product.

[0044] Similar to the understanding in the Examination Guidelines, in this utility model, expressions such as "greater than," "less than," and "exceeding" are understood to exclude the stated number; expressions such as "above," "below," and "within" are understood to include the stated number. Furthermore, in the description of the embodiments of this utility model, "multiple" means two or more (including two), and similar expressions related to "multiple" are also understood in this way, such as "multiple groups" and "multiple times," unless otherwise explicitly specified.

[0045] In the description of the embodiments of this utility model, the space-related expressions used, such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "vertical," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," indicate the orientation or positional relationship based on the orientation or positional relationship shown in the specific embodiments or drawings. They are only for the convenience of describing the specific embodiments of this utility model or for the reader's understanding, and do not indicate or imply that the device or component referred to must have a specific position, a specific orientation, or be constructed or operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this utility model.

[0046] Unless otherwise expressly specified or limited, the terms "installation," "connection," "linking," "fixing," and "setting," as used in the description of the embodiments of this utility model, should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two components or the interaction between two components. For those skilled in the art to which this utility model pertains, the specific meaning of the above terms in the embodiments of this utility model can be understood according to the specific circumstances.

[0047] Please refer to Figure 2 Embodiment 1 of this utility model is as follows:

[0048] This embodiment provides a chip packaging structure for an isolated transmission device, such as... Figure 2 As shown, it is a multi-level structure, including an upper insulating layer 100, a chip insulating layer 200 and a lower insulating layer 300 stacked sequentially from top to bottom; it also includes a transmitter chip 1, a receiver chip 2, a transmitter circuit 3, a receiver circuit 4, a transmitter signal pin 5, a receiver signal pin 6, a transmitter conductive post 7 and a receiver conductive post 8.

[0049] In this embodiment, the transmitting chip 1 and the receiving chip 2 are embedded in the chip insulating layer 200 at a certain distance apart, and their respective signals are led out to the upper surface of the chip insulating layer 200 through conductors for subsequent connection with the external transmitting circuit 3 and receiving circuit 4. Optionally, the transmitting chip and the receiving chip can be integrally formed using techniques such as embedding or rewiring. Preferably, the transmitting chip and the receiving chip are at or approximately at the same horizontal level in the chip insulating layer to minimize the thickness of the chip insulating layer. Here, since the chip is placed inside the insulating material, no additional encapsulation protection is required, thus reducing the overall thickness of the structure, shortening the project cycle, and lowering the cost.

[0050] In this embodiment, the transmitting circuit 3 and the receiving circuit 4 are disposed on the upper insulating layer 100; the transmitting signal pin 5 and the receiving signal pin 6 are located on the outer surface of the lower insulating layer 300; the transmitting chip 1 in the chip insulating layer 200 is connected to the transmitting circuit 3 and the transmitting signal pin 5 through the transmitting conductive post 7; the receiving chip 2 is connected to the receiving circuit 4 and the receiving signal pin 6 through the receiving conductive post 8.

[0051] It is understood that the signal connection points led out from the transmitting chip to the upper surface of the chip's insulating layer via conductors include a transmit signal connection point and a ground signal connection point; the transmit signal connection point is connected to the transmitting circuit through a transmitting conductive post; the ground signal connection point is connected to the transmitting signal pin through another transmitting conductive post. Similarly, the signal connection points led out from the receiving chip to the upper surface of the chip's insulating layer via conductors also include a receive signal connection point and a ground signal connection point; the receive signal connection point is connected to the receiving circuit through a receive conductive post; the ground signal connection point is connected to the receiving signal pin through another transmitting conductive post.

[0052] Based on the multi-level structure of this embodiment, the transmitting / receiving conductive posts responsible for signal transmission are straight-line structures, transmitting signals in a linear manner along the horizontal or vertical direction of the hierarchical structure. For example, the ground signal connection point of the transmitting / receiving chip needs to be connected to the transmitting / receiving signal pin in a U-shaped route, sequentially passing through the transmitting / receiving conductive posts of the vertical hierarchical structure, the transmitting / receiving conductive posts of the parallel hierarchical structure, and the transmitting / receiving conductive posts of the vertical hierarchical structure.

[0053] Here, due to the chip packaging structure of this embodiment, the signal adopts a straight-up-down connection method, so the signal connection path will be shortened, which will reduce power consumption to a certain extent and thus reduce parasitic parameters.

[0054] The chip packaging structure for isolated transmission devices provided in this embodiment adopts a multi-level structure, embedding the chip in an insulating material to eliminate the chip packaging step, thereby reducing the overall thickness, shortening the project cycle, and reducing costs. At the same time, in the multi-level structure, the signal is transmitted in a "straight up and down" manner through conductive pillars, which can shorten the signal connection path and reduce parasitic parameters.

[0055] Please refer to Figure 3 Embodiment two of this utility model is as follows:

[0056] This embodiment further extends the above embodiments and provides a chip packaging structure for a side-transmission isolated transmission device.

[0057] In this embodiment, as Figure 3 As shown, the upper insulating layer 100 includes an upper interlayer insulating layer 101 and an upper surface insulating layer 102; the chip insulating layer 200, the upper interlayer insulating layer 101 and the upper surface insulating layer 102 are stacked sequentially from bottom to top.

[0058] The transmitting circuit 3 and the receiving circuit 4 are disposed in the upper surface insulating layer 102. The transmitting circuit 3 and the receiving circuit 4 are located at or approximately at the same horizontal level in the upper surface insulating layer 102. This ensures effective transmission and reception of signals in the horizontal direction and minimizes the thickness of the upper surface insulating layer, thereby reducing the overall thickness.

[0059] The transmitting circuit 3 is connected to the transmitting chip 1 through the transmitting end conductive post 7 that penetrates the upper interlayer insulating layer 101; the receiving circuit 4 is connected to the receiving chip 2 through the receiving end conductive post 8 that penetrates the upper interlayer insulating layer 101.

[0060] The lower insulating layer 300 includes a lower interlayer insulating layer 301 and a lower surface insulating layer 302; the chip insulating layer 200, the lower interlayer insulating layer 301 and the lower surface insulating layer 302 are stacked sequentially from top to bottom;

[0061] The transmitting signal pin 5 and the receiving signal pin 6 are located on the outer surface of the lower interlayer insulating layer 302; the transmitting chip 1 is connected to the transmitting signal pin 5 through the transmitting conductive post 7 that passes sequentially through the upper interlayer insulating layer 101, the upper surface insulating layer 102, the upper interlayer insulating layer 101, the chip insulating layer 200, the lower interlayer insulating layer 301, and the lower surface insulating layer 302; the receiving chip 2 is connected to the receiving signal pin 6 through the receiving conductive post 8 that passes sequentially through the upper interlayer insulating layer 101, the upper surface insulating layer 102, the upper interlayer insulating layer 101, the chip insulating layer 200, the lower interlayer insulating layer 301, and the lower surface insulating layer 302.

[0062] In this embodiment, as Figure 3 As shown, the transmitting circuit 3 and the receiving circuit 4 are located on the same level, and the signal will be transmitted horizontally to achieve lateral transmission of isolated signals. It can be understood that the lateral transmission chip packaging structure can further reduce the thickness of the overall structure, which is more conducive to the thin and light design and application of the isolated transmission device.

[0063] In some specific implementations of this embodiment, such as Figure 3As shown, the transmitting conductive post 7 specifically includes a first transmitting conductive short post 71, a second transmitting conductive short post 72, a transmitting conductive horizontal post 73, and a transmitting conductive long post 74; the transmitting signal connection point of the transmitting chip 1 is connected to the transmitting circuit 3 through the first transmitting conductive short post 71 that penetrates the upper interlayer insulating layer 101; the ground signal connection point of the transmitting chip 1 is first connected to the transmitting conductive horizontal post 73 located in the upper surface insulating layer 101 through the second transmitting conductive short post 72 that penetrates the upper interlayer insulating layer 101, and then connected to the transmitting signal pin 5 through the transmitting conductive long post 74 that penetrates from the upper interlayer insulating layer 101 to the lower surface insulating layer 302.

[0064] Accordingly, in some specific embodiments of this example, such as Figure 3 As shown, the receiving end conductive post 8 includes a first receiving end conductive short post 81, a second receiving end conductive short post 82, a receiving end conductive horizontal post 83, and a receiving end conductive long post 84; the receiving chip 2 is connected to the receiving circuit 4 through the first receiving end conductive short post 81 that penetrates the upper interlayer insulating layer 101; the receiving chip 2 is connected to the receiving end conductive horizontal post 83 located in the upper surface insulating layer 102 through the second receiving end conductive short post 82 that penetrates the upper interlayer insulating layer 101; the receiving end conductive horizontal post 83 is also connected to the receiving end signal pin 6 through the receiving end conductive long post 84 that penetrates from the upper interlayer insulating layer 101 to the lower surface insulating layer 302.

[0065] It is understandable that the aforementioned transmitting / receiving conductive pillars adopt a "straight-line" conductive pillar structure design, enabling the signal to be transmitted in a "straight up and down" manner, which can effectively shorten the signal connection path and thus reduce parasitic parameters.

[0066] Please refer to Figure 4 Embodiment three of this utility model is as follows:

[0067] This embodiment further extends the above embodiments and provides a chip packaging structure for a surface-to-surface isolated transmission device.

[0068] In this embodiment, as Figure 4 As shown, the upper interlayer insulating layer 101 includes a first upper interlayer insulating layer 101-1, a second upper interlayer insulating layer 101-2, and a third upper interlayer insulating layer 101-3; the chip insulating layer 200, the first upper interlayer insulating layer 101-1, the second upper interlayer insulating layer 101-2, the third upper interlayer insulating layer 101-3, and the upper surface insulating layer 102 are stacked sequentially from bottom to top;

[0069] The transmitting circuit 3 and the receiving circuit 4 are respectively disposed in different insulating layers of the upper insulating layer 100, and the chip insulating layer 200, the insulating layer containing the transmitting circuit 3, and the insulating layer containing the receiving circuit 4 are further separated by different insulating layers; the transmitting circuit and the receiving circuit overlap in the stacking direction. That is, the transmitting circuit, the receiving circuit, and the chip insulating layer are all isolated by insulating materials to avoid unnecessary interference and damage, and to contribute to the stability and effective transmission of signals.

[0070] In this embodiment, as Figure 4 As shown, the transmitting circuit 3 and the receiving circuit 4 are located at different levels in the overall hierarchical structure, corresponding to each other as upper and lower layers. Therefore, the signal will be transmitted in the direction perpendicular to the hierarchical structure, achieving face-to-face transmission of isolated signals. It can be understood that the face-to-face chip packaging structure can compress the overall structure length, which is more conducive to the miniaturization design and application of isolated transmission devices.

[0071] In some specific implementations of this embodiment, such as Figure 4 As shown, the transmitting circuit 3 is specifically disposed on the second upper interlayer insulating layer 101-2, and the receiving circuit 4 is disposed on the upper surface insulating layer 102. It can be seen that the chip insulating layer 200 and the transmitting circuit 3 are isolated by the first upper interlayer insulating layer 101-1; the transmitting circuit 3 and the receiving circuit 4 are isolated by the third upper interlayer insulating layer 101-3.

[0072] It is understood that, based on design or scenario requirements and the specific implementation described above, the positions of the transmitting circuit and the receiving circuit can be interchanged in other specific implementations. Specifically, the receiving circuit can be located in the second upper interlayer insulating layer, and the transmitting circuit can be located in the upper surface insulating layer.

[0073] In some specific implementations of this embodiment, such as Figure 4As shown, the transmitting conductive post 7 and the receiving conductive post 8 will adopt the specific structure described in Embodiment 2. Specifically, the transmitting circuit 3 is located in the second upper interlayer insulating layer 101-2, and the receiving circuit 4 is located in the upper surface insulating layer 102. The transmitting chip 1 is connected to the transmitting circuit 3 via a first transmitting conductive post 71 penetrating the first upper interlayer insulating layer 101-1; the receiving chip 2 is connected to the receiving circuit 4 via a first receiving conductive post 81 penetrating the first upper interlayer insulating layer 101-1, the second upper interlayer insulating layer 101-2, and the third upper interlayer insulating layer 101-3. Similarly, the receiving circuit 4 is located in the second upper interlayer insulating layer 101-2, and the transmitting circuit 3 is located in the upper surface insulating layer 102 (not shown in the figure). The receiving chip 2 is connected to the receiving circuit 4 via a first receiving conductive post 81 in the first upper interlayer insulating layer 101-1. The transmitting chip 1 is connected to the transmitting circuit 3 through a first transmitting end conductive short post 71 that simultaneously penetrates the first upper interlayer insulating layer 101-1, the second upper interlayer insulating layer 101-2, and the third upper interlayer insulating layer 101-3.

[0074] Furthermore, in order to shorten the signal transmission path as much as possible, in some specific embodiments of this example, such as Figure 4 As shown, the transmitting conductive horizontal post 73 is specifically disposed in the second upper interlayer insulating layer 101-2. Correspondingly, the transmitting conductive long post 74 extends from the second upper interlayer insulating layer 101-2 to the lower surface insulating layer 302, thus connecting the transmitting conductive horizontal post 73 and the transmitting signal pin 5. Similarly, the receiving conductive horizontal post is also specifically disposed in the second upper interlayer insulating layer. Correspondingly, the receiving conductive long post extends from the second upper interlayer insulating layer to the lower surface insulating layer, thus connecting the receiving conductive horizontal post and the receiving signal pin.

[0075] Please refer to Figure 5 and Figure 6 Embodiment four of this utility model is as follows:

[0076] This embodiment is a further extension of any of the above embodiments. For high-power application scenarios, the heat dissipation performance is improved by optimizing the heat dissipation device design, while the overall layout design is also optimized.

[0077] This embodiment applies to the chip packaging structure in an isolated transmission device for high-power scenarios, and further includes a transmitter heat dissipation device and a receiver heat dissipation device; the transmitter heat dissipation device and the receiver heat dissipation device are disposed in the lower insulating layer; one end of the transmitter heat dissipation device is connected to the transmitter chip, and the other end is connected to the outer surface of the lower insulating layer; one end of the receiver heat dissipation device is connected to the receiver chip, and the other end is connected to the outer surface of the lower insulating layer.

[0078] In some specific implementations of this embodiment, such as Figure 5 and Figure 6 As shown, they correspond to Figure 3 Side-transmitting chip packaging structure and Figure 4 This is a schematic diagram of a surface-mount chip packaging structure with added heat dissipation devices in high-power applications. As can be seen, both the transmitter heat dissipation device 9 and the receiver heat dissipation device 10 are comb-type heat dissipation structures. The comb-type heat dissipation structure has comb teeth connected to the corresponding chip, and the opposite end (which can be understood as the planar end) is connected to the outer surface of the lower insulating layer 300, i.e., the lower surface insulating layer 302. Here, the comb-type heat dissipation structure, with its comb teeth composed of multiple parallel tooth-like tubes, is more conducive to guiding heat transfer from the chip to the heat dissipation device, while the planar end located on the outer surface of the structure, due to its large contact area, is more conducive to heat dissipation. Therefore, designing the transmitter and receiver heat dissipation devices as comb-type heat dissipation structures is beneficial for improving heat dissipation performance.

[0079] In this embodiment, since the chip is embedded in the chip insulating layer, a double-sided layout design is possible. Specifically, signals can be led out from the chip's pad side to the upper surface of the chip insulating layer, while a heat dissipation pattern layout design is implemented on the back side of the chip, i.e., the lower surface of the chip insulating layer, directly transferring heat from the chip to the outside of the package structure. The heat dissipation device layout design used in this embodiment has better heat dissipation performance than traditional methods. Figure 1 (c) shows a significant improvement in heatsink design; and it is isolated from the signal transmission end, ensuring that signal transmission performance is not interfered with, i.e., it does not require... Figure 1 (c) shows that crossing over the transmitting / receiving circuit may interfere with signal transmission; furthermore, custom heat dissipation paths can be customized for different chips to better meet the different needs of high-power application scenarios.

[0080] Please see Figure 7 Embodiment five of this utility model is as follows:

[0081] This embodiment uses the chip packaging structure of the isolated transmission device applied in high-power scenarios, namely Embodiment 4, as an example to provide a general process flow for its fabrication:

[0082] like Figure 7 As shown, firstly, the transmitting chip and the receiving chip are set in an insulating material using techniques such as embedding or rewiring to obtain an integrally formed chip insulating layer; then, an insulating layer is pressed onto the upper and lower surfaces of the chip insulating layer, and then a conductor is pressed onto it; next, circuits and pad patterns are fabricated on the conductors; then, inner layer interconnect conductive pillars are fabricated; next, top and bottom layer interconnect conductive pillars are fabricated; finally, the entire structure is covered with an outer insulating layer.

[0083] It is understandable that the manufacturing process of chip packaging structures applied to low-power scenarios, i.e., chip packaging structures excluding heat dissipation devices, is largely the same as described above. Therefore, the manufacturing process of the chip packaging structure for the isolated transmission device provided above is simple and easy to implement, resulting in a shorter project cycle.

[0084] Please see Figure 8 and Figure 9 Embodiment six of this utility model is as follows:

[0085] This embodiment further extends any of the above embodiments, providing a millimeter-wave isolator, including the chip packaging structure of the isolation transmission device described in any of the above embodiments. Here, the specific structure of the chip packaging structure will not be detailed; please refer to the descriptions in the above embodiments for more information.

[0086] It is understood that the chip packaging structure used in the millimeter-wave isolator of this embodiment has been optimized in three main aspects: package structure, signal connection path, and heat dissipation method. This optimization achieves the goals of reducing the overall thickness of the chip packaging structure, shortening the project cycle and reducing costs, shortening the signal connection path, and reducing parasitic parameters. Furthermore, it optimizes the heat dissipation performance and layout design of the heat dissipation device in high-power scenarios, further reducing the overall size and optimizing isolation transmission performance. Therefore, the cost and project cycle of the millimeter-wave isolator of this embodiment will be reduced, making it more suitable for miniaturized design. More importantly, its isolation transmission performance will be improved, and it will also have greater advantages in high-power applications.

[0087] In some specific implementations of this embodiment, such as Figure 8 As shown, the isolation transmission device in the millimeter-wave isolator adopts the side-transmission chip packaging structure described in Embodiment 2 above.

[0088] In some other specific embodiments of this example, such as Figure 9 As shown, the isolation transmission device in the millimeter-wave isolator adopts the surface-transmission chip packaging structure described in Embodiment 3 above.

[0089] Figure 8 and Figure 9 The transmitting chip and receiving chip in the chip packaging structure shown correspond to the first voltage domain and the second voltage domain, respectively; for example, the first voltage domain is a high voltage domain and the second voltage domain is a low voltage domain, or vice versa; the entire chip is wrapped by insulating material 123 to form an internal isolation transmission device at the chip packaging level.

[0090] The above description is merely an embodiment of this utility model and does not limit the patent scope of this utility model. Any equivalent modifications made based on the content of this utility model specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A chip packaging structure for an isolated transmission device, characterized in that, It includes an upper insulating layer, a chip insulating layer, and a lower insulating layer stacked sequentially from top to bottom; it also includes a transmitter chip, a receiver chip, a transmitter circuit, a receiver circuit, transmitter signal pins, receiver signal pins, transmitter conductive posts, and receiver conductive posts; The transmitting chip and the receiving chip are embedded in the chip insulating layer and respectively lead the signal out to the upper surface of the chip insulating layer; the transmitting circuit and the receiving circuit are disposed on the upper insulating layer; the transmitting end signal pin and the receiving end signal pin are located on the lower insulating layer; the transmitting chip is connected to the transmitting circuit and the transmitting end signal pin through the transmitting end conductive post; the receiving chip is connected to the receiving circuit and the receiving end signal pin through the receiving end conductive post.

2. The chip packaging structure of the isolated transmission device as described in claim 1, characterized in that, The upper insulating layer includes an upper interlayer insulating layer and an upper surface insulating layer; the chip insulating layer, the upper interlayer insulating layer, and the upper surface insulating layer are stacked sequentially from bottom to top; The transmitting circuit and the receiving circuit are disposed in the upper surface insulating layer; The transmitting circuit is connected to the transmitting chip via the transmitting end conductive post that penetrates the upper interlayer insulating layer; the receiving circuit is connected to the receiving chip via the receiving end conductive post that penetrates the upper interlayer insulating layer.

3. The chip packaging structure of the isolated transmission device as described in claim 2, characterized in that, The lower insulating layer includes a lower interlayer insulating layer and a lower surface insulating layer; the chip insulating layer, the lower interlayer insulating layer, and the lower surface insulating layer are stacked sequentially from top to bottom; The transmitting signal pin and the receiving signal pin are located on the outer surface of the lower insulating layer; the transmitting chip is connected to the transmitting signal pin via transmitting conductive posts that sequentially pass through the upper interlayer insulating layer, the upper surface insulating layer, the upper interlayer insulating layer, the chip insulating layer, the lower interlayer insulating layer, and the lower surface insulating layer; the receiving chip is connected to the receiving signal pin via receiving conductive posts that sequentially pass through the upper interlayer insulating layer, the upper surface insulating layer, the upper interlayer insulating layer, the chip insulating layer, the lower interlayer insulating layer, and the lower surface insulating layer.

4. The chip packaging structure of the isolated transmission device as described in claim 3, characterized in that, The transmitting conductive post includes a first transmitting conductive short post, a second transmitting conductive short post, a transmitting conductive horizontal post, and a transmitting conductive long post; the transmitting chip is connected to the transmitting circuit through the first transmitting conductive short post penetrating the upper interlayer insulating layer; the transmitting chip is connected to the transmitting conductive horizontal post located in the upper surface insulating layer through the second transmitting conductive short post penetrating the upper interlayer insulating layer, and the transmitting conductive horizontal post is also connected to the transmitting signal pin through the transmitting conductive long post penetrating from the upper interlayer insulating layer to the lower surface insulating layer.

5. The chip packaging structure of the isolated transmission device as described in claim 3, characterized in that, The receiving end conductive post includes a first receiving end conductive short post, a second receiving end conductive short post, a receiving end conductive horizontal post, and a receiving end conductive long post; the receiving chip is connected to the receiving circuit through the first receiving end conductive short post penetrating the upper interlayer insulating layer; the receiving chip is connected to the receiving end conductive horizontal post located in the upper surface insulating layer through the second receiving end conductive short post penetrating the upper interlayer insulating layer; the receiving end conductive horizontal post is also connected to the receiving end signal pin through the receiving end conductive long post penetrating from the upper interlayer insulating layer to the lower surface insulating layer.

6. The chip packaging structure of the isolated transmission device as described in claim 1, characterized in that, It also includes a transmitter heat dissipation device and a receiver heat dissipation device; the transmitter heat dissipation device and the receiver heat dissipation device are disposed in the lower insulating layer; one end of the transmitter heat dissipation device is connected to the transmitter chip, and the other end is connected to the outer surface of the lower insulating layer; one end of the receiver heat dissipation device is connected to the receiver chip, and the other end is connected to the outer surface of the lower insulating layer.

7. The chip packaging structure of the isolated transmission device as described in claim 6, characterized in that, Both the transmitter heat dissipation device and the receiver heat dissipation device are comb-shaped heat dissipation structures; the other end of the comb-shaped heat dissipation structure opposite to the comb tooth end is connected to the outer surface of the lower insulating layer.

8. The chip packaging structure of the isolated transmission device as described in claim 2, characterized in that, The upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer; the chip insulating layer, the first upper interlayer insulating layer, the second upper interlayer insulating layer, the third upper interlayer insulating layer, and the upper surface insulating layer are stacked sequentially from bottom to top; The transmitting circuit and the receiving circuit are respectively disposed in different insulating layers in the upper insulating layer, and the chip insulating layer, the insulating layer where the transmitting circuit is located, and the insulating layer where the receiving circuit is located are also separated by different insulating layers; the transmitting circuit and the receiving circuit overlap in the stacking direction.

9. The chip packaging structure of the isolated transmission device as described in claim 8, characterized in that, The transmitting circuit is disposed in the second upper interlayer insulating layer, and the receiving circuit is disposed in the upper surface insulating layer.

10. A millimeter-wave isolator, characterized in that, A chip packaging structure including the isolated transmission device as described in any one of claims 1 to 9.

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