Scanning driver and display device

Abstract

The utility model relates to a scan driver and a display device. The display device includes: a plurality of first semiconductor transistors having a first semiconductor layer and a semiconductor pattern; and a plurality of second semiconductor transistors having a second semiconductor layer and a semiconductor pattern. The first electrode layer is located between the first semiconductor layer and the second semiconductor layer, and the second electrode layer is located on the second semiconductor layer. A first transistor among the plurality of second semiconductor transistors includes a first semiconductor pattern in the second semiconductor layer, a bridge pattern in the first electrode layer, and an electrode pattern in the second electrode layer. The first semiconductor pattern includes an etched portion, the electrode pattern connects the first semiconductor pattern and the bridge pattern, and the electrode pattern passes through the etched portion of the first semiconductor pattern and contacts the bridge pattern.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0005417, filed on January 12, 2024, in the Korean Intellectual Property Office, the contents of which are incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The disclosure relates to a scan driver and a display device including the same. BACKGROUND

[0004] With the development of information technology, the importance of display devices as a connecting medium between users and information is being emphasized. In response to this, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

[0005] As the resolution is improved and the number of integrated elements in a display device increases, a technology capable of minimizing dead space becomes necessary. SUMMARY

[0006] The technical problem to be solved by the disclosure is to provide a scan driver capable of minimizing dead space by using a hydrogen gas exhaust port as a contact hole and a display device including the same.

[0007] A display device according to an embodiment can include a plurality of first semiconductor transistors having a first semiconductor layer and a plurality of semiconductor patterns of the plurality of first semiconductor transistors in the first semiconductor layer, and a plurality of second semiconductor transistors having a second semiconductor layer and a plurality of semiconductor patterns of the plurality of second semiconductor transistors in the second semiconductor layer positioned on the first semiconductor layer. A first electrode layer can be positioned between the first semiconductor layer and the second semiconductor layer, a second electrode layer can be positioned on the second semiconductor layer, a first transistor among the plurality of second semiconductor transistors can include a first semiconductor pattern in the second semiconductor layer, a bridge pattern in the first electrode layer, and an electrode pattern in the second electrode layer, the first semiconductor pattern can include an etching portion, the electrode pattern can connect the first semiconductor pattern and the bridge pattern, and the electrode pattern can pass through the etching portion of the first semiconductor pattern and contact the bridge pattern.

[0008] The etching portion can be a notch or an opening.

[0009] The etching portion can be a hydrogen gas exhaust port.

[0010] The first semiconductor pattern can include a first electrode of the first transistor, and the electrode pattern can contact the first electrode of the first transistor.

[0011] The bridge pattern can be connected to electrodes of transistors other than the first transistor among the plurality of first semiconductor transistors and the plurality of second semiconductor transistors.

[0012] The first semiconductor pattern can include a first electrode of the first transistor, the first electrode of the first transistor can include a plurality of first sub-electrodes spaced apart from each other, the electrode pattern can include a plurality of sub-electrode patterns spaced apart from each other, the plurality of sub-electrode patterns can contact the corresponding plurality of first sub-electrodes, and the bridge pattern can connect the plurality of sub-electrode patterns.

[0013] The bridge pattern can be a scan line connecting a pixel of the display device and a scan driver.

[0014] The bridge pattern can be an emission line connecting a pixel of the display device and an emission driver.

[0015] A scan driver according to an embodiment can include a plurality of stages. Each of the plurality of stages can include a plurality of first semiconductor transistors having a first semiconductor layer and a plurality of semiconductor patterns of the plurality of first semiconductor transistors positioned in the first semiconductor layer, and a plurality of second semiconductor transistors having a second semiconductor layer and a plurality of semiconductor patterns of the plurality of second semiconductor transistors positioned in the second semiconductor layer positioned on the first semiconductor layer. A first electrode layer can be positioned between the first semiconductor layer and the second semiconductor layer, a second electrode layer can be positioned on the second semiconductor layer, a first transistor among the plurality of second semiconductor transistors can include a first semiconductor pattern positioned in the second semiconductor layer, a bridge pattern positioned in the first electrode layer, and an electrode pattern positioned in the second electrode layer, the first semiconductor pattern can include an etching portion, the electrode pattern can connect the first semiconductor pattern and the bridge pattern, and the electrode pattern can pass through the etching portion of the first semiconductor pattern and contact the bridge pattern.

[0016] The etching portion can be a notch or an opening.

[0017] The etching portion can be a hydrogen gas exhaust.

[0018] The first semiconductor pattern can include a first electrode of the first transistor, and the electrode pattern can contact the first electrode of the first transistor.

[0019] The bridge pattern can be connected to electrodes of transistors other than the first transistor.

[0020] The second electrode of the first transistor can receive a scan start signal or a scan signal of a previous stage.

[0021] The first semiconductor pattern can include a first electrode of a first transistor, the first electrode of the first transistor can include a plurality of first sub-electrodes spaced apart from each other, the electrode pattern can include a plurality of sub-electrode patterns spaced apart from each other, the plurality of sub-electrode patterns can contact the corresponding plurality of first sub-electrodes, and the bridge pattern can connect the plurality of sub-electrode patterns.

[0022] The first electrode of the first transistor can be connected to a gate electrode of at least one of the plurality of first semiconductor transistors.

[0023] The first electrode of the first transistor can also be connected to a gate electrode of at least one of the plurality of second semiconductor transistors.

[0024] The bridge pattern can be a scan line.

[0025] The first transistor can be connected to at least one of the plurality of first semiconductor transistors.

[0026] The first transistor can be connected to at least one of the plurality of first semiconductor transistors through the electrode pattern. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings, which are included to provide a further understanding of the present inventive concept and are incorporated in and constitute a part of this specification, illustrate embodiments of the present inventive concept and together with the description serve to explain the principles of the present inventive concept.

[0028] Figure 1 FIG. 1 is a schematic diagram for explaining a display device according to an embodiment.

[0029] Figure 2 FIG. 2 is a schematic diagram for explaining a pixel according to an embodiment.

[0030] Figure 3 FIG. 3 is a schematic diagram for explaining a method of changing a display frequency according to an embodiment.

[0031] Figure 4 FIG. 4 is a schematic diagram for explaining a first scan period according to an embodiment.

[0032] Figure 5 FIG. 5 is a schematic diagram for explaining a second scan period according to an embodiment.

[0033] Figure 6 FIG. 6 is a schematic diagram for explaining a scan driver according to an embodiment.

[0034] Figure 7 FIG. 7 is a schematic diagram for explaining a stage according to an embodiment.

[0035] Figure 8 FIG. 8 is a schematic diagram for explaining a driving Figure 7schematic diagram of an example of the method of the stage.

[0036] Figure 9 is a schematic diagram for explaining a stack structure of a scan driver according to an embodiment.

[0037] Figures 10 to 16 is a schematic diagram for explaining a planar layout of a stage according to an embodiment.

[0038] Figure 17 is a reference schematic diagram showing all layers shown in Figures 10 to 16 overlapping each other.

[0039] Figure 18 is a schematic cross-sectional view taken along line I-I' in Figures 10 to 17

[0040] Figure 19 is a schematic cross-sectional view taken along line II-II' in Figures 10 to 17

[0041] Figure 20 is a schematic cross-sectional view taken along line III-III' in Figures 10 to 17 DETAILED DESCRIPTION

[0042] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art can easily practice the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the embodiments described herein.

[0043] In order to clearly describe the present disclosure, portions unrelated to the description are omitted, and throughout the specification, the same or similar components are denoted by the same reference numerals. Accordingly, the above-described reference numerals can also be used in other drawings.

[0044] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable terms that are non-limiting examples of employing the apparatus or method disclosed herein. It will be apparent, however, that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In this document, various embodiments can not necessarily be mutually exclusive, nor must they necessarily be practiced in isolation. For example, specific shapes, configurations, and characteristics of an embodiment can be used or implemented in another embodiment.

[0045] ​​​Unless otherwise stated, the embodiments shown are to be understood as providing illustrative features of the present invention. Thus, unless otherwise stated, the features, components, modules, layers, films, panels, regions, and / or aspects of various embodiments (hereinafter, individually or collectively referred to as “elements”) can be additionally combined, separated, interchanged, and / or rearranged, without departing from the present inventive concept.

[0046] The use of cross-hatching and / or shading in the drawings is generally provided to make the boundaries and regions of the elements being depicted more clearly for ease of understanding. As such, unless otherwise noted, the presence of cross-hatching or shading in a drawing generally shall not be construed to indicate or imply materal, material properties, dimensions, proportions, commonality between elements, and / or any other characteristic, attribute, property, or the like of the elements being portrayed, unless such attributes or properties are specifically described. Additionally, in the drawings, the size and relative sizes of elements can be exaggerated for clarity and / or descriptive purposes. When embodiments can be practiced differently, a specific processing sequence can be performed in an order other than the described one. For example, two consecutively described processes can be performed at substantially the same time or in the reverse order of the described one. Moreover, like drawing reference numerals (and / or reference designators) can denote like elements.

[0047] When an element such as a layer, region, or substrate is referred to as being “on” another element, or “connected” or “coupled” to another element, it can be directly on the other element or coupled to the other element, or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly connected” or “directly coupled” to another element, there are no intervening elements present. In this context, the term “connected” can refer to physical or electrical and / or fluid connection, with or without intervening elements. In addition, the X-axis, Y-axis and Z-axis do not limit the three axes of a rectangular coordinate system, such as the x-axis, y-axis and z-axis, and can be interpreted in a wider sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, “at least one of A and B” can be interpreted to mean only A, only B, or any combination of A and B. In addition, “at least one of X, Y and Z” and “at least one selected from the group consisting of X, Y and Z” can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a "first" element discussed below could be termed a "second" element without departing from the teachings of the present disclosure.

[0049] Spatially relative terms, such as "under," "below," "lower," "above," "upper," "on," "directly on," "side" (e.g., as in "side wall"), and the like, can be used herein for descriptive purposes, e.g., relative to the position of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. Moreover, the device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including," "includes," "containing," "contains," or "containing," are used, for example, in the description and the claims, such terms are intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional term in the patent claims. It is also noted that the terms "substantial," "approximately," and other similar terms are used as terms of approximation and not as terms of degree, unless otherwise indicated, and accordingly, such terms are utilized to account for inherent deviations in measurements, calculations and / or other sources of variations.

[0051] Various embodiments are described herein with reference to cross-sectional / exploded illustrations of schematic diagrams / views of examples and / or intermediate structures as part of the overall process flow. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments disclosed herein are not to be construed as being limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. In this manner, regions illustrated in the figures can in some examples be schematic in nature and / or can not have shapes that actually appear in and / or on the devices themselves. The same can be said concerning the relative sizing of regions illustrated in the figures.

[0052] The dimensions and the proportions of each component shown in the drawings are arbitrarily shown for ease of description and, as such, the present disclosure is not necessarily limited to those shown in the drawings. In the drawings, thicknesses can be exaggerated to clearly illustrate layers and regions.

[0053] In the description, the expression "same" can mean "substantially the same". For example, this can be sufficiently the same to convince one of ordinary skill in the art that it is the same. In other expressions, "substantially" can be omitted.

[0054] The term "dead space" as used herein can refer to an area or region that cannot be used for active components because of, for example, design considerations.

[0055] Unless otherwise defined or implied, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the specification.

[0056] Figure 1 is a schematic diagram for explaining a display device according to an embodiment.

[0057] Referring to Figure 1 , a display device 10 according to an embodiment can include a timing controller 11, a data driver 12, a scan driver 13, a pixel unit 14, and an emission driver 15.

[0058] The timing controller 11 can receive a gray scale level for an input image or an input frame. The gray scale level can include a first color gray scale level, a second color gray scale level, and a third color gray scale level. The first color gray scale level can be a gray scale level for expressing a first color, the second color gray scale level can be a gray scale level for expressing a second color, and the third color gray scale level can be a gray scale level for expressing a third color.

[0059] The timing controller 11 can receive a control signal for an image. The control signal can include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a data enable signal. The vertical synchronization signal can include a pulse, and can indicate that a previous frame period ends and a current frame period starts based on a time point in case each pulse is generated. An interval between adjacent pulses of the vertical synchronization signal can correspond to one frame period. The horizontal synchronization signal can include a pulse, and can indicate that a previous horizontal period ends and a new horizontal period starts based on a time point in case each pulse is generated. An interval between adjacent pulses of the horizontal synchronization signal can correspond to one horizontal period. The data enable signal can have an enable level for a certain horizontal period and a disable level for the remaining periods. In case the data enable signal is at the enable level, it can indicate that color gray scales are supplied in the corresponding horizontal period.

[0060] The timing controller 11 can provide gray scales, which are rendered or corrected to satisfy the specifications of the display device 10, to the data driver 12. The timing controller 11 can provide a clock signal and a scan start signal, etc. to the scan driver 13. The timing controller 11 can provide a clock signal and an emission stop signal, etc. to the emission driver 15.

[0061] The data driver 12 can generate data voltages to be provided to the data lines DL1, …, DLj, …, and DLq using the gray scales and the control signal received from the timing controller 11. For example, the data driver 12 can sample the gray scales using the clock signal, and apply data voltages corresponding to the gray scales to the data lines in units of pixels. Herein, q can be an integer greater than or equal to 1, and j can be an integer greater than 0 and less than or equal to q.

[0062] The scan driver 13 can include a first scan driver 13GW, a second scan driver 13GB, a third scan driver 13GI, and a fourth scan driver 13GC. The first scan driver 13GW can provide a first scan signal to the first scan lines GW1, …, GWi, …, and GWp. Herein, p can be an integer greater than or equal to 1, and i can be an integer greater than 0 and less than or equal to p. The second scan driver 13GB can provide a second scan signal to the second scan lines GB1, …, GBi, …, and GBp. The third scan driver 13GI can provide a third scan signal to the third scan lines GI1, …, GIi, …, and GIp. The fourth scan driver 13GC can provide a fourth scan signal to the fourth scan lines GC1, …, GCi, …, and GCp.

[0063] For example, the first scan driver 13GW can receive at least one scan clock signal and a scan start signal from the timing controller 11 to generate a first scan signal to be supplied to the first scan lines GW1 to GWp. The first scan driver 13GW can sequentially supply the first scan signal having an on-level pulse to the first scan lines GW1 to GWp. For example, the first scan driver 13GW can be configured in the form of a shift register. The first scan driver 13GW can generate the first scan signal by sequentially transmitting the scan start signal in the form of an on-level pulse to the next scan stage under the control of the scan clock signal.

[0064] Since each of the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC can be configured similarly to the first scan driver 13GW, a repeated description will be omitted. According to an embodiment, at least some of the first scan driver 13GW, the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC can be integrated. For example, two or more scan drivers can be integrated in the case where the polarities and widths of the pulses are the same. Referring to FIG. 1, the first scan driver 13GW, the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC can be integrated into one scan driver 13. Figure 4 Since the on-level pulse applied to the third scan line GIi at the time point t2a and the on-level pulse applied to the fourth scan line GCi at the time point t3a have the same polarity and width, the third scan driver 13GI and the fourth scan driver 13GC can be integrated.

[0065] The emission driver 15 can receive at least one emission clock signal and an emission stop signal from the timing controller 11 to generate an emission signal to be supplied to the emission lines EM1, …, EMi, …, and EMp. The emission driver 15 can sequentially supply the emission signal having an off-level pulse to the emission lines EM1 to EMp. For example, the emission driver 15 can be configured in the form of a shift register. The emission driver 15 can generate the emission signal by sequentially transmitting the emission stop signal in the form of an off-level pulse to the next emission stage under the control of the emission clock signal.

[0066] In Figure 1In the present embodiment, the number of each of the first scan lines GW1 to GWp, the second scan lines GB1 to GBp, the third scan lines GI1 to GIp, the fourth scan lines GC1 to GCp, and the emission lines EM1 to EMp is shown as p. However, in another embodiment, the number of at least one of the second scan lines GB1 to GBp, the third scan lines GI1 to GIp, the fourth scan lines GC1 to GCp, and the emission lines EM1 to EMp can be p / 2 or less. For example, two adjacent pixel rows can share one second scan line. Similarly, two adjacent pixel rows can share one third scan line, one fourth scan line, or one emission line. The same pixel row can refer to pixels connected to the same first scan line. Hereinafter, for the convenience of description, a case where the number of each of the first scan lines GW1 to GWp, the second scan lines GB1 to GBp, the third scan lines GI1 to GIp, the fourth scan lines GC1 to GCp, and the emission lines EM1 to EMp is p will be described as an example.

[0067] The pixel unit 14 can include pixels. Each pixel PXij can be connected to a corresponding data line DLj, a corresponding scan line GWi, GBi, GIi, and GCi, and a corresponding emission line EMi. The pixel unit 14 can include a first pixel that emits light of a first color, a second pixel that emits light of a second color, and a third pixel that emits light of a third color. The first color, the second color, and the third color can be different colors. For example, the first color can be one of red, green, and blue. The second color can be one of red, green, and blue other than the first color. The third color can be one of red, green, and blue other than the first color and the second color. Instead of red, green, and blue, magenta, cyan, and yellow can be used as the first color to the third color.

[0068] The pixel unit 14 can have various arrangements, such as a diamond RGB stripe, S stripe, real RGB, or normal and the like.

[0069] Figure 2 is a schematic diagram for explaining a pixel according to an embodiment.

[0070] Referring to Figure 2 The pixel PXij can include a pixel circuit PXC and a light emitting element LD. The pixel circuit PXC can include transistors T1, T2, T3, T4, T5, T6, T7, and T8, a storage capacitor Cst, and a holding capacitor Chold. According to an embodiment, the holding capacitor Chold and the eighth transistor T8 can be omitted.

[0071] The pixel PXij can be in an i-th pixel row and a j-th pixel column. The pixel PXij can be a first pixel for expressing a first color. Since a second pixel for expressing a second color and a third pixel for expressing a third color can also be configured to be the same as the first pixel, a repeated description will be omitted.

[0072] In this embodiment, the P-type transistor can be a polysilicon semiconductor transistor. In the polysilicon semiconductor transistor, a channel of an active layer can include a polysilicon semiconductor. For example, the polysilicon semiconductor transistor can be a low temperature polysilicon (LTPS) thin film transistor. The polysilicon semiconductor transistor can have a high electron mobility, and thus can have a fast driving characteristic.

[0073] In this embodiment, the N-type transistor can be an oxide semiconductor transistor. In the oxide semiconductor transistor, a channel of an active layer can include an oxide semiconductor. For example, the oxide semiconductor transistor can be a low temperature polysilicon oxide (LTPO) thin film transistor. The oxide semiconductor transistor can have a lower charge mobility than the polysilicon semiconductor transistor. Thus, an amount of a leakage current generated in a case where the oxide semiconductor transistor is off can be less than an amount of a leakage current of the polysilicon semiconductor transistor.

[0074] The first transistor T1 can have a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first transistor T1 can be a driving transistor. The first transistor T1 can be a P-type transistor.

[0075] The second transistor T2 can have a gate electrode connected to the first scan line GWi, a first electrode connected to the data line DLj, and a second electrode connected to the second node N2. The second transistor T2 can be a scan transistor. The second transistor T2 can be a P-type transistor.

[0076] The third transistor T3 can have a gate electrode connected to the fourth scan line GCi, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 can be a transistor connected in a diode form. The third transistor T3 can be an N-type transistor.

[0077] The fourth transistor T4 can have a gate electrode connected to the third scan line GIi, a first electrode connected to the first node N1, and a second electrode receiving the first initialization voltage VINT. The fourth transistor T4 can be a gate initialization transistor. The fourth transistor T4 can be an N-type transistor.

[0078] The fifth transistor T5 can have a gate electrode connected to the emission line EMi, a first electrode receiving the first power supply voltage ELVDD, and a second electrode connected to the second node N2. The fifth transistor T5 can be a first emission control transistor. The fifth transistor T5 can be a P-type transistor.

[0079] The sixth transistor T6 can have a gate electrode connected to the emission line EMi, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The sixth transistor T6 can be a second emission control transistor. The sixth transistor T6 can be a P-type transistor.

[0080] The seventh transistor T7 can have a gate electrode connected to the second scan line GBi, a first electrode receiving the second initialization voltage VAINT, and a second electrode connected to the fourth node N4. The seventh transistor T7 can be an anode initialization transistor. The seventh transistor T7 can be a P-type transistor.

[0081] The eighth transistor T8 can have a gate electrode connected to the second scan line GBi, a first electrode receiving the bias voltage VOBS, and a second electrode connected to the second node N2. The eighth transistor T8 can be a P-type transistor.

[0082] The storage capacitor Cst can have a first electrode receiving the first power supply voltage ELVDD and a second electrode connected to the first node N1.

[0083] The hold capacitor Chold can have a first electrode receiving the first power supply voltage ELVDD and a second electrode connected to the second node N2.

[0084] The light emitting element LD can have an anode connected to the fourth node N4 and a cathode receiving the second power supply voltage ELVSS. The light emitting element LD can emit light of one of a first color, a second color, and a third color. The light emitting element LD can be a light emitting diode. The light emitting element LD can be composed of an organic light emitting diode, an inorganic light emitting diode, or a quantum dot / well light emitting diode, etc. In the present embodiment, each pixel is provided with a single light emitting element LD. However, in another embodiment, each pixel can be provided with a plurality of light emitting elements. The plurality of light emitting elements can be connected in series, in parallel, or in series-parallel.

[0085] Figure 3 is a schematic diagram for explaining a method of changing a display frequency according to an embodiment.

[0086] Referring to Figure 3 , also referring to Figure 1 , the display apparatus 10 can change a display frequency using a first scan period DISPLAY SCAN and a second scan period SELF SCAN.

[0087] The first scan period DISPLAY SCAN can be a period in which the pixels of the pixel units 14 receive data voltages. Therefore, in a case where a new first scan period DISPLAY SCAN starts, the image frame displayed by the pixel units 14 can change. Therefore, the cycle period of the first scan period DISPLAY SCAN can be the same as the display frequency. For example, during the first scan period DISPLAY SCAN, the first scan driver 13GW, the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC can transmit the scan signals at the on level. For example, during the first scan period DISPLAY SCAN, the emission driver 15 can transmit the emission signal at the off level to overlap with the first scan signal at the on level (see Figure 4 ).

[0088] The second scan period SELF SCAN can be a period in which the pixels of the pixel units 14 do not receive data voltages. For example, during the second scan period SELF SCAN, the first scan driver 13GW, the third scan driver 13GI, and the fourth scan driver 13GC can hold the scan signals at the off level. During the second scan period SELF SCAN, the second scan driver 13GB can transmit the second scan signal at the on level, and the emission driver 15 can transmit the emission signal at the off level (see Figure 5 ).

[0089] Figure 3 An example in which one first scan period DISPLAY SCAN is about 1 / 120 seconds is shown. If the first scan period DISPLAY SCAN is repeated without the second scan period SELF SCAN, the display device 10 can display an image at a display frequency of about 120 Hz. As the number of the second scan periods SELF SCAN located between the adjacent first scan periods DISPLAY SCAN increases, the display frequency can decrease.

[0090] Figure 4 is a schematic diagram for explaining the first scan period according to the embodiment. The description will be made with reference to the pixel PXij of Figure 2 . Figure 4 .

[0091] At the time point t1a, in a case where the emission signal at the off level (high level) is applied to the emission line EMi, the fifth transistor T5 and the sixth transistor T6 can be turned off, and the pixel PXij can be in a non-emitting state.

[0092] At the time point t2a, the fourth transistor T4 can be turned on in a case where the third scan signal at the on level (high level) is applied to the third scan line GIi. Accordingly, the first initialization voltage VINT can be applied to the first node N1. The first initialization voltage VINT can be a sufficiently low voltage capable of biasing the first transistor T1 to be turned on.

[0093] At the time point t3a, the third transistor T3 can be turned on in a case where the fourth scan signal at the on level (high level) is applied to the fourth scan line GCi. Accordingly, the first transistor T1 can be in a diode-connected state in which the drain electrode and the gate electrode are connected.

[0094] At the time point t4a, the second transistor T2 can be turned on in a case where the scan signal at the on level (low level) is applied to the first scan line GWi. Accordingly, the data voltage of the data line DLj can be applied to the first node N1 through the turned-on second transistor T2, the first transistor T1, and the third transistor T3. The voltage of the first node N1 can be a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage. The storage capacitor Cst can maintain a voltage difference between the first power supply voltage ELVDD and the compensation voltage.

[0095] At the time point t5a, the seventh transistor T7 and the eighth transistor T8 can be turned on in a case where the scan signal at the on level (low level) is applied to the second scan line GBi. When the seventh transistor T7 is turned on, the second initialization voltage VAINT can be applied to the anode of the light emitting element LD, and the light emitting element LD can be initialized with a charge amount corresponding to a voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. Accordingly, low gray scale expression can be facilitated in the light emitting element LD.

[0096] When the eighth transistor T8 is turned on, the voltage of the second node N2 can be set to the bias voltage VOBS. Accordingly, the bias voltage VOBS, instead of the data voltage of the previous frame period, can be applied to the source electrode of the first transistor T1. Accordingly, a hysteresis phenomenon can be prevented, and an on bias state can be guaranteed.

[0097] At the time point t6a, the fifth transistor T5 and the sixth transistor T6 can be turned on in a case where the emission signal at the on level (low level) is applied to the emission line EMi. Accordingly, a path for a driving current to flow from the first power supply voltage ELVDD to the second power supply voltage ELVSS via the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light emitting element LD can be formed.

[0098] The amount of the drive current can be adjusted according to the voltage held in the storage capacitor Cst. The light emitting element LD can emit light having a luminance corresponding to the amount of the drive current. The light emitting element LD can emit light until the emission signal at the cutoff level is applied to the emission line EMi.

[0099] Figure 5 is a schematic diagram for explaining a second scan period according to an embodiment. The operation of the pixel PXij will be described with reference to Figure 2 . Figure 5 .

[0100] At the time point t7a, in a case where the emission signal at the cutoff level (high level) is applied to the emission line EMi, the fifth transistor T5 and the sixth transistor T6 can be turned off, and the pixel PXij can be in a non-light emitting state.

[0101] During the time points t7a to t8a, the scan signal at the cutoff level can be held in the first scan line GWi, the third scan line GIi, and the fourth scan line GCi. Accordingly, the voltage of the first node N1 can not change.

[0102] At the time point t8a, in a case where the scan signal at the on level (low level) is applied to the second scan line GBi, the seventh transistor T7 and the eighth transistor T8 can be turned on. When the seventh transistor T7 is turned on, the second initialization voltage VAINT can be applied to the anode of the light emitting element LD, and the light emitting element LD can be initialized with a charge amount corresponding to a voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. Accordingly, low gray scale expression can be promoted in the light emitting element LD.

[0103] When the eighth transistor T8 is turned on, the voltage of the second node N2 can be set to the bias voltage VOBS. Accordingly, the bias voltage VOBS, instead of the data voltage of the previous frame period, can be applied to the source electrode of the first transistor T1. Accordingly, a hysteresis phenomenon can be prevented, and an on bias state can be guaranteed.

[0104] At the time point t9a, in a case where the emission signal at the on level (low level) is applied to the emission line EMi, the fifth transistor T5 and the sixth transistor T6 can be turned on. Accordingly, a path for the drive current to flow from the first power supply voltage ELVDD to the second power supply voltage ELVSS via the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light emitting element LD can be formed.

[0105] The amount of the drive current can be adjusted according to the voltage held in the storage capacitor Cst. The voltage of the first node N1 recorded during the first scan period DISPLAY SCAN can be held during the second scan period SELF SCAN. Thus, the image frame displayed by the pixel unit 14 during the second scan period SELF SCAN can be the same as the image frame displayed by the pixel unit 14 during the first scan period DISPLAY SCAN.

[0106] Figure 6 is a schematic diagram for explaining the scan driver according to an embodiment.

[0107] Referring to Figure 6 , the scan driver 13S according to an embodiment can include stages STG1, STG2, STG3, STG4, STG5,....

[0108] For example, referring also to Figure 1 , the scan driver 13S can be a third scan driver 13GI or a fourth scan driver 13GC. Hereinafter, the scan driver 13S will be described, but the emission driver 15 can also have the same structure. Referring to Figure 4 , it can be seen that the pulse waveforms applied to the third scan lines GIi, the fourth scan lines GCi, and the emission lines EMi are similar to each other. The length of the pulses can be adjusted by the pulse length of the scan start signal FLM. For example, all of the following embodiments can be equally applied to the emission driver 15.

[0109] If Figure 8 the voltage level of the scan start signal FLM is inverted, the voltage level of the scan signal at the output terminal OUT can also be inverted. Thus, the scan driver 13S can function as a first scan driver 13GW or a second scan driver 13GB.

[0110] Each of the plurality of stages STG1, STG2, STG3, STG4, STG5,.... can include a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, an output terminal OUT, and a voltage input terminal. The plurality of stages STG1, STG2, STG3, STG4, STG5,.... can commonly receive a first low voltage VGL1, a second low voltage VGL2, a high voltage VGH, and a reset signal ESR.

[0111] In the odd-numbered stages STG1, STG3, STG5,...., the first input terminal IN1 can receive a first clock signal CK1, and the second input terminal IN2 can receive a second clock signal CK2.

[0112] In the even-numbered stages STG2, STG4,..., the first input terminal IN1 can receive the second clock signal CK2, and the second input terminal IN2 can receive the first clock signal CK1.

[0113] The output terminal OUT of the stage STG1 to STG5,... can be connected to the corresponding scan line SL1, SL2, SL3, SL4, SL5,.... The stages STG1 to STG5,... can sequentially supply the on-level scan signal to the scan lines SL1 to SL5,....

[0114] The third input terminal IN3 of the stage STG2 to STG5,... can be connected to the output terminal OUT of the previous stage. However, the third input terminal IN3 of the first stage STG1 can receive the scan start signal FLM.

[0115] Figure 7 is a schematic diagram for explaining the stage according to the embodiment.

[0116] Referring to Figure 7 The stage STG1 according to the embodiment can include transistors ST1, ST2, ST3, ST4, ST5, ST6, and ST7, and a capacitor C1.

[0117] The transistors ST1, ST2, ST3, and ST4 can be P-type transistors. The transistors ST1, ST2, ST3, and ST4 can be polysilicon semiconductor transistors. The transistors ST5, ST6, and ST7 can be N-type transistors. The transistors ST5, ST6, and ST7 can be oxide semiconductor transistors.

[0118] The gate electrode of the first transistor ST1 can be connected to the second input terminal IN2 to receive the second clock signal CK2. The first electrode of the first transistor ST1 can be connected to the third input terminal IN3 to receive the scan start signal FLM. The second electrode of the first transistor ST1 can be connected to a node AN.

[0119] The second transistor ST2 can have a gate electrode connected to the node AN, a first electrode receiving a high voltage VGH, and a second electrode connected to a node BN.

[0120] The third transistor ST3 can have a gate electrode connected to the node BN, a first electrode receiving the high voltage VGH, and a second electrode connected to the output terminal OUT.

[0121] The fourth transistor ST4 can have a gate electrode receiving a reset signal ESR, a first electrode receiving the high voltage VGH, and a second electrode connected to the node AN. The fourth transistor ST4 can be turned on in a case where the node AN needs to be reset to the high voltage VGH.

[0122] The gate electrode of the fifth transistor ST5 can be connected to the first input terminal IN1 to receive the first clock signal CK1. The first electrode of the fifth transistor ST5 can be connected to the node AN, and the second electrode of the fifth transistor ST5 can be connected to the third input terminal IN3 to receive the scan start signal FLM.

[0123] The sixth transistor ST6 can have a gate electrode connected to the node AN, a first electrode connected to the node BN, and a second electrode receiving the first low voltage VGL1.

[0124] The seventh transistor ST7 can have a gate electrode connected to the node BN, a first electrode connected to the output terminal OUT, and a second electrode receiving the first low voltage VGL1.

[0125] The back gate electrodes of the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 can receive the second low voltage VGL2. The voltage level of the second low voltage VGL2 can be lower than the voltage level of the first low voltage VGL1. This can adjust the threshold voltage of the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7, and can vary according to embodiments. For example, the back gate electrode of each of the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 can be connected to its own gate electrode. The supply of the second low voltage VGL2 can be omitted.

[0126] The capacitor C1 can have a first electrode receiving the high voltage VGH and a second electrode connected to the node AN. According to embodiments, the capacitor C1 can be omitted in case the parasitic capacitance of the second transistor ST2 and the sixth transistor ST6 is large enough.

[0127] Figure 8 is a schematic diagram for explaining an example of a method of driving Figure 7 a stage.

[0128] In embodiments, the phase of the second clock signal CK2 can be different from the phase of the first clock signal CK1. For example, the phase of the second clock signal CK2 can have a difference of about 180 degrees from the phase of the first clock signal CK1. In another embodiment, the second clock signal CK2 can be an inverted phase of the first clock signal CK1.

[0129] Referring to Figure 8 , also referring to Figure 7 , at the time point t1b, the scan start signal FLM of the on level (high level) can be supplied. The fifth transistor ST5 can be turned off by the first clock signal CK1 of the low level, and the first transistor ST1 can be turned off by the second clock signal CK2 of the high level. Accordingly, the voltage level of the node AN can be maintained at the low level.

[0130] At time point t2b, the fifth transistor ST5 can be turned on by the high-level first clock signal CK1, and the first transistor ST1 can be turned on by the low-level second clock signal CK2. Accordingly, the scan start signal FLM of the on level can be applied to the node AN, and the voltage level of the node AN can rise to the high level.

[0131] When the voltage level of the node AN becomes the high level, the sixth transistor ST6 can be turned on. Accordingly, the first low voltage VGL1 can be applied to the node BN. Accordingly, the voltage level of the node BN can fall to the low level.

[0132] When the voltage level of the node BN becomes the low level, the third transistor ST3 can be turned on. Accordingly, the high voltage VGH can be applied to the output terminal OUT, and the scan signal of the on level (high level) can be output through the output terminal OUT.

[0133] At time point t3b, the fifth transistor ST5 can be turned on by the high-level first clock signal CK1, and the first transistor ST1 can be turned on by the low-level second clock signal CK2. Accordingly, the scan start signal FLM of the off level (low level) can be applied to the node AN, and the voltage level of the node AN can fall to the low level.

[0134] When the voltage level of the node AN becomes the low level, the second transistor ST2 can be turned on. Accordingly, the high voltage VGH can be applied to the node BN. Accordingly, the voltage level of the node BN can rise to the high level.

[0135] When the voltage level of the node BN becomes the high level, the seventh transistor ST7 can be turned on. Accordingly, the first low voltage VGL1 can be applied to the output terminal OUT, and the scan signal of the off level (low level) can be output through the output terminal OUT.

[0136] Figure 9 FIG. 1 is a schematic diagram for explaining a stack structure of a scan driver according to an embodiment.

[0137] The first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other. The first direction DR1 and the second direction DR2 can indicate planar directions, and the third direction DR3 can indicate a height direction.

[0138] Referring to Figure 9The scan driver 13S may have a structure in which the substrate SUB, the first insulating layer INL1, the first active layer ACL1, the second insulating layer INL2, the first electrode layer CEL1, the third insulating layer INL3, the second electrode layer CEL2, the fourth insulating layer INL4, the second active layer ACL2, the fifth insulating layer INL5, the third electrode layer CEL3, the sixth insulating layer INL6, the fourth electrode layer CEL4, the seventh insulating layer INL7, and the fifth electrode layer CEL5 are stacked sequentially.

[0139] Figure 9 The stacked structure can also be applied to pixel unit 14 (see Figure 1 For example, pixel unit 14 and scan driver 13S can be fabricated simultaneously on a single substrate SUB. For example, pixel unit 14 and scan driver 13S can share an electrode layer and an insulating layer. Figure 2 The P-type transistors T1, T2, T5, T6, T7, and T8 of the pixel circuit PXC can be composed of a polysilicon semiconductor transistor TR1 (also known as the first semiconductor transistor TR1). Furthermore, Figure 2 The N-type transistors T3 and T4 in the pixel circuit PXC can be composed of oxide semiconductor transistor TR2 (also known as the second semiconductor transistor TR2). For example, Figure 7 The P-type transistors ST1, ST2, ST3, and ST4 of the STG1 stage can be composed of polysilicon semiconductor transistor TR1. Furthermore, Figure 7 The N-type transistors ST5, ST6, and ST7 of the STG1 stage can be composed of oxide semiconductor transistors TR2.

[0140] The substrate SUB can be made of various materials such as glass, polymers, or metals. Depending on the product to which it is applied, the substrate SUB can be selected from rigid and flexible substrates. When the substrate SUB includes polymeric organic materials, it can be made of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate, etc. On the other hand, the substrate SUB can be made of glass or fiberglass reinforced plastic (FRP), etc.

[0141] The first active layer ACL1 and the second active layer ACL2 can be semiconductor layers. For example, the first active layer ACL1 can be made of polysilicon semiconductor, and the second active layer ACL2 can be made of oxide semiconductor. The first active layer ACL1 may include a polysilicon semiconductor transistor TR1. Figure 7The second active layer ACL2 can include a channel CH2, a first electrode E21, and a second electrode E22 of a transistor ST5, ST6, or ST7. The first electrode and the second electrode of each transistor can be doped with impurities to have conductivity. Figure 7 The second active layer ACL2 can include a channel CH2, a first electrode E21, and a second electrode E22 of a transistor ST5, ST6, or ST7. The first electrode and the second electrode of each transistor can be doped with impurities to have conductivity.

[0142] The gate electrode GE1 of the polysilicon semiconductor transistor TR1 can be located in the first electrode layer CEL1. According to an embodiment, a sub-gate electrode (back gate electrode or body electrode) of the polysilicon semiconductor transistor TR1 can be located between the substrate SUB and the first insulating layer INL1.

[0143] The gate electrode GE2 of the oxide semiconductor transistor TR2 can be located in the third electrode layer CEL3. According to an embodiment, a sub-gate electrode (back gate electrode or body electrode) of the oxide semiconductor transistor TR2 can be located in the second electrode layer CEL2.

[0144] The first electrode layer CEL1, the second electrode layer CEL2, the third electrode layer CEL3, the fourth electrode layer CEL4, and the fifth electrode layer CEL5 can be conductive layers. Each electrode layer can be composed of a single layer or multiple layers, and can include known conductors such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt).

[0145] The first insulating layer INL1, the second insulating layer INL2, the third insulating layer INL3, the fourth insulating layer INL4, the fifth insulating layer INL5, the sixth insulating layer INL6, and the seventh insulating layer INL7 can be inserted to electrically isolate the active layers ACL1 and ACL2 from the first electrode layer CEL1, the second electrode layer CEL2, the third electrode layer CEL3, the fourth electrode layer CEL4, and the fifth electrode layer CEL5. Necessary electrode patterns can be connected to each other through contact holes formed in each of the insulating layers INL1 to INL7. The insulating layers INL1 to INL7 can be made of an organic insulating film, an inorganic insulating film, or an organic / inorganic insulating film, and can be composed of a single layer or multiple layers. For example, the insulating layers INL1 to INL7 can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin.

[0146] Figures 10 to 16is a schematic diagram for explaining a planar layout of a stage according to an embodiment.

[0147] Referring to Figure 10 Also referring to Figure 7 The first active layer ACL1 can include channels ST1c, ST2c, ST3c, and ST4c of transistors ST1, ST2, ST3, and ST4. Portions of the first active layer ACL1 that are spaced apart from each other with channels therebetween can constitute first and second electrodes of the transistors ST1, ST2, ST3, and ST4.

[0148] Referring to Figure 11 Also referring to Figure 7 and Figure 10 An example of a pattern of the first electrode layer CEL1 is shown. The first electrode layer CEL1 can include gate electrodes ST1g, ST2g, ST3g, and ST4g of transistors ST1, ST2, ST3, and ST4. The gate electrodes ST1g, ST2g, ST3g, and ST4g can overlap corresponding channels ST1c, ST2c, ST3c, and ST4c in the third direction DR3.

[0149] Some patterns of the first electrode layer CEL1 can constitute bridge patterns BRP5, BRP6, and BRP7 and a second electrode C1e2 of the capacitor C1. For example, the bridge pattern BRP7 can correspond to the output terminal OUT.

[0150] Referring to Figure 12 Also referring to Figure 7 An example of a pattern of the second electrode layer CEL2 is shown. The second electrode layer CEL2 can include back gate electrodes ST5b, ST6b, and ST7b of transistors ST5, ST6, and ST7. For example, one pattern of the second electrode layer CEL2 can constitute a first electrode C1e1 of the capacitor C1.

[0151] Referring to Figure 13 Also referring to Figure 7 and Figure 12 An example of a pattern of the second active layer ACL2 is shown. The second active layer ACL2 can include semiconductor patterns of transistors ST5, ST6, and ST7. The semiconductor patterns of the transistors ST5, ST6, and ST7 can include channels ST5c, ST6c, and ST7c. The channels ST5c, ST6c, and ST7c can overlap corresponding back gate electrodes ST5b, ST6b, and ST7b in the third direction DR3. Portions of the semiconductor patterns that are spaced apart from each other with channels therebetween can constitute first and second electrodes of the transistors ST5, ST6, and ST7.

[0152] For example, the semiconductor pattern of the fifth transistor ST5 can include a channel ST5c, a first electrode ST5el, and a second electrode ST5e2. The channel ST5c can extend in the first direction DR1. The first electrode ST5el can extend in the first direction DR1 and can include the etching portion n52. The second electrode ST5e2 can extend in the first direction DR1 and can include the etching portion n51.

[0153] For example, the semiconductor pattern of the sixth transistor ST6 can include two channels ST6c, two first sub-electrodes ST6el 1 and ST6el2, and one second electrode ST6e2. The channel ST6c can extend in the second direction DR2. The first sub-electrode ST6el 1 can extend in the second direction DR2 and can include the etching portion n61. The second electrode ST6e2 can extend in the second direction DR2 and can include the etching portion o61. The first sub-electrode ST6el2 can extend in the second direction DR2 and can include the etching portion n62.

[0154] For example, the semiconductor pattern of the seventh transistor ST7 can include a channel ST7c, first sub-electrodes ST7el 1, ST7el2,..., and second sub-electrodes ST7e21, ST7e22,.... As Figure 13 indicated in FIG. 17B, twelve channels ST7c, eight first sub-electrodes ST7el 1, ST7el2,..., and six second sub-electrodes ST7e21, ST7e22,... can be provided. The channel ST7c, the first sub-electrodes ST7el 1, ST7el2,..., and the second sub-electrodes ST7e21, ST7e22,... can extend in the first direction DR1.

[0155] The first sub-electrodes ST7el 1, ST7el2,... can include corresponding etching portions n72, n74, o73, o78, o71, o76, n71, and n73. The first sub-electrodes ST7el 1, ST7el2,... and the etching portions n72, n74, o73, o78, o71, o76, n71, and n73 can overlap with the electrode pattern EP71 in the third direction DR3 (see Figure 15 ). The second sub-electrodes ST7e21, ST7e22,... can include corresponding etching portions o74, o79, o72, o77, o70, and o75. The second sub-electrodes ST7e21, ST7e22,... and the etching portions o74, o79, o72, o77, o70, and o75 can overlap with the electrode pattern EP72 in the third direction DR3 (see Figure 15 ).

[0156] The etching portions n51 to n74 and the etching portions o61 to o79 can be hydrogen gas exhaust ports. As hydrogen gas escapes through the etching portions, the conductivity of the semiconductor pattern can be determined. For example, as the etching portions become larger and more, the conductivity of the adjacent semiconductor pattern can improve. The etching portions n51 to n74 and the etching portions o61 to o79 can be notches n51 to n74 and openings o61 to o79, respectively.

[0157] Referring to Figure 14 Also referring to Figure 7 and Figure 13 An example of a pattern of the third electrode layer CEL3 is shown. The third electrode layer CEL3 can include gate electrodes ST5g, ST6g, and ST7g of the transistors ST5, ST6, and ST7. The gate electrodes ST5g, ST6g, and ST7g can overlap the corresponding channels ST5c, ST6c, and ST7c in the third direction DR3.

[0158] Referring to Figure 15 Also referring to Figure 9 , Figure 11 and Figure 16 An example of a pattern of the fourth electrode layer CEL4 is shown. Some patterns of the fourth electrode layer CEL4 can include the first clock line CK1L, the second clock line CK2L, the scan start line FLML, and electrode patterns EP5, EP61, EP62, EP71, and EP72. However, in the stages other than the first stage STG1, the output terminal OUT of the previous stage can be located at the position of the scan start line FLML. The electrode pattern EP71 can correspond to the third input terminal IN3 of the next stage STG2. The first clock signal CK1 can be applied to the first clock line CK1L, and the second clock signal CK2 can be applied to the second clock line CK2L.

[0159] The first contact hole PCNT can be a hole etched to connect a pattern of the fourth electrode layer CEL4 to an electrode layer located below or the first active layer ACL1. The second contact hole OCNT can be a hole etched to connect a pattern of the fourth electrode layer CEL4 to an electrode layer located below or the second active layer ACL2.

[0160] The third contact hole VIA1 can be a hole formed in the seventh insulating layer INL7 located on the fourth electrode layer CEL4 and is shown to explain the relationship between the fourth electrode layer CEL4 and the fifth electrode layer CEL5.

[0161] Referring to Figure 16 Also referring to Figure 6, an example of a pattern of the fifth electrode layer CEL5 is shown. Some patterns of the fifth electrode layer CEL5 can include a first low voltage line VGL1L, a reset line ESRL, a second low voltage line VGL2L, and a high voltage line VGHL. A first low voltage VGL1 can be applied to the first low voltage line VGL1L, a second low voltage VGL2 can be applied to the second low voltage line VGL2L, a reset signal ESR can be applied to the reset line ESRL, and a high voltage VGH can be applied to the high voltage line VGHL.

[0162] Figure 17 is a reference schematic diagram showing all layers shown in Figures 10 to 16 overlapping each other.

[0163] Figure 18 is a schematic cross-sectional view taken along the line I-I’ in Figures 10 to 17 .

[0164] Referring to Figure 18 , also referring to Figure 7 , Figure 9 and Figure 15 , the fifth transistor ST5 can include a semiconductor pattern located in the second active layer ACL2, a bridge pattern BRP5 located in the first electrode layer CEL1, and an electrode pattern EP5 located in the fourth electrode layer CEL4.

[0165] The semiconductor pattern can include an etched portion n52. The electrode pattern EP5 can connect the semiconductor pattern and the bridge pattern BRP5, but the electrode pattern EP5 can pass through the etched portion n52 of the semiconductor pattern and contact the bridge pattern BRP5.

[0166] The semiconductor pattern can include a first electrode ST5e1 of the fifth transistor ST5. The electrode pattern EP5 can contact the first electrode ST5e1 of the fifth transistor ST5.

[0167] The bridge pattern BRP5 can be connected to an electrode of a transistor other than the fifth transistor ST5. For example, the bridge pattern BRP5 can be connected to a gate electrode ST2g of the second transistor ST2 (see Figure 11 ).

[0168] A second electrode ST5e2 (see Figure 13 ) of the fifth transistor ST5 can receive a scan start signal FLM (see Figure 6 ) or a scan signal of a previous stage.

[0169] Figure 19 is a schematic cross-sectional view taken along the line II-II’ in Figures 10 to 17 .

[0170] Referring to Figure 19 , also referring toFigure 7 、 Figure 9 and Figure 15 The sixth transistor ST6 can include a semiconductor pattern located in the second active layer ACL2, a bridge pattern BRP6 located in the first electrode layer CEL1, and electrode patterns EP61 and EP62 located in the fourth electrode layer CEL4. The electrode patterns can include sub-electrode patterns EP61 and EP62 spaced apart from each other.

[0171] The semiconductor pattern can include etched portions n61 and n62. The sub-electrode pattern EP61 can connect the semiconductor pattern and the bridge pattern BRP6, but the sub-electrode pattern EP61 can pass through the etched portion n61 of the semiconductor pattern and contact the bridge pattern BRP6. The sub-electrode pattern EP62 can connect the semiconductor pattern and the bridge pattern BRP6, but the sub-electrode pattern EP62 can pass through the etched portion n62 of the semiconductor pattern and contact the bridge pattern BRP6.

[0172] The semiconductor pattern can include a first electrode of the sixth transistor ST6. The first electrode of the sixth transistor ST6 can include first sub-electrodes ST6e11 and ST6e12 spaced apart from each other. The sub-electrode patterns EP61 and EP62 can contact the corresponding first sub-electrodes ST6e11 and ST6e12, respectively. For example, the sub-electrode pattern EP61 can contact the first sub-electrode ST6e11, and the sub-electrode pattern EP62 can contact the first sub-electrode ST6e12. The bridge pattern BRP6 can connect the sub-electrode patterns EP61 and EP62.

[0173] The first electrode of the sixth transistor ST6 can be connected to a gate electrode of at least one first semiconductor transistor TR1. For example, the first electrode of the sixth transistor ST6 can be connected to a gate electrode of the third transistor ST3 (see Figure 7 ).

[0174] The first electrode of the sixth transistor ST6 can also be connected to a gate electrode of at least one second semiconductor transistor TR2. For example, the first electrode of the sixth transistor ST6 can be connected to a gate electrode of the seventh transistor ST7 (see Figure 7 ).

[0175] Figure 20 is a schematic cross-sectional view taken along line III-III’ in Figures 10 to 17 .

[0176] Referring to Figure 20 , also referring to Figure 1 、 Figure 7 、 Figure 9 and Figure 15The seventh transistor ST7 can include a semiconductor pattern in the second active layer ACL2, a bridge pattern BRP7 in the first electrode layer CEL1, and an electrode pattern EP71 in the fourth electrode layer CEL4.

[0177] The semiconductor pattern can include etching portions n74 and n72. The electrode pattern EP71 can connect the semiconductor pattern and the bridge pattern BRP7, but the electrode pattern EP71 can pass through the etching portions n74 and n72 of the semiconductor pattern and contact the bridge pattern BRP7.

[0178] The semiconductor pattern can include a first electrode of the seventh transistor ST7. The first electrode of the seventh transistor ST7 can include first sub-electrodes ST7e12 and ST7e11 spaced apart from each other. The electrode pattern EP71 can contact the first sub-electrodes ST7e12 and ST7e11 of the seventh transistor ST7.

[0179] The bridge pattern BRP7 can be a scan line connecting the pixel PXij and the scan driver 13S. For example, the scan line can be a wire extending from the output terminal OUT. For example, as described above, the emission driver 15 can be configured in the same manner as the scan driver 13S (see Figure 6 the description thereof). Accordingly, the bridge pattern BRP7 can be an emission line connecting the pixel PXij and the emission driver 15.

[0180] The seventh transistor ST7 can be connected to at least one of a plurality of first semiconductor transistors TR1. For example, the seventh transistor ST7 can be connected to the third transistor ST3 (see Figure 7 ). The seventh transistor ST7 can be connected to at least one (for example, the third transistor ST3) of the first semiconductor transistors TR1 through the electrode pattern EP71 (see Figure 15 ).

[0181] According to the present embodiment, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 can form various connection structures using etching portions as hydrogen gas exhaust ports. Accordingly, it is possible to reduce useless spaces in the display device 10 or the scan driver 13S.

[0182] The scan driver according to an embodiment of the present application and the display device including the same can minimize useless spaces by using a hydrogen gas exhaust port as a contact hole.

[0183] The above description is an example of technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and changes. Therefore, the above-described embodiments of the present disclosure can be implemented individually or in combination with each other.

[0184] The embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The scope of protection of the present disclosure should be interpreted by the appended claims, and all technical spirits within the equivalent scope should be interpreted to be within the scope of the present disclosure.

Claims

1. A display device, characterized by comprising: The display device includes: a plurality of first semiconductor transistors having: a first semiconductor layer; and a plurality of semiconductor patterns of the plurality of first semiconductor transistors in the first semiconductor layer; and a plurality of second semiconductor transistors having: a second semiconductor layer; and a plurality of semiconductor patterns of the plurality of second semiconductor transistors in the second semiconductor layer positioned on the first semiconductor layer, wherein, a first electrode layer is between the first semiconductor layer and the second semiconductor layer, a second electrode layer is on the second semiconductor layer, a first transistor among the plurality of second semiconductor transistors includes a first semiconductor pattern in the second semiconductor layer, a bridge pattern in the first electrode layer, and an electrode pattern in the second electrode layer, the first semiconductor pattern includes an etching portion, the electrode pattern connects the first semiconductor pattern and the bridge pattern, and the electrode pattern passes through the etching portion of the first semiconductor pattern and contacts the bridge pattern.

2. The display device according to claim 1, wherein The etching portion is a notch or an opening.

3. The display device according to claim 1, wherein The etching portion is a hydrogen gas exhaust.

4. The display device according to claim 1, wherein, the first semiconductor pattern includes a first electrode of the first transistor, and the electrode pattern contacts the first electrode of the first transistor.

5. The display device according to claim 1, wherein The bridge pattern is connected to electrodes of transistors among the plurality of first semiconductor transistors and the plurality of second semiconductor transistors other than the first transistor.

6. The display device according to claim 1, wherein, the first semiconductor pattern includes a first electrode of the first transistor, the first electrode of the first transistor includes a plurality of first sub-electrodes spaced apart from each other, the electrode pattern includes a plurality of sub-electrode patterns spaced apart from each other, the plurality of sub-electrode patterns contact a corresponding plurality of first sub-electrodes, and the bridge pattern connects the plurality of sub-electrode patterns.

7. The display device according to claim 1, wherein The bridge pattern is a scan line connecting a pixel and a scan driver of the display device.

8. The display device according to claim 1, wherein The bridge pattern is an emission line connecting a pixel and an emission driver of the display device.

9. A scan driver comprising a plurality of stages, characterized in that, Each of the plurality of stages includes: a plurality of first semiconductor transistors having: a first semiconductor layer; and a plurality of semiconductor patterns of the plurality of first semiconductor transistors in the first semiconductor layer; and a plurality of second semiconductor transistors having: a second semiconductor layer; and a plurality of semiconductor patterns of the plurality of second semiconductor transistors in the second semiconductor layer positioned on the first semiconductor layer, wherein, a first electrode layer is between the first semiconductor layer and the second semiconductor layer, a second electrode layer is on the second semiconductor layer, a first transistor among the plurality of second semiconductor transistors includes a first semiconductor pattern in the second semiconductor layer, a bridge pattern in the first electrode layer, and an electrode pattern in the second electrode layer, the first semiconductor pattern includes an etching portion, the electrode pattern connects the first semiconductor pattern and the bridge pattern, and the electrode pattern passes through the etching portion of the first semiconductor pattern and contacts the bridge pattern. The electrode pattern passes through the etched portion of the first semiconductor pattern and contacts the bridge pattern.

10. The scan driver of claim 9, wherein, The bridge pattern is a scan line.

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