Anti-misoperation power supply circuit and electronic equipment

Abstract

The embodiment of the utility model relates to the field of power management, and discloses an anti-misoperation power supply circuit and electronic equipment. The anti-misoperation power supply circuit comprises a time delay module, a first NMOS (N-channel Metal Oxide Semiconductor) transistor, a second NMOS transistor and a power supply circuit, the delay module is connected with the first NMOS transistor, and an input level signal is transmitted to the first NMOS transistor through the delay module; the drain electrode of the first NMOS transistor is connected with the grid electrode of the second NMOS transistor, when the first NMOS transistor is in the on state, the second NMOS transistor is in the off state, and when the first NMOS transistor is in the off state, the second NMOS transistor determines whether the second NMOS transistor is in the on state or not based on an input level signal; the second NMOS transistor is connected with the power supply circuit, and the on-off state of the second NMOS transistor is associated with the on-off state of the power supply circuit. The power supply circuit is prevented from being mistakenly triggered by a wrong level signal under the condition that power supply is not needed, and normal work of equipment is guaranteed.

Description

TECHNICAL FIELD

[0001] The embodiment of the utility model relates to the power management field, especially relates to a power supply circuit and electronic equipment of preventing misoperation. BACKGROUND

[0002] When the main control chip controls the opening or closing of the power supply circuit, a high level signal is usually sent by the main control chip, the switch of the power supply circuit is turned on by the high level signal, and the power supply circuit completes power supply to the equipment. The inventor finds that at least the following problems exist in the control mode: due to chip failure or other interference factors, the main control chip may send an error high level signal without power supply, which causes the switch of the power supply circuit to be mis-triggered, and the equipment side presents a cycle of switching between starting and shutting down, which affects the normal work of the equipment and even affects the service life of the equipment. CONTENT OF THE UTILITY MODEL

[0003] The embodiment of the utility model aims at providing a power supply circuit and electronic equipment of preventing misoperation, which prevents the power supply circuit from being mis-triggered by an error level signal without power supply.

[0004] To solve the above technical problems, the embodiment of the utility model provides a power supply circuit of preventing misoperation, which comprises: a delay module, a first NMOS transistor, a second NMOS transistor and a power supply circuit. The delay module is connected with the first NMOS transistor, and an input level signal is transmitted to the first NMOS transistor through the delay module. The drain electrode of the first NMOS transistor is connected with the gate electrode of the second NMOS transistor. When the first NMOS transistor is in the on state, the second NMOS transistor is in the off state. When the first NMOS transistor is in the off state, the second NMOS transistor determines whether to be in the on state based on the input level signal. The second NMOS transistor is connected with the power supply circuit, and the on-off state of the second NMOS transistor is associated with the on-off state of the power supply circuit.

[0005] The embodiment of the utility model also provides an electronic equipment, which comprises a main control chip and the above-mentioned power supply circuit of preventing misoperation connected with the pin of the main control chip.

[0006] The embodiment of the utility model relative to prior art, in input level signal reaches the switch of power supply circuit, in turn through delay module, first NMOS transistor and second NMOS transistor. First NMOS transistor drain connects second NMOS transistor grid, when first NMOS transistor is on state, second NMOS transistor is off state, when first NMOS transistor is off state, second NMOS transistor is based on input level signal and determines whether it is on state. After input level signal reaches delay module, under the influence of delay module and first NMOS transistor, second NMOS transistor receives a short low level signal and keeps off state, if input level signal is normal high level control signal, then second NMOS transistor receives a short low level signal and restores to normal high level control signal and switches to on state, and then control power supply circuit on. If input level signal is abnormal signal, then it restores to low level soon, because second NMOS transistor will receive a short low level signal and keep off state, therefore, this abnormal signal will not affect the on-off state of second NMOS transistor, avoid power supply circuit under the condition of not needing power supply to be error level signal false triggering.

[0007] In addition, the delay module comprises an RC delay sub-circuit composed of a first capacitor and a first resistor.

[0008] In addition, the anti-misoperation power supply circuit further comprises a voltage dividing module connected to the gate of the second NMOS transistor, for voltage dividing the input level signal.

[0009] In addition, the voltage dividing module comprises a second resistor connected in series with the second NMOS transistor, and a second capacitor and a third resistor connected in parallel with the second NMOS transistor.

[0010] In addition, the power supply circuit comprises a battery and a power switch connected to the second NMOS transistor, for adjusting the on-off state of the power switch based on the on-off state of the second NMOS transistor.

[0011] In addition, the power switch is a PMOS transistor.

[0012] In addition, the drain of the second NMOS transistor is connected to the gate of the PMOS transistor.

[0013] In addition, the anti-misoperation power supply circuit further comprises a fourth resistor, and the power supply is connected to the drain of the second NMOS transistor through the fourth resistor. BRIEF DESCRIPTION OF DRAWINGS

[0014] One or more embodiments are illustrated by way of example in the drawings and are described herein in connection with the embodiments described. These embodiments are not intended to limit the scope of the embodiments to the embodiments described, but rather, serve as well to cover any modifications and equivalents included within the spirit and scope of the embodiments.

[0015] Figure 1 is a structural schematic diagram of a power supply circuit according to the present application;

[0016] Figure 2 is a structural schematic diagram of a power supply circuit according to the present application;

[0017] Figure 3 is a circuit structural schematic diagram of a power supply circuit according to the present application. DETAILED DESCRIPTION

[0018] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are proposed in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be realized even without these technical details and various changes and modifications based on the following embodiments.

[0019] The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation of the present application, and each embodiment can be combined and referenced with each other on the premise of no contradiction.

[0020] The embodiments of the present application relate to a power supply circuit for preventing misoperation, as shown in Figure 1 The embodiments of the present application relate to a power supply circuit for preventing misoperation, as shown in The drain electrode of the first NMOS transistor is connected to the gate electrode of the second NMOS transistor, when the first NMOS transistor is in a conductive state, the second NMOS transistor is in a disconnected state, when the first NMOS transistor is in a disconnected state, the second NMOS transistor determines whether to be in a conductive state based on the input level signal; the second NMOS transistor is connected with the power supply circuit, and the on-off state of the second NMOS transistor is associated with the on-off state of the power supply circuit.

[0021] The working state of the power supply circuit for preventing misoperation in the embodiments will be described in detail below under the condition of different input level signals BAT_CTL:

[0022] When the input level signal BAT_CTL is a normal control signal, the BAT_CTL is changed from low level to stable high level, the first NMOS transistor gate receives high level and is in the on state, which pulls down the level of the second NMOS transistor gate, and the second NMOS transistor gate remains closed. After the delay module is charged under the influence of the level, the delay module pulls down the first NMOS transistor gate level, the first NMOS transistor is switched to the off state, the second NMOS transistor gate is switched to the on state under the influence of the high level of the input level signal BAT_CTL, and then controls the power supply circuit to be turned on to supply power.

[0023] When the input level signal BAT_CTL is a low level signal, the first NMOS transistor gate and the second NMOS transistor gate are both low level, and the two NMOS transistors are both in the off state. At this time, the delay module is not charged, so the state of the first NMOS transistor gate and the second NMOS transistor gate will not be changed, and the power supply circuit always remains in the off state without power supply.

[0024] When the input level signal BAT_CTL is an error high level signal, that is, a short high level signal is generated and then restored to a low level signal. The first NMOS transistor gate receives a high level and is in the on state, which pulls down the level of the second NMOS transistor gate, and the second NMOS transistor gate remains closed. During the charging process of the delay module under the influence of the level, the high level signal of the BAT_CTL has been switched to a low level signal, so the level of the second NMOS transistor gate remains a low level signal and remains closed before the delay module is charged. The power supply circuit also remains in the off state without power supply, and the short error high level signal will not affect the opening of the power supply circuit.

[0025] Compared with the related art, in the embodiment of the utility model, the input level signal sequentially passes through the delay module, the first NMOS transistor and the second NMOS transistor before reaching the switch of the power supply circuit. The first NMOS transistor drain is connected with the second NMOS transistor gate, when the first NMOS transistor is in the on state, the second NMOS transistor is in the off state, when the first NMOS transistor is in the off state, the second NMOS transistor determines whether to be in the on state based on the input level signal. After the input level signal reaches the delay module, under the influence of the delay module and the first NMOS transistor, the second NMOS transistor receives a short low level signal to keep the off state, if the input level signal is a normal high level control signal, the second NMOS transistor receives a short low level signal and then restores to the normal high level control signal to switch to the on state, thereby controlling the power supply circuit to be on. If the input level signal is an abnormal signal, it will soon restore to the low level, because the second NMOS transistor will receive a short low level signal to keep the off state, therefore, the abnormal signal will not affect the on-off state of the second NMOS transistor, avoiding that the power supply circuit is triggered by the false level signal in the case of no power supply.

[0026] In addition, as shown in Figure 2 The false operation prevention power supply circuit further comprises a voltage dividing module connected with the gate of the second NMOS transistor for dividing the input level signal. The high level signal is prevented from directly entering the second NMOS transistor to cause damage.

[0027] The false operation prevention power supply circuit is introduced as follows, as shown in Figure 3 The delay module comprises an RC delay sub-circuit composed of a first capacitor C1 and a first resistor R1. When the BAT_CTL received by the first capacitor C1 changes from low level to high level, because the voltage difference across the capacitor cannot change suddenly, the first capacitor C1 close to NMOS1 one end will change to high level instantaneously, and with the charging of the first capacitor C1, the voltage difference across C1 gradually increases, the level close to NMOS1 one end gradually decreases, and the gate level of NMOS1 gradually decreases, from the on state to the low level off state.

[0028] In addition, the voltage dividing module comprises a second resistor R2 connected with the second NMOS transistor (NMOS2) in series, and a second capacitor C2 and a third resistor R3 connected with the second NMOS transistor (NMOS2) in parallel.

[0029] In addition, the power supply circuit comprises a battery BAT+ and a power switch.

[0030] In addition, the anti-misoperation power supply circuit further comprises a fourth resistor R4, and the power supply is connected with the drain of the second NMOS transistor (NMOS2) through the fourth resistor R4.

[0031] When the power switch PMOS1 is in the on state, the power supply outputs VBAT to supply power to the device.

[0032] The utility model discloses an electronic equipment, and it comprises: master control chip and the anti-misoperation power supply circuit of preceding described that is connected with master control chip pin.

[0033] Compared with the prior art, the electronic equipment provided by the embodiment of the utility model is provided with the anti-misoperation power supply circuit provided by the preceding embodiment, so it also has the technical effects provided by the preceding embodiment, which will not be described here.

[0034] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the utility model, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the utility model.

Claims

1. A misoperation prevention power supply circuit characterized by comprising: The application relates to a misoperation-preventing power supply circuit. The misoperation-preventing power supply circuit comprises a delay module, a first NMOS transistor, a second NMOS transistor and a power supply circuit. The delay module is connected with the first NMOS transistor, and an input level signal is transmitted to the first NMOS transistor through the delay module. The drain electrode of the first NMOS transistor is connected with the gate electrode of the second NMOS transistor, when the first NMOS transistor is in a conducting state, the second NMOS transistor is in a non-conducting state, and when the first NMOS transistor is in a non-conducting state, the second NMOS transistor determines whether to be in a conducting state based on the input level signal. The second NMOS transistor is connected with the power supply circuit, and the on-off state of the second NMOS transistor is associated with the on-off state of the power supply circuit.

2. The misoperation prevention power supply circuit according to claim 1, characterized by The delay module comprises an RC delay sub-circuit composed of a first capacitor and a first resistor.

3. The misoperation prevention power supply circuit according to claim 1, characterized by The misoperation-preventing power supply circuit further comprises: a voltage dividing module; The voltage dividing module is connected with the gate electrode of the second NMOS transistor and is used for dividing the input level signal.

4. The misoperation-preventing power supply circuit according to claim 3, wherein The voltage dividing module comprises a second resistor connected with the second NMOS transistor in series, and a second capacitor and a third resistor connected with the second NMOS transistor in parallel.

5. The misoperation prevention power supply circuit according to claim 1, characterized by The power supply circuit comprises a battery and a power supply switch. The power supply switch is connected with the second NMOS transistor, and the on-off state of the power supply switch is adjusted based on the on-off state of the second NMOS transistor.

6. The misoperation prevention power supply circuit according to claim 5, wherein The power supply switch is a PMOS transistor.

7. The misoperation prevention power supply circuit according to claim 6, characterized by The drain electrode of the second NMOS transistor is connected with the gate electrode of the PMOS transistor.

8. The misoperation prevention power supply circuit according to claim 7, characterized by The misoperation-preventing power supply circuit further comprises: a fourth resistor; The power supply is connected with the drain electrode of the second NMOS transistor through the fourth resistor.

9. An electronic device, comprising: The misoperation-preventing power supply circuit comprises a master control chip and a misoperation-preventing power supply circuit connected with the pin of the master control chip. The misoperation-preventing power supply circuit comprises a master control chip and a misoperation-preventing power supply circuit connected with the pin of the master control chip.

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