Display substrate, pixel circuit and display device

Abstract

The utility model provides a display substrate, a pixel circuit and a display device. The display substrate comprises a driving circuit layer, wherein a pixel circuit in the driving circuit layer comprises a first transistor, a second transistor and a third transistor; wherein the driving circuit layer comprises a first functional film layer and a second functional film layer which are sequentially stacked in the direction away from the substrate, the first functional film layer comprises a first transistor, and the second functional film layer comprises a second transistor and a third transistor; the first electrode of the second transistor is electrically coupled with the control electrode of the first transistor through a first via hole, and the first electrode of the third transistor is electrically coupled with the first electrode of the first transistor through a second via hole. The orthographic projection of the first transistor on the substrate is at least partially overlapped with the orthographic projection of the second transistor and / or the third transistor on the substrate. The plurality of transistors of the pixel circuit are stacked in different functional film layers and are electrically coupled through the via holes, so that high resolution of the display panel can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display substrate, a pixel circuit and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field. CONTENT OF THE UTILITY MODEL

[0003] The purpose of the present application is to provide a display substrate, a pixel circuit and a display device.

[0004] In a first aspect, the present application provides a display substrate, comprising:

[0005] a substrate substrate;

[0006] a driving circuit layer disposed on the substrate substrate, comprising a plurality of pixel circuits arranged in an array, the pixel circuit comprising a first transistor, a second transistor and a third transistor;

[0007] a plurality of sub-pixels arranged in an array, electrically coupled one-to-one with the plurality of pixel circuits, and disposed on a side of the driving circuit layer away from the substrate substrate;

[0008] wherein the driving circuit layer comprises a first functional film layer and a second functional film layer stacked in sequence in a direction away from the substrate substrate;

[0009] The first functional film layer comprises the first transistor, the second functional film layer comprises the second transistor and the third transistor, the first electrode of the second transistor is electrically coupled with the control electrode of the first transistor through a first via, the first electrode of the third transistor is electrically coupled with the first electrode of the first transistor through a second via, and the orthographic projection of the first transistor on the substrate substrate at least partially overlaps with the orthographic projection of the second transistor and / or the third transistor on the substrate substrate.

[0010] In a second aspect, the present application provides a pixel circuit applied to the display substrate in the first aspect, wherein the pixel circuit comprises a driving unit, a first storage capacitor, a light-emitting unit, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit and a fifth switching unit.

[0011] The first switching unit is electrically coupled with a first reset signal terminal and a first terminal of the first storage capacitor.

[0012] The second switching unit is electrically coupled with a data signal terminal and the first terminal of the first storage capacitor.

[0013] The third switching unit is electrically coupled with the light-emitting unit and a second terminal of the first storage capacitor.

[0014] The light-emitting unit is electrically coupled with a first power terminal.

[0015] The fourth switching unit is electrically coupled with a second power terminal and the driving unit.

[0016] The driving unit is electrically coupled with the first terminal of the first storage capacitor and the second terminal of the first storage capacitor.

[0017] The fifth switching unit is electrically coupled with an initial signal terminal and the second terminal of the first storage capacitor.

[0018] In a third aspect, the present application provides a display device comprising the display substrate in the first aspect.

[0019] As can be seen from the above, the present application provides a display substrate, a pixel circuit and a display device. The display substrate comprises a driving circuit layer, and the pixel circuit in the driving circuit layer comprises a first transistor, a second transistor and a third transistor. The driving circuit layer comprises a first functional film layer and a second functional film layer which are sequentially stacked in a direction away from a substrate. The first functional film layer comprises the first transistor, and the second functional film layer comprises the second transistor and the third transistor. A first pole of the second transistor is electrically coupled with a control pole of the first transistor through a first via, and a first pole of the third transistor is electrically coupled with a first pole of the first transistor through a second via. A normal projection of the first transistor on the substrate at least partially overlaps with a normal projection of the second transistor and / or the third transistor on the substrate. The multiple transistors of the pixel circuit are stacked in different functional film layers and electrically coupled through vias, so as to realize high resolution of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the application or the related art, the drawings needed to be used in the embodiments or the related description will be briefly introduced. Obviously, the drawings in the following description only constitute the embodiments of the application, and for those skilled in the art, other drawings can be obtained without creative labor based on these drawings.

[0021] Figure 1 A schematic diagram of an exemplary display device 100 according to an embodiment of the application is shown.

[0022] Figure 2 An equivalent circuit schematic diagram of a pixel circuit 200 according to an embodiment of the application is shown.

[0023] Figure 3 A timing diagram of nodes in a driving method of an exemplary pixel circuit 200 according to an embodiment of the application is shown.

[0024] Figure 4A A structural schematic diagram of an exemplary pixel circuit 400 according to an embodiment of the application is shown.

[0025] Figure 4B An equivalent circuit schematic diagram of an exemplary pixel circuit 420 according to an embodiment of the application is shown.

[0026] Figure 4C A structural schematic diagram of an exemplary pixel circuit 440 according to an embodiment of the application is shown.

[0027] Figure 4D An equivalent circuit schematic diagram of an exemplary pixel circuit 460 according to an embodiment of the application is shown.

[0028] Figure 5 A timing diagram of nodes in a driving method of an exemplary pixel circuit 400 or pixel circuit 420 according to an embodiment of the application is shown.

[0029] Figure 6A A schematic diagram of an exemplary display substrate 600 according to an embodiment of the application is shown.

[0030] Figure 6B A schematic diagram of an exemplary display substrate 700 according to an embodiment of the application is shown.

[0031] Figure 7 A flow schematic diagram of a preparation method 710 of an exemplary display substrate according to an embodiment of the application is shown. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the application clearer, the application will be further described in detail below with reference to specific embodiments and drawings.

[0033] It should be noted that, unless otherwise defined, technical terms or scientific terms used in the embodiments of the present application shall have the ordinary meaning understood by one of ordinary skill in the art to which the present application pertains. The terms "first", "second", and similar terms used in the embodiments of the present application do not denote any order, quantity, or importance, but are merely used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" and "connected" and similar terms do not mean only physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are merely used to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0034] With the diversification of market demand in the field of display technology, the requirement for high resolution of display panels is also increasingly high. However, in order to improve the display effect, a plurality of thin film transistor devices need to be applied in the pixel circuit corresponding to each pixel in the display panel. The number of thin film transistor devices increases, and the occupied area also increases, which limits the opening area of the pixel and further limits the resolution of the display panel.

[0035] To at least solve the above technical problems, the present application provides a display substrate, a pixel circuit and a display device. The display substrate comprises a driving circuit layer, and the pixel circuit in the driving circuit layer comprises a first transistor, a second transistor and a third transistor; wherein the driving circuit layer comprises a first functional film layer and a second functional film layer which are sequentially stacked in a direction away from a substrate, the first functional film layer comprises the first transistor, the second functional film layer comprises the second transistor and the third transistor, the first electrode of the second transistor is electrically coupled with the control electrode of the first transistor through a first via, the first electrode of the third transistor is electrically coupled with the first electrode of the first transistor through a second via, and the orthogonal projection of the first transistor on the substrate at least partially overlaps with the orthogonal projection of the second transistor and / or the third transistor on the substrate. Stacking a plurality of transistors of the pixel circuit in different functional film layers and electrically coupling them through vias can achieve high resolution of the display panel.

[0036] Figure 1 A schematic diagram of an exemplary display device 100 according to embodiments of the present application is shown.

[0037] The display device 100 is a product with image display function, for example, can be: a display, a television, a billboard, a digital photo frame, a laser printer with display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, a household appliance, an information query device (such as a business query device of an electronic government, a bank, a hospital, a power department, a monitor, etc.).

[0038] As shown in Figure 1 , the display device 100 can include a display substrate 102. The display substrate 102 can include a substrate substrate (not shown in the figure). The display device 100 can also include a driving circuit layer (not shown in the figure) disposed on the substrate substrate, and the driving circuit layer can include a plurality of pixel circuits arranged in an array, which are used to control the brightness and gray scale of the pixels. In some embodiments, the pixel circuit can be a 2T1C, 3T1C, 4T1C, 5T1C, 6T1C or 7T1C structure.

[0039] Figure 2 An equivalent circuit schematic diagram of a pixel circuit 200 according to an embodiment of the present application is shown. The pixel circuit 200 can be a 7T1C structure.

[0040] As shown in Figure 2 , the pixel circuit 200 can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor C. Among them, the third transistor T3 can be a driving transistor T3.

[0041] For example, as shown in Figure 2 , the first transistor T1 is a first reset transistor T1, the second transistor T2 is a threshold compensation transistor T2, the fourth transistor T4 is a data writing transistor T4, the fifth transistor T5 is a second light-emitting control transistor T5, the sixth transistor T6 is a first light-emitting control transistor T6, and the seventh transistor T7 is a second reset transistor T7.

[0042] For example, the first electrode of the first transistor T1 is connected to the N1 node, i.e. is electrically coupled to the control electrode of the driving transistor T3, the second electrode of the first transistor T1 is electrically coupled to the first initial signal terminal Vinit1, i.e. is electrically coupled to the first reset signal line to receive a reset signal, and the control electrode of the first transistor T1 is electrically coupled to the first reset signal terminal Re1, i.e. is electrically coupled to the reset control signal line to receive a reset control signal; the first electrode of the second transistor T2, i.e. the threshold compensation transistor, is connected to the N1 node, i.e. is electrically coupled to the control electrode of the driving transistor T3, the second electrode of the second transistor T2 is electrically coupled to the second electrode of the driving transistor T3, and the control electrode of the second transistor T2 is electrically coupled to the first driving signal terminal G1 to receive a compensation control signal; the control electrode of the driving transistor T3 is connected to the N1 node, i.e. is electrically coupled to the first electrode of the storage capacitor C, the first electrode of the first transistor T1 and the first electrode of the second transistor T2; the first electrode of the fourth transistor T4, i.e. the data writing transistor, is electrically coupled to the data signal terminal Data to receive a data signal, the second electrode of the fourth transistor T4 is electrically coupled to the first electrode of the driving transistor T3, and the control electrode of the fourth transistor T4 is electrically coupled to the second driving signal terminal G2 to receive a scanning signal; the first electrode of the fifth transistor T5, i.e. the second light-emitting control transistor, is electrically coupled to the first power supply terminal VDD to receive a first power supply signal, the second electrode of the fifth transistor T5 is electrically coupled to the first electrode of the driving transistor T3, and the control electrode of the fifth transistor T5 is electrically coupled to the light-emitting control signal terminal EM to receive a light-emitting control signal; the first electrode of the sixth transistor T6, i.e. the first light-emitting control transistor, is electrically coupled to the second electrode of the driving transistor T3, the second electrode of the sixth transistor T6 is electrically coupled to the first electrode of the seventh transistor T7, and the control electrode of the sixth transistor T6 is electrically coupled to the light-emitting control signal terminal EM to receive a light-emitting control signal; the second electrode of the seventh transistor T7 is electrically coupled to the second initial signal terminal Vinit2, i.e. is electrically coupled to the second reset signal line to receive a reset signal Vinit, the control electrode of the seventh transistor T7 is electrically coupled to the second reset signal terminal Re2, i.e. is electrically coupled to the reset control signal line to receive a reset control signal, and the first electrode of the seventh transistor T7 is connected to the node N4; the first electrode of the storage capacitor C is connected to the N1 node and is electrically coupled to the control electrode of the driving transistor T3, and the second electrode of the storage capacitor C is electrically coupled to the first power supply terminal VDD, i.e. is connected to the first power supply signal line. The pixel circuit 200 can be connected to the light-emitting unit 120, which can be an organic light-emitting diode (OLED), and the pixel circuit 200 is used to drive the light-emitting unit 120 to emit light. The light-emitting unit 120 can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS, i.e. is connected to the second power supply signal line.

[0043] For example, the first power signal line refers to a signal line outputting a voltage signal VDD, which can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal. The second power signal line refers to a signal line outputting a voltage signal VSS, which can be connected to a voltage source to output a constant voltage signal, such as a negative voltage signal.

[0044] For example, the scan signal and the compensation control signal can be the same, i.e., the control electrode of the data write transistor T4 and the control electrode of the threshold compensation transistor T2 can be electrically coupled to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the control electrode of the data write transistor T4 and the control electrode of the threshold compensation transistor T2 can also be electrically coupled to different signal lines, respectively, i.e., the control electrode of the data write transistor T4 is electrically coupled to a second scan signal line, and the control electrode of the threshold compensation transistor T2 is electrically coupled to a first scan signal line, and the signals transmitted by the first scan signal line and the second scan signal line can be the same or different, so that the control electrode of the data write transistor T4 and the control electrode of the threshold compensation transistor T2 can be separately controlled, thereby increasing the flexibility of controlling the pixel circuit.

[0045] For example, the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can be input with the same light-emitting control signal, i.e., the control electrode of the first light-emitting control transistor T6 and the control electrode of the second light-emitting control transistor T5 can be electrically coupled to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the control electrodes of the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can also be electrically coupled to different light-emitting control signal lines, respectively, and the signals transmitted by the different light-emitting control signal lines can be the same or different.

[0046] For example, the second reset transistor T7 and the first reset transistor T1 can be input with the same reset control signal, i.e., the control electrode of the second reset transistor T7 and the control electrode of the first reset transistor T1 can be electrically coupled to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the control electrode of the second reset transistor T7 and the control electrode of the first reset transistor T1 can also be electrically coupled to different reset control signal lines, respectively, and the signals on the different reset control signal lines can be the same or different.

[0047] For example, the first transistor T1 and the second transistor T2 can be N-type transistors. For example, the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors, which have a small leakage current, thereby avoiding the leakage of the N1 node through the first transistor T1 and the second transistor T2 in the light-emitting stage. Meanwhile, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors, for example, P-type low-temperature polysilicon transistors, which have a high carrier mobility, thereby facilitating the realization of a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal Vinit1 and the second initial signal terminal Vinit2 can output the same or different voltage signals according to actual conditions.

[0048] Figure 3 A timing diagram of each node in a driving method of an exemplary pixel circuit 200 according to an embodiment of the present application is shown.

[0049] As shown in FIG. 2, the pixel circuit 200 includes a first initial signal terminal Vinit1, a second initial signal terminal Vinit2, a first reset signal terminal Re1, a second reset signal terminal Re2, a first driving signal terminal G1, a second driving signal terminal G2, a data signal terminal Data, a light-emitting control signal terminal EM, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first transistor T1, a second transistor T2, and a light-emitting unit 120. Figure 3 As shown in FIG. 3, G1 represents the timing of the first driving signal terminal G1, G2 represents the timing of the second driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the light-emitting control signal terminal EM, and Data represents the timing of the data signal terminal Data. The driving method of the pixel circuit 200 can include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light-emitting stage t4. In the first reset stage t1, the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N1. In the compensation stage t2, the first driving signal terminal G1 outputs a high-level signal, the second driving signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Data outputs a driving signal to write a voltage Vdata+Vth (i.e., the sum of the voltage Vdata and Vth) to the node N1, where Vdata is the voltage of the driving signal and Vth is the threshold voltage of the driving transistor T3. In the second reset stage t3, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6. In the light-emitting stage t4, the light-emitting control signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit 120 to emit light under the action of the voltage Vdata+Vth stored in the storage capacitor C.

[0050] It should be noted that, in the embodiments of this application, each pixel circuit can, in addition to being able to... Figure 2 In addition to the 7T1C (i.e., seven transistors and one capacitor) structure shown, other structures including other numbers of transistors are also possible, such as 2T1C, 3T1C, 4T1C, 5T1C, 6T1C or 7T1C structures. This application does not limit the embodiments to this.

[0051] like Figure 3 As shown, during the driving of the pixel circuit 200, both data writing and Vth compensation occur in the compensation phase t2. Simultaneous Vth compensation and data writing can lead to a conflict in time resources. The compensation process requires sufficient time to accurately extract and store the Vth value, while data writing also requires enough time to ensure accurate data transmission and storage. If both occur simultaneously, neither may be able to complete within the limited time, thus affecting the display effect.

[0052] Figure 4A A schematic diagram of the structure of an exemplary pixel circuit 400 according to an embodiment of this application is shown.

[0053] like Figure 4A As shown, in some embodiments, the pixel circuit 400 may include a driving unit 402, a first storage capacitor 404, a light-emitting unit 406, a first switching unit 408, a second switching unit 410, a third switching unit 412, a fourth switching unit 414, and a fifth switching unit 416. The first switching unit 408 is electrically coupled to a first reset signal terminal Vref and a first terminal of the first storage capacitor 404; the second switching unit 410 is electrically coupled to a data signal terminal Data and a first terminal of the first storage capacitor 404; the third switching unit 412 is electrically coupled to the light-emitting unit 406 and a second terminal of the first storage capacitor; the light-emitting unit 406 is electrically coupled to a first power supply terminal VSS; the fourth switching unit 414 is electrically coupled to a second power supply terminal VDD and the driving unit 402; the driving unit 402 is electrically coupled to a first terminal and a second terminal of the first storage capacitor 404; and the fifth switching unit 416 is electrically coupled to an initial signal terminal Vinit and a second terminal of the first storage capacitor 404. The first switching unit 408, the second switching unit 410, the driving unit 402 and the first storage capacitor 404 are respectively connected to node N1, the driving unit 402, the first storage capacitor 404, the third switching unit 412 and the fifth switching unit 416 are respectively connected to node N2, and the third switching unit 412 is also connected to node N3.

[0054] Figure 4B An equivalent circuit diagram of an exemplary pixel circuit 420 according to an embodiment of this application is shown. In some embodiments, pixel circuit 400 may be pixel circuit 420.

[0055] likeFigure 4B As shown in some embodiments, the driving unit 402 can include a first transistor T1, the first switch unit 408 can include a second transistor T2, the third switch unit 412 can include a third transistor T3, the second switch unit 410 can include a fourth transistor T4, the fourth switch unit 414 can include a fifth transistor T5, and the fifth switch unit 416 can include a sixth transistor T6. The first storage capacitor 404 can be a first storage capacitor Cst1.

[0056] The control electrode of the first transistor T1 is electrically coupled with the first electrode of the fourth transistor T4, the first end of the first storage capacitor Cst1 and the first electrode of the second transistor T2, the first electrode of the first transistor T1 is electrically coupled with the second end of the first storage capacitor Cst1, the first electrode of the third transistor T3 and the first electrode of the sixth transistor T6, and the second electrode of the first transistor T1 is electrically coupled with the first electrode of the fifth transistor T5.

[0057] The second electrode of the second transistor T2 is electrically coupled with a first reset signal terminal Vref, and the control electrode of the second transistor T2 is electrically coupled with a first driving signal terminal G1.

[0058] The second electrode of the third transistor T3 is electrically coupled with the light emitting unit 406, the light emitting unit 406 is electrically coupled with a first power supply terminal VSS, and the control electrode of the third transistor T3 is electrically coupled with a first light emitting control signal terminal EM1.

[0059] The second electrode of the fourth transistor T4 is electrically coupled with a data signal terminal Data, and the control electrode of the fourth transistor T4 is electrically coupled with a second driving signal terminal G2.

[0060] The second electrode of the fifth transistor T5 is electrically coupled with a second power supply terminal VDD, and the control electrode of the fifth transistor T5 is electrically coupled with a second light emitting control signal terminal EM2.

[0061] The second electrode of the sixth transistor T6 is electrically coupled with an initial signal terminal Vinit, and the control electrode of the sixth transistor T6 is electrically coupled with a second reset signal terminal Reset.

[0062] Figure 4C A structure diagram of an exemplary pixel circuit 440 according to an embodiment of the present application is shown.

[0063] As Figure 4C shown, in some embodiments, the pixel circuit 440 can include a second storage capacitor 442, the first end of the second storage capacitor 442 is electrically coupled with the second power supply terminal VDD, and the second end of the second storage capacitor 442 is electrically coupled with the driving unit 402.

[0064] Figure 4DAn equivalent circuit diagram of an exemplary pixel circuit 460 according to an embodiment of this application is shown. In some embodiments, pixel circuit 440 may be pixel circuit 460.

[0065] like Figure 4D As shown, in some embodiments, the first terminal of the second storage capacitor 442 is electrically coupled to the second power supply terminal VDD, and the second terminal of the second storage capacitor 442 is electrically coupled to the first terminal of the first transistor T1. The second storage capacitor 442 may be a second storage capacitor Cst2.

[0066] Figure 5 Timing diagrams of nodes in a driving method of an exemplary pixel circuit 400 or pixel circuit 420 according to embodiments of this application are shown.

[0067] like Figure 5 As shown, G1 represents the timing of the first driving signal terminal G1, G2 represents the timing of the second driving signal terminal G2, Reset represents the timing of the second reset signal terminal Reset, EM1 represents the timing of the first light emission control signal terminal EM1, and EM2 represents the timing of the second light emission control signal terminal EM2. The driving method of pixel circuit 400 or pixel circuit 420 may include an initialization phase t1, a compensation phase t2, a data writing phase t3, and a light emission phase t4. In the initialization phase t1: the first driving signal terminal G1 outputs a high-level signal, the second transistor T2 is turned on, and the first reset signal terminal Vref inputs a reset signal to node N1; the second reset signal terminal Reset outputs a high-level signal, the sixth transistor T6 is turned on, and the initial signal terminal Vinit inputs an initial signal to node N2. During compensation phase t2: The first drive signal terminal G1 outputs a high-level signal, the second light-emitting control signal terminal EM2 outputs a high-level signal, the second transistor T2 and the fifth transistor T5 are turned on, and simultaneously the first reset signal terminal Vref outputs a reset signal to write voltage Vref (the voltage of the reset signal) to node N1. The second power supply terminal VDD outputs a drive signal to write voltage Vref-Vth (the difference between voltages Vref and Vth) to node N2, where Vth is the threshold voltage of the first transistor T1 (the drive transistor). During data writing phase t3: The second drive signal terminal G2 outputs a high-level signal, the fourth transistor T4 is turned on, and the data signal terminal Data outputs a drive signal to write data voltage Vdata (the voltage of the data signal) to node N1. At this time, the voltage change at node N2 is Vdata-Vref, and the voltage at node N2 is Vref-Vth+Vdata-Vref, i.e., Vdata-Vth. During the light-emitting stage t4: the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2 output high-level signals, the third transistor T3 and the fifth transistor T5 are turned on, and the first transistor T1 drives the light-emitting unit 406 to emit light under the action of the voltage of the first storage capacitor Cst1.

[0068] It should be noted that the timing of the driving method of the pixel circuit 440 or 460 is similar to that of the pixel circuit 400 or 420, and will not be repeated here. For the data writing stage t3 of the pixel circuit 440 or 460, since the second storage capacitor Cst2 is provided in the pixel circuit 440 or 460, the voltage variation of the node N2 is wherein C1 represents the capacitance value of the first storage capacitor Cst1, C2 represents the capacitance value of the second storage capacitor Cst2, and the voltage of the node N2 is That is Therefore, due to the provision of the second storage capacitor Cst2, a part of the Vref voltage is reserved, so that the voltage of the node N2 is more sufficient.

[0069] Figure 6A A schematic diagram of an example display substrate 600 according to an embodiment of the present application is shown. The pixel circuits 400, 420, 440, 460 can be applied to the display substrate 600.

[0070] As Figure 6A shown, in some embodiments, the display substrate 600 can include a substrate substrate 602; a driving circuit layer 604 provided on the substrate substrate 602 and including a plurality of pixel circuits arranged in an array, wherein the pixel circuit can be 400, 420, 440, 460. The pixel circuit includes a first transistor T1, a second transistor T2 and a third transistor T3. The display substrate 600 can further include a plurality of sub-pixels arranged in an array and electrically coupled one-to-one with the plurality of pixel circuits, and provided on a side of the driving circuit layer 604 away from the substrate substrate 602. Wherein the driving circuit layer 604 includes a first functional film layer 6042 and a second functional film layer 6044 which are sequentially stacked in a direction away from the substrate substrate 602.

[0071] The first functional film layer 6042 includes the first transistor T1, the second functional film layer 6044 includes the second transistor T2 and the third transistor T3, the first electrode 606 of the second transistor T2 is electrically coupled with the control electrode 608 of the first transistor T1 through the first via, the first electrode 610 of the third transistor T3 is electrically coupled with the first electrode 612 of the first transistor T1 through the second via, and the orthogonal projection of the first transistor T1 on the substrate 602 at least partially overlaps with the orthogonal projection of the second transistor T2 and / or the third transistor T3 on the substrate 602. In this way, the plurality of transistors of the pixel circuit are arranged in different functional film layers (for example, the first functional film layer 6042 and the second functional film layer 6044) and are electrically coupled through the via, effectively reducing the area of the display substrate occupied by the plurality of transistors arranged in the same film layer in the X direction, achieving high resolution of the display panel, and better applying to high-resolution products such as virtual reality (VR) and local free refresh products. In addition, the plurality of transistors arranged in the same film layer are close to each other, and the signals are easily coupled due to parasitic capacitance, and the voltage change easily affects the nodes N1, N2 and N3, such as crosstalk and picture jitter, thereby affecting the display of the picture. At the boundary position of local refresh with different refresh frequencies, it is more likely to cause defects due to coupling voltage effects. Therefore, the plurality of transistors arranged in different film layers can improve the above problems by controlling the distance between the film layers.

[0072] As shown in FIG. 6A, Figure 4B In some embodiments, the pixel circuit can include a first storage capacitor Cst1, a first end of the first storage capacitor Cst1 is electrically coupled with the control electrode of the first transistor T1, and a second end of the first storage capacitor Cst1 is electrically coupled with the first electrode of the first transistor T1. It can be understood that when the first transistor T1 is a double-gate transistor, the first transistor T1 can further include a control electrode 680.

[0073] In the display substrate 600, as shown in FIG. 6A, Figure 6A In some embodiments, the first functional film layer 6042 further includes a first storage capacitor Cst1, and a first conductive layer 614 and a second conductive layer 616 arranged in sequence in a direction away from the substrate 602, a first end 618 of the first storage capacitor Cst1 is located on the first conductive layer 614, a second end 620 of the first storage capacitor Cst1 is located on the second conductive layer 616, the second end 620 of the first storage capacitor Cst1 is electrically coupled with the second electrode 622 of the first transistor T1 through a third via, and the orthogonal projection of the first end 618 of the first storage capacitor Cst1 and the second end 620 of the first storage capacitor Cst1 on the substrate 602 overlaps.

[0074] As shown in FIG. 6A, Figure 4BAs shown, in some embodiments, the control electrode of the first transistor T1 is electrically coupled with the first electrode of the second transistor T2, the first electrode of the first transistor T1 is electrically coupled with the first electrode of the third transistor T3, the second electrode of the second transistor T2 is electrically coupled with the first reset signal terminal Vref, the control electrode of the second transistor T2 is electrically coupled with the first drive signal terminal G1, the second electrode of the third transistor T3 is electrically coupled with the first power supply terminal VSS, and the control electrode of the third transistor T3 is electrically coupled with the first light-emitting control signal terminal EM1.

[0075] In the display substrate 600, as shown, Figure 6A In some embodiments, the display substrate 600 can further include a light-emitting functional layer 624 located on the side of the driving circuit layer 604 away from the substrate 602, and the light-emitting functional layer 624 includes a first electrode 6242. The second functional film layer 6044 further includes a third conductive layer 626 and a fourth conductive layer 628 stacked in sequence in the direction away from the substrate 602, the control electrode 630 of the second transistor T2 and the control electrode 632 of the third transistor T3 are located on the third conductive layer 626, the second electrode 634 of the second transistor T2 and the second electrode 638 of the third transistor T3 are located on the fourth conductive layer 628, and the first electrode 6242 is electrically coupled with the second electrode 638 of the third transistor T3 through a fourth via hole.

[0076] In the display substrate 600, as shown, Figure 6A In some embodiments, the second transistor T2 includes a first active layer 640, the third transistor T3 includes a second active layer 642, the control electrode 630 of the second transistor T2 includes a first sub-control electrode 6302 and a second sub-control electrode 6304, and the control electrode 632 of the third transistor T3 includes a third sub-control electrode 6322 and a fourth sub-control electrode 6324.

[0077] The third conductive layer 626 includes a first sub-conductive layer 6262 and a second sub-conductive layer 6264, the first sub-conductive layer 6262 is located between the first active layer 640 and the first functional film layer 6042, and the second sub-conductive layer 6264 is located between the first active layer 640 and the fourth conductive layer 628. The first sub-control electrode 6302 and the third sub-control electrode 6322 are located on the first sub-conductive layer 6262, and the second sub-control electrode 6304 and the fourth sub-control electrode 6324 are located on the second sub-conductive layer 6264.

[0078] In the display substrate 600, as shown, Figure 6AAs shown, in some embodiments, the pixel circuit further includes a fourth transistor T4, and the first functional film layer 6042 further includes the fourth transistor T4 and a fifth conductive layer 644 and a sixth conductive layer 646 sequentially stacked on the side of the second conductive layer 616 away from the substrate 602. The fourth transistor T4 includes a third active layer 648, which is located between the first conductive layer 614 and the substrate 602. The control electrode 650 of the fourth transistor T4 is located in the first conductive layer 614, the second electrode 654 of the fourth transistor T4 is located in the fifth conductive layer 644, and the first electrode 652 of the fourth transistor T4 is located in the sixth conductive layer 646. The first electrode 652 of the fourth transistor T4 is electrically coupled to the third active layer 648 through a fifth via, and the second electrode 654 of the fourth transistor T4 is electrically coupled to the third active layer 648 through a sixth via.

[0079] like Figure 4B As shown, in some embodiments, the first terminal 652 of the fourth transistor T4 is electrically coupled to the control terminal of the first transistor T1, the second terminal of the fourth transistor T4 is electrically coupled to the data signal terminal Data, and the control terminal of the fourth transistor T4 is electrically coupled to the second drive signal terminal G2.

[0080] In the display substrate 600, such as Figure 6A As shown, in some embodiments, the first electrode 652 of the fourth transistor T4 is electrically coupled to the control electrode 608 of the first transistor T1 through a seventh via, and the first electrode 606 of the second transistor T2 is electrically coupled to the first electrode 652 of the fourth transistor T4 through an eighth via.

[0081] like Figure 6A As shown, in some embodiments, the control electrode 608 of the first transistor T1 is multiplexed as the first terminal 618 of the first storage capacitor Cst1, and the first electrode 612 of the first transistor T1 is multiplexed as the second terminal 620 of the first storage capacitor Cst1. This eliminates the need for an additional first terminal 618 of the first storage capacitor Cst1, effectively saving space.

[0082] like Figure 6A As shown, in some embodiments, the first transistor T1 includes a fourth active layer 656, which is located between the first conductive layer 614 and the substrate 602. The fourth active layer 656 is multiplexed as the second electrode 622 of the first transistor T1, thereby effectively utilizing space.

[0083] Figure 6B A schematic diagram of an exemplary display substrate 700 according to an embodiment of this application is shown.

[0084] like Figure 6BAs shown in FIG. 6, in some embodiments, the first functional film layer 6042 further includes a first signal line 658 and a seventh conductive layer 660, the seventh conductive layer 660 is located between the second conductive layer 616 and the fifth conductive layer 644, the first signal line 658 is located on the seventh conductive layer 660, the first signal line 658 is electrically coupled with the control electrode 608 of the first transistor T1 through a ninth via, the first signal line 658, the first end 618 of the first storage capacitor Cst1 and the second end 620 of the first storage capacitor Cst1 overlap in orthographic projection on the substrate 602. In this way, a capacitor can also be formed between the first signal line 658 and the second end 620 of the first storage capacitor Cst1, thereby effectively shielding noise, reducing crosstalk and improving display stability.

[0085] As shown in FIG. 6, in some embodiments, the pixel circuit further includes a fifth transistor T5, the first electrode of the fifth transistor T5 is electrically coupled with the second electrode of the first transistor T1, the second electrode of the fifth transistor T5 is electrically coupled with the second power supply terminal VDD, and the control electrode of the fifth transistor T5 is electrically coupled with the second light-emitting control signal terminal EM2. Figure 4B As shown in FIG. 6, in some embodiments, the pixel circuit further includes a fifth transistor T5, the first electrode of the fifth transistor T5 is electrically coupled with the second electrode of the first transistor T1, the second electrode of the fifth transistor T5 is electrically coupled with the second power supply terminal VDD, and the control electrode of the fifth transistor T5 is electrically coupled with the second light-emitting control signal terminal EM2.

[0086] Figure 6A As shown in FIG. 6, in some embodiments, the first functional film layer 6042 further includes a fifth transistor T5, the first electrode 662 of the fifth transistor T5 is located on the fifth conductive layer 644, the control electrode 664 of the fifth transistor T5 is located on the first conductive layer 614, the fifth transistor T5 includes a fifth active layer 666, the fifth active layer 666 is located between the first conductive layer 614 and the substrate 602, the first electrode 662 of the fifth transistor T5 is electrically coupled with the fifth active layer 666 through a tenth via, and the fifth active layer 666 is multiplexed as the second electrode 668 of the fifth transistor T5, thereby effectively saving space.

[0087] As shown in FIG. 6, in some embodiments, the pixel circuit further includes a fifth transistor T5, the first electrode of the fifth transistor T5 is electrically coupled with the second electrode of the first transistor T1, the second electrode of the fifth transistor T5 is electrically coupled with the second power supply terminal VDD, and the control electrode of the fifth transistor T5 is electrically coupled with the second light-emitting control signal terminal EM2. Figure 4B As shown in FIG. 6, in some embodiments, the pixel circuit further includes a fifth transistor T5, the first electrode of the fifth transistor T5 is electrically coupled with the second electrode of the first transistor T1, the second electrode of the fifth transistor T5 is electrically coupled with the second power supply terminal VDD, and the control electrode of the fifth transistor T5 is electrically coupled with the second light-emitting control signal terminal EM2.

[0088] Figure 6A ​​As shown, in some embodiments, the first functional film layer 6042 further includes a sixth transistor T6. The first electrode 670 of the sixth transistor T6 is located in the fifth conductive layer 644, and the control electrode 672 of the sixth transistor T6 is located in the first conductive layer 614. The sixth transistor T6 includes a sixth active layer 674, which is located between the first conductive layer 614 and the substrate 602. The first electrode 670 of the sixth transistor T6 is electrically coupled to the sixth active layer 674 through an eleventh via. The sixth active layer 674 is multiplexed as the second electrode 676 of the sixth transistor T6, thereby effectively utilizing space.

[0089] In some embodiments, the first electrode 612 of the first transistor T1 is the source, and the second electrode 622 of the first transistor T1 is the drain. This allows the pixel circuit to implement a source-following driving mode, improving the stability of the signal output.

[0090] In some embodiments, the second transistor T2 and the third transistor T3 are oxide transistors, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are low-temperature polycrystalline silicon transistors. Oxide transistors have high field-effect mobility, which enables them to meet higher frame rates and resolution requirements when driving high-resolution display panels. In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are N-type metal-oxide-semiconductor field-effect transistors (NMOS transistors). NMOS transistors have low on-resistance and low power consumption.

[0091] like Figure 4D As shown, in some embodiments, the pixel circuit further includes a second storage capacitor Cst2, the first end of which is electrically coupled to the second power supply terminal VDD, and the second end of which is electrically coupled to the first terminal of the first transistor T1.

[0092] In some embodiments, the first functional film layer 6042 further includes a second storage capacitor Cst2 and an eighth conductive layer located on the side of the second conductive layer 616 away from the substrate 602. The first end of the second storage capacitor Cst2 is located in the eighth conductive layer, and the second end 620 of the first storage capacitor Cst1 is multiplexed as the second end of the second storage capacitor Cst2. The orthographic projections of the first end of the second storage capacitor Cst2 and the second end 620 of the first storage capacitor Cst1 on the substrate 602 overlap. The first end of the second storage capacitor Cst2 is electrically coupled to the first terminal 662 of the fifth transistor T5. The arrangement of the second storage capacitor Cst2 makes the voltage at node N2 more sufficient.

[0093] It should be noted that, as Figure 6AAs shown, taking the second transistor T2 as an example, the second electrode 634 of the second transistor T2 can be electrically coupled with the first active layer 640 through a signal line 678, so as to avoid too long wiring leading to impedance, or can be directly electrically coupled with the first active layer 640 without the signal line 678, which is not limited in the embodiments of the present application. The electrodes of other transistors are the same, which will not be described herein.

[0094] In the manufacturing of the display substrate 600, a substrate can be provided, which can be a glass substrate, a polyimide layer (PI) is deposited on the glass substrate, in some embodiments, the thickness of the polyimide layer can be 7-10 μm, as a process substrate, a first buffer layer (Buffer0) is deposited thereon, the first buffer layer is composed of silicon nitride (SiNx) with a thickness of and silicon oxide (SiOx) with a thickness of , amorphous silicon (a-Si) (with a thickness of ) is deposited thereon, N-type silicon (N-Si) is formed through a patterning process, the pattern of the active layer (Poly) is formed through exposure, development and etching (for making switch transistors (SWTFT) and drive transistors (DTFT)), a small amount of particles is injected to adjust the threshold voltage (Vth Doping) of the transistor through a doping process.

[0095] The first insulating layer (GI1) (the manufacturing material can be SiOx, and the thickness can be ) is deposited on the active layer, the first gate metal (the control electrode of the first transistor) (the manufacturing material can be molybdenum (Mo), and the thickness can be ) is deposited thereon, the first gate metal pattern (the gate of the sixth transistor / the fourth transistor / the first transistor / the fifth transistor and the signal line) is formed through a communication process, a large amount of particles is injected to form a better ohmic contact.

[0096] The second insulating layer (GI2) (the manufacturing material can be SiNx, and the thickness can be for the insulating layer of the storage capacitor) is deposited, the via pattern between the first insulating layer and the second insulating layer is formed through the first insulating layer and the second insulating layer, and a patterning process is used for connecting the active layer.

[0097] The second gate metal (the first electrode of the fifth transistor) (the manufacturing material can be Mo, and the thickness can be ) is deposited on the second insulating layer, the pattern is formed through a patterning process (the first electrode of the sixth transistor / the fifth transistor and the drain electrode of the first transistor are made, and are connected to the active layer through the via; at the same time, the first storage capacitor is formed between N1 and N2).

[0098] Depositing a third insulating layer (GI3) (the material can be SiNx, and the thickness can be 1000A) on the second gate metal. Depositing a fourth insulating layer (GI4) (the material can be SiNx, and the thickness can be 1000A) on the third gate metal.

[0099] Depositing a third gate metal (the control electrode of the first transistor) (the material can be Mo, and the thickness can be 1000A) on the third insulating layer. Depositing a fourth insulating layer (GI4) (the material can be SiNx, and the thickness can be 1000A) on the third gate metal.

[0100] Depositing a fourth insulating layer (GI4) (the material can be SiNx, and the thickness can be 1000A) on the third gate metal. Depositing a fourth insulating layer (GI4) (the material can be SiNx, and the thickness can be 1000A) on the third gate metal.

[0101] Depositing a fourth insulating layer (GI4) (the material can be SiNx, and the thickness can be 1000A) on the third gate metal. Depositing a fourth insulating layer (GI4) (the material can be SiNx, and the thickness can be 1000A) on the third gate metal.

[0102] Depositing a fourth insulating layer (GI4) (the material can be SiNx, and the thickness can be 1000A) on the third gate metal. Depositing a fourth insulating layer (GI4) (the material can be SiNx, and the thickness can be 1000A) on the third gate metal.

[0103] Depositing a fourth insulating layer (GI4) (the material can be SiNx, and the thickness can be 1000A) on the third gate metal. Depositing a fourth insulating layer (GI4) (the material can be SiNx, and the thickness can be 1000A) on the third gate metal.

[0104] A first planarization layer (PLN) (the material can be PI, and the thickness can be 1.5 μm) is formed on the first electrode of the fourth transistor by a first patterning process, a second buffer layer (Buffer1) (the material can be SiNx, and the thickness can be 100 nm) is deposited thereon, a fourth gate metal (the material can be Mo, and the thickness can be 100 nm) is deposited thereon by a second patterning process, and a pattern of the fourth gate metal is formed by a first patterning process to serve as a bottom gate (for example, a first sub-control electrode) of the second transistor and the third transistor. A fifth insulating layer (GI5) (the material can be SiOx, and the thickness can be 100 nm) is deposited on the fourth gate metal, a via hole is formed, and a pattern of the via hole is formed by a first patterning process (for connecting the first electrode of the fourth transistor, i.e., the N1 node and the N2 node, to the indium gallium zinc oxide (IGZO) through the via hole).

[0105] A sixth insulating layer (GI6) (the material can be SiOx, and the thickness can be 100 nm) is deposited on the indium gallium zinc oxide, a fifth gate metal (the material can be Mo, and the thickness can be 100 nm) is deposited thereon, and a pattern of the fifth gate metal is formed by a first patterning process to serve as a top gate (for example, a second sub-control electrode) of the second transistor and the third transistor.

[0106] An interlayer dielectric (the material can be SiNx, and the thickness can be 100 nm) is deposited on the fifth gate metal, and a pattern (for connecting the second electrode of the second transistor and the third transistor to the IGZO) is formed by a first patterning process. A third gate metal (the material can be Al, and the thickness can be 100 nm) is deposited on the interlayer dielectric, and a pattern of the second electrode of the second transistor and the third transistor is formed by a first patterning process to connect the IGZO of the second transistor and the third transistor through a via hole.

[0107]

[0108]

[0109]

[0110] ​​​​​​​​​A second planarization layer (PLN2 layer) is formed on the second electrodes of the second transistor and the third transistor by a patterning process (the material can be PI, and the thickness can be 1.5-1.7 μm), and a via is formed on the second electrode of the second transistor and the third transistor for connection with a signal line.

[0111] A fourth gate metal is deposited on the second planarization layer (the material can be Al, and the thickness can be ), a signal line pattern is formed by a patterning process, and the second electrode of the second transistor and the third transistor below is connected through the via of the second planarization layer.

[0112] A third planarization layer is formed on the signal line by a patterning process (the material can be PI, and the thickness can be 1.7-2.1 μm), and a via is formed on the second electrode of the third transistor for connection with the first electrode (e.g., anode) below.

[0113] A first electrode is deposited on the third planarization layer (the material can be indium tin oxide / silver / indium tin oxide (ITO / Ag / ITO), and the thickness can be ), an anode pattern is formed by a patterning process, and the third transistor below is connected through the via of the third planarization layer.

[0114] Finally, a pixel definition layer (PDL) opening is formed on the anode by exposure, and the R / G / B pixel definition layer is formed according to a certain opening ratio.

[0115] Figure 7 A flowchart of a preparation method 710 of an exemplary display substrate according to an embodiment of the present application is shown. The preparation method 710 can include the following steps.

[0116] In step 712, a substrate is provided.

[0117] In step 714, a driving circuit layer is formed on the substrate, and the driving circuit layer includes a plurality of pixel circuits arranged in an array, and each pixel circuit includes a first transistor, a second transistor, and a third transistor.

[0118] In step 716, a plurality of sub-pixels arranged in an array are formed on a side of the driving circuit layer away from the substrate, and the plurality of sub-pixels are electrically coupled to the plurality of pixel circuits one by one.

[0119] The driving circuit layer comprises a first functional film layer and a second functional film layer which are sequentially stacked in a direction away from the substrate base plate, the first functional film layer comprises a first transistor, and the second functional film layer comprises a second transistor and a third transistor, a first electrode of the second transistor is electrically coupled to a control electrode of the first transistor through a first via, a first electrode of the third transistor is electrically coupled to a first electrode of the first transistor through a second via, and a projection of the first transistor on the substrate base plate at least partially overlaps with a projection of the second transistor and / or the third transistor on the substrate base plate.

[0120] In some embodiments, the pixel circuit comprises a first storage capacitor, a first end of the first storage capacitor is electrically coupled to the control electrode of the first transistor, and a second end of the first storage capacitor is electrically coupled to the first electrode of the first transistor; the first functional film layer further comprises the first storage capacitor and a first conductive layer and a second conductive layer which are sequentially stacked in a direction away from the substrate base plate, the first end of the first storage capacitor is located in the first conductive layer, the second end of the first storage capacitor is located in the second conductive layer, the second end of the first storage capacitor is electrically coupled to the second electrode of the first transistor through a third via, and a projection of the first end of the first storage capacitor and the second end of the first storage capacitor on the substrate base plate overlaps.

[0121] In some embodiments, the control electrode of the first transistor is electrically coupled to the first electrode of the second transistor, the first electrode of the first transistor is electrically coupled to the first electrode of the third transistor, the second electrode of the second transistor is electrically coupled to the first reset signal end, the control electrode of the second transistor is electrically coupled to the first driving signal end, the second electrode of the third transistor is electrically coupled to the first power supply end, and the control electrode of the third transistor is electrically coupled to the first light-emitting control signal end.

[0122] The preparation method further comprises:

[0123] The light-emitting functional layer is formed on a side of the driving circuit layer away from the substrate base plate, and the light-emitting functional layer comprises a first electrode; the second functional film layer further comprises a third conductive layer and a fourth conductive layer which are sequentially stacked in a direction away from the substrate base plate, the control electrode of the second transistor and the control electrode of the third transistor are located in the third conductive layer, the second electrode of the second transistor and the second electrode of the third transistor are located in the fourth conductive layer, and the first electrode is electrically coupled to the second electrode of the third transistor through a fourth via.

[0124] In some embodiments, the second transistor comprises a first active layer, the third transistor comprises a second active layer, the control electrode of the second transistor comprises a first sub-control electrode and a second sub-control electrode, the control electrode of the third transistor comprises a third sub-control electrode and a fourth sub-control electrode; the third conductive layer comprises a first sub-conductive layer and a second sub-conductive layer, the first sub-conductive layer is located between the first active layer and the first functional film layer, and the second sub-conductive layer is located between the first active layer and the fourth conductive layer; the first sub-control electrode and the third sub-control electrode are located in the first sub-conductive layer, and the second sub-control electrode and the fourth sub-control electrode are located in the second sub-conductive layer.

[0125] In some embodiments, the pixel circuit further comprises a fourth transistor, the first functional film layer further comprises the fourth transistor and a fifth conductive layer and a sixth conductive layer which are sequentially stacked on a side of the second conductive layer away from the substrate substrate; the fourth transistor comprises a third active layer, the third active layer is located between the first conductive layer and the substrate substrate; the control electrode of the fourth transistor is located in the first conductive layer, the first electrode of the fourth transistor is located in the sixth conductive layer, and the second electrode of the fourth transistor is located in the fifth conductive layer; the first electrode of the fourth transistor is electrically coupled to the third active layer through a fifth via, and the second electrode of the fourth transistor is electrically coupled to the third active layer through a sixth via.

[0126] In some embodiments, the first electrode of the fourth transistor is electrically coupled to the control electrode of the first transistor, the second electrode of the fourth transistor is electrically coupled to the data signal end, and the control electrode of the fourth transistor is electrically coupled to the second drive signal end; the first electrode of the fourth transistor is electrically coupled to the control electrode of the first transistor through a seventh via, and the first electrode of the second transistor is electrically coupled to the first electrode of the fourth transistor through an eighth via.

[0127] In some embodiments, the control electrode of the first transistor is multiplexed as a first end of a first storage capacitor, and the first electrode of the first transistor is multiplexed as a second end of the first storage capacitor.

[0128] In some embodiments, the first transistor comprises a fourth active layer, the fourth active layer is located between the first conductive layer and the substrate substrate, and the fourth active layer is multiplexed as the second electrode of the first transistor.

[0129] In some embodiments, the first functional film layer further comprises a first signal line and a seventh conductive layer, the seventh conductive layer is located between the second conductive layer and the fifth conductive layer, the first signal line is located in the seventh conductive layer, and the first signal line is electrically coupled to the control electrode of the first transistor through a ninth via; the first signal line, the first end of the first storage capacitor, and the second end of the first storage capacitor overlap in orthographic projection on the substrate substrate.

[0130] In some embodiments, the pixel circuit further comprises a fifth transistor, a first electrode of the fifth transistor is electrically coupled with a second electrode of the first transistor, a second electrode of the fifth transistor is electrically coupled with the second power supply terminal, and a control electrode of the fifth transistor is electrically coupled with the second light-emitting control signal terminal; the first functional film layer further comprises the fifth transistor, the first electrode of the fifth transistor is located on the fifth conductive layer, the control electrode of the fifth transistor is located on the first conductive layer, the fifth transistor comprises a fifth active layer, the fifth active layer is located between the first conductive layer and the substrate substrate, the first electrode of the fifth transistor is electrically coupled with the fifth active layer through the tenth via hole, and the fifth active layer is multiplexed as the second electrode of the fifth transistor.

[0131] In some embodiments, the pixel circuit further comprises a sixth transistor, a first electrode of the sixth transistor is electrically coupled with the first electrode of the third transistor, a second electrode of the sixth transistor is electrically coupled with the initial signal terminal, and a control electrode of the sixth transistor is electrically coupled with the second reset signal terminal; the first functional film layer further comprises the sixth transistor, the first electrode of the sixth transistor is located on the fifth conductive layer, the control electrode of the sixth transistor is located on the first conductive layer, the sixth transistor comprises a sixth active layer, the sixth active layer is located between the first conductive layer and the substrate substrate, the first electrode of the sixth transistor is electrically coupled with the sixth active layer through the eleventh via hole, and the sixth active layer is multiplexed as the second electrode of the sixth transistor.

[0132] In some embodiments, the first electrode of the first transistor is a source electrode, and the second electrode of the first transistor is a drain electrode.

[0133] In some embodiments, the second transistor and the third transistor comprise oxide transistors, and the first transistor, the fourth transistor, the fifth transistor and the sixth transistor comprise low-temperature polysilicon transistors.

[0134] In some embodiments, the pixel circuit further comprises a second storage capacitor, a first terminal of the second storage capacitor is electrically coupled with the second power supply terminal, and a second terminal of the second storage capacitor is electrically coupled with the first electrode of the first transistor; the first functional film layer further comprises the second storage capacitor and an eighth conductive layer located on a side of the second conductive layer away from the substrate substrate, the first terminal of the second storage capacitor is located on the eighth conductive layer, the second terminal of the first storage capacitor is multiplexed as the second terminal of the second storage capacitor, the first terminal of the second storage capacitor and the second terminal of the first storage capacitor overlap in orthographic projection on the substrate substrate, and the first terminal of the second storage capacitor is electrically coupled with the first electrode of the fifth transistor.

[0135] The application provides a display substrate, a pixel circuit and a display device. The display substrate comprises a driving circuit layer, and a pixel circuit in the driving circuit layer comprises a first transistor, a second transistor and a third transistor; wherein the driving circuit layer comprises a first functional film layer and a second functional film layer which are sequentially stacked in a direction away from a substrate substrate, the first functional film layer comprises the first transistor, the second functional film layer comprises the second transistor and the third transistor, a first electrode of the second transistor is electrically coupled with a control electrode of the first transistor through a first via, a first electrode of the third transistor is electrically coupled with the first electrode of the first transistor through a second via, and a projection of the first transistor on the substrate substrate at least partially overlaps with a projection of the second transistor and / or the third transistor on the substrate substrate. The pixel circuit is stacked in different functional film layers and electrically coupled through the via, so that high resolution of the display panel can be achieved.

[0136] It should be understood by those of ordinary skill in the art that the above discussion of any of the embodiments is merely exemplary and is not intended to suggest the scope of the application (including the claims) is limited to these examples; under the concept of the present application, the above embodiments or technical features among different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of the embodiments of the present application as described above, which are not provided in details for the sake of brevity.

[0137] In addition, in order to simplify the description and discussion, and so as not to make the embodiments of the present application difficult to understand, the known power / ground connections of integrated circuit (IC) chips and other components can or can not be shown in the provided drawings. In addition, the devices can be shown in the form of block diagrams in order to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented (i.e. these details should be fully within the understanding of those skilled in the art). Where specific details (e.g. circuits) are set forth in order to describe an exemplary embodiment of the present application, it will be apparent to those skilled in the art that the embodiments of the present application can be practiced without these specific details or with variations on these specific details. Therefore, these descriptions should be considered as illustrative rather than limiting.

[0138] Although the present application has been described in conjunction with the specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g. dynamic RAM (DRAM)) can use the embodiments discussed.

[0139] Embodiments of the present application are intended to embrace all such alterations, modifications, and variations that fall within the broad scope of the appended claims. Accordingly, any one or more features of a given embodiment are intended to be illustrative only and not limiting of the scope of the application.

Claims

1. A display substrate, comprising: a substrate substrate; a drive circuit layer disposed on the substrate substrate, comprising a plurality of pixel circuits arranged in an array, the pixel circuit comprising a first transistor, a second transistor and a third transistor; a plurality of sub-pixels arranged in an array, electrically coupled to the plurality of pixel circuits one by one, and disposed on a side of the drive circuit layer away from the substrate substrate; wherein the drive circuit layer comprises a first functional film layer and a second functional film layer sequentially stacked in a direction away from the substrate substrate; the first functional film layer comprises the first transistor, and the second functional film layer comprises the second transistor and the third transistor, a first electrode of the second transistor is electrically coupled to a control electrode of the first transistor through a first via, a first electrode of the third transistor is electrically coupled to a first electrode of the first transistor through a second via, and a normal projection of the first transistor on the substrate substrate at least partially overlaps with a normal projection of the second transistor and / or the third transistor on the substrate substrate. 2.The display substrate of claim 1, wherein, the pixel circuit comprises a first storage capacitor, a first end of the first storage capacitor is electrically coupled to the control electrode of the first transistor, and a second end of the first storage capacitor is electrically coupled to the first electrode of the first transistor; the first functional film layer further comprises the first storage capacitor, and a first conductive layer and a second conductive layer sequentially stacked in a direction away from the substrate substrate, the first end of the first storage capacitor is located in the first conductive layer, the second end of the first storage capacitor is located in the second conductive layer, the second end of the first storage capacitor is electrically coupled to a second electrode of the first transistor through a third via, and a normal projection of the first end of the first storage capacitor and the second end of the first storage capacitor on the substrate substrate overlaps. 3.The display substrate of claim 1, wherein, a control electrode of the first transistor is electrically coupled to a first electrode of the second transistor, a first electrode of the first transistor is electrically coupled to a first electrode of the third transistor, a second electrode of the second transistor is electrically coupled to a first reset signal terminal, a control electrode of the second transistor is electrically coupled to a first drive signal terminal, a second electrode of the third transistor is electrically coupled to a first power supply terminal, and a control electrode of the third transistor is electrically coupled to a first light-emitting control signal terminal; the display substrate further comprises: a light-emitting functional layer located on a side of the drive circuit layer away from the substrate substrate, comprising a first electrode; the second functional film layer further comprises a third conductive layer and a fourth conductive layer sequentially stacked in a direction away from the substrate substrate, a control electrode of the second transistor and a control electrode of the third transistor are located in the third conductive layer, a second electrode of the second transistor and a second electrode of the third transistor are located in the fourth conductive layer, and the first electrode is electrically coupled to the second electrode of the third transistor through a fourth via. 4.The display substrate of claim 3, wherein, the second transistor comprises a first active layer, the third transistor comprises a second active layer, a control electrode of the second transistor comprises a first sub-control electrode and a second sub-control electrode, and a control electrode of the third transistor comprises a third sub-control electrode and a fourth sub-control electrode; The third conductive layer comprises a first sub-conductive layer and a second sub-conductive layer, the first sub-conductive layer is located between the first active layer and the first functional film layer, and the second sub-conductive layer is located between the first active layer and the fourth conductive layer. The first sub-control electrode and the third sub-control electrode are located in the first sub-conductive layer, and the second sub-control electrode and the fourth sub-control electrode are located in the second sub-conductive layer. 5.The display substrate of claim 2, wherein, The pixel circuit further comprises a fourth transistor, and the first functional film layer further comprises the fourth transistor and a fifth conductive layer and a sixth conductive layer which are sequentially stacked on a side of the second conductive layer away from the substrate substrate. The fourth transistor comprises a third active layer, and the third active layer is located between the first conductive layer and the substrate substrate. The control electrode of the fourth transistor is located in the first conductive layer, the first electrode of the fourth transistor is located in the sixth conductive layer, and the second electrode of the fourth transistor is located in the fifth conductive layer. The first electrode of the fourth transistor is electrically coupled to the third active layer through a fifth via, and the second electrode of the fourth transistor is electrically coupled to the third active layer through a sixth via. 6.The display substrate of claim 5, wherein, The first electrode of the fourth transistor is electrically coupled to the control electrode of the first transistor, the second electrode of the fourth transistor is electrically coupled to a data signal end, and the control electrode of the fourth transistor is electrically coupled to a second driving signal end. The first electrode of the fourth transistor is electrically coupled to the control electrode of the first transistor through a seventh via, and the first electrode of the second transistor is electrically coupled to the first electrode of the fourth transistor through an eighth via. 7.The display substrate of claim 2, wherein, The control electrode of the first transistor is multiplexed as a first end of the first storage capacitor, and the first electrode of the first transistor is multiplexed as a second end of the first storage capacitor. 8.The display substrate of claim 2, wherein, The first transistor comprises a fourth active layer, the fourth active layer is located between the first conductive layer and the substrate substrate, and the fourth active layer is multiplexed as the second electrode of the first transistor. 9.The display substrate of claim 5, wherein, The first functional film layer further comprises a first signal line and a seventh conductive layer, the seventh conductive layer is located between the second conductive layer and the fifth conductive layer, the first signal line is located in the seventh conductive layer, and the first signal line is electrically coupled to the control electrode of the first transistor through a ninth via. The first signal line, the first end of the first storage capacitor and the second end of the first storage capacitor overlap in orthographic projection on the substrate substrate. 10.The display substrate of claim 5, wherein, The pixel circuit further comprises a fifth transistor, the first electrode of the fifth transistor is electrically coupled to the second electrode of the first transistor, the second electrode of the fifth transistor is electrically coupled to a second power supply end, and the control electrode of the fifth transistor is electrically coupled to a second light-emitting control signal end. The first functional film layer further comprises the fifth transistor, a first electrode of the fifth transistor is located on the fifth conductive layer, a control electrode of the fifth transistor is located on the first conductive layer, the fifth transistor comprises a fifth active layer, the fifth active layer is located between the first conductive layer and the substrate substrate, the first electrode of the fifth transistor is electrically coupled with the fifth active layer through a tenth via hole, and the fifth active layer is multiplexed as a second electrode of the fifth transistor. 11.The display substrate of claim 10, wherein, The pixel circuit further comprises a sixth transistor, a first electrode of the sixth transistor is electrically coupled with a first electrode of the third transistor, a second electrode of the sixth transistor is electrically coupled with an initial signal terminal, and a control electrode of the sixth transistor is electrically coupled with a second reset signal terminal. The first functional film layer further comprises the sixth transistor, a first electrode of the sixth transistor is located on the fifth conductive layer, a control electrode of the sixth transistor is located on the first conductive layer, the sixth transistor comprises a sixth active layer, the sixth active layer is located between the first conductive layer and the substrate substrate, the first electrode of the sixth transistor is electrically coupled with the sixth active layer through an eleventh via hole, and the sixth active layer is multiplexed as a second electrode of the sixth transistor. 12.The display substrate of claim 2, wherein, The first electrode of the first transistor is a source electrode, and the second electrode of the first transistor is a drain electrode. 13.The display substrate of claim 11, wherein, The second transistor and the third transistor comprise oxide transistors, and the first transistor, the fourth transistor, the fifth transistor and the sixth transistor comprise low-temperature polysilicon transistors. 14.The display substrate of claim 11, wherein, The pixel circuit further comprises a second storage capacitor, a first end of the second storage capacitor is electrically coupled with the second power supply terminal, and a second end of the second storage capacitor is electrically coupled with the first electrode of the first transistor. The first functional film layer further comprises the second storage capacitor and an eighth conductive layer located on a side of the second conductive layer away from the substrate substrate, the first end of the second storage capacitor is located on the eighth conductive layer, the second end of the first storage capacitor is multiplexed as the second end of the second storage capacitor, the first end of the second storage capacitor and the second end of the first storage capacitor overlap in orthographic projection on the substrate substrate, and the first end of the second storage capacitor is electrically coupled with the first electrode of the fifth transistor.

15. The pixel circuit according to any one of claims 1-14, applied to the display substrate. The pixel circuit comprises a driving unit, a first storage capacitor, a light-emitting unit, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit and a fifth switching unit. The first switching unit is electrically coupled with a first reset signal terminal and a first end of the first storage capacitor. The second switching unit is electrically coupled with a data signal terminal and the first end of the first storage capacitor. The third switching unit is electrically coupled with the light-emitting unit and a second end of the first storage capacitor. The light-emitting unit is electrically coupled with a first power supply terminal. The fourth switching unit is electrically coupled with a second power supply terminal and the driving unit. The driving unit is electrically coupled with the first end of the first storage capacitor and the second end of the first storage capacitor. The fifth switching unit is electrically coupled with an initial signal terminal and the second end of the first storage capacitor.

16. The pixel circuit of claim 15, wherein, The driving unit comprises a first transistor, the first switch unit comprises a second transistor, the third switch unit comprises a third transistor, the second switch unit comprises a fourth transistor, the fourth switch unit comprises a fifth transistor, and the fifth switch unit comprises a sixth transistor; a first electrode of the first transistor is electrically coupled with a first electrode of the fourth transistor, a first terminal of the first storage capacitor and a first electrode of the second transistor, a second electrode of the first transistor is electrically coupled with a second terminal of the first storage capacitor, a first electrode of the third transistor and a first electrode of the sixth transistor, and a second electrode of the first transistor is electrically coupled with a first electrode of the fifth transistor; a second electrode of the second transistor is electrically coupled with the first reset signal terminal, and a control electrode of the second transistor is electrically coupled with the first driving signal terminal; a second electrode of the third transistor is electrically coupled with the light emitting unit, the light emitting unit is electrically coupled with the first power supply terminal, and a control electrode of the third transistor is electrically coupled with the first light emitting control signal terminal; a second electrode of the fourth transistor is electrically coupled with the data signal terminal, and a control electrode of the fourth transistor is electrically coupled with the second driving signal terminal; a second electrode of the fifth transistor is electrically coupled with the second power supply terminal, and a control electrode of the fifth transistor is electrically coupled with the second light emitting control signal terminal; a second electrode of the sixth transistor is electrically coupled with the initial signal terminal, and a control electrode of the sixth transistor is electrically coupled with the second reset signal terminal.

17. The pixel circuit of claim 16, wherein, The pixel circuit further comprises a second storage capacitor, a first terminal of the second storage capacitor is electrically coupled with the second power supply terminal, and a second terminal of the second storage capacitor is electrically coupled with the first electrode of the first transistor.

18. A display device comprising the display substrate according to any one of claims 1-14.

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