Display device

Abstract

A display device includes a substrate including a first well region, a third well region, and a fifth well region; a first gate electrode on the first channel region of the first well region; a third gate electrode on a third channel region of the third well region; a fifth gate electrode on a fifth channel region of the fifth well region; a first gate insulating layer between the first channel region and the first gate electrode; a third gate insulating layer between the third channel region and the third gate electrode; and a fifth gate insulating layer between the fifth channel region and the fifth gate electrode, in which at least two of the first gate insulating layer, the third gate insulating layer, and the fifth gate insulating layer have different thicknesses from each other.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0000070, filed on January 2, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure relate to display devices, and more specifically, to display devices capable of displaying fine grayscale and methods for manufacturing the display device. Background Technology

[0004] A head-mounted display (HMD) is an image display device worn on a user's head in the form of glasses or a helmet to create a focused image at close range in front of the user's eyes. For example, head-mounted displays can enable virtual reality (VR) or augmented reality (AR).

[0005] Head-mounted displays magnify images displayed on small display devices using multiple lenses, and display the magnified images. Therefore, display devices used in head-mounted displays can provide high-resolution images, for example, with a resolution of 3000 PPI (pixels per inch) or higher. For this purpose, organic light-emitting diodes on silicon (OLEDoS), which are high-resolution small organic light-emitting display devices, can be used (e.g., utilized) as display devices applied to head-mounted displays. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are disposed on a semiconductor wafer substrate, on which complementary metal-oxide-semiconductor (CMOS) is disposed.

[0006] The information disclosed in this background section is intended to enhance the understanding of the background technology of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0007] One or more embodiments of this disclosure provide a display device capable of displaying fine grayscale and a method for manufacturing the display device.

[0008] According to one or more embodiments of the present disclosure, a display device includes a substrate including a first well region, a third well region, and a fifth well region; a first source electrode and a first drain electrode in the first well region; a third source electrode and a third drain electrode in the third well region; a fifth source electrode and a fifth drain electrode in the fifth well region; a first gate electrode on a first channel region of the first well region; a third gate electrode on a third channel region of the third well region; a fifth gate electrode on a fifth channel region of the fifth well region; a first gate insulating layer between the first channel region and the first gate electrode; a third gate insulating layer between the third channel region and the third gate electrode; a fifth gate insulating layer between the fifth channel region and the fifth gate electrode; a first electrode connected to the first drain electrode; a light emitting layer on the first electrode; and a second electrode on the light emitting layer, wherein at least two of the first gate insulating layer, the third gate insulating layer, and the fifth gate insulating layer have different thicknesses from each other.

[0009] In one or more embodiments, the third gate insulating layer has a thickness greater than a thickness of the fifth gate insulating layer and a thickness of the first gate insulating layer.

[0010] In one or more embodiments, the display device further includes a first transistor including the first gate electrode, the first source electrode, the first drain electrode, and the first gate insulating layer; a third transistor including the third gate electrode, the third source electrode, the third drain electrode, and the third gate insulating layer; and a first capacitor including the fifth gate electrode, the fifth source electrode, the fifth drain electrode, and the fifth gate insulating layer.

[0011] In one or more embodiments, the third transistor is connected between a driving voltage line and the first source electrode of the first transistor.

[0012] In one or more embodiments, the display device further includes a second transistor connected between a data line and the first gate electrode of the first transistor.

[0013] In one or more embodiments, the second transistor includes a second source electrode and a second drain electrode disposed in a second well region of the substrate; a second gate electrode on a second channel region of the second well region; and a second gate insulating layer between the second channel region and the second gate electrode.

[0014] In one or more embodiments, a thickness of the second gate insulating layer is substantially the same (e.g., substantially equal) as a thickness of the third gate insulating layer.

[0015] In one or more embodiments, the display device further includes a fourth transistor connected between an initialization voltage line and the first drain electrode of the first transistor.

[0016] In one or more embodiments, the fourth transistor includes: a fourth source electrode and a fourth drain electrode disposed in a fourth well region of the substrate; a fourth gate electrode over a fourth channel region of the fourth well region; and a fourth gate insulating layer between the fourth channel region and the fourth gate electrode.

[0017] In one or more embodiments, a thickness of the fourth gate insulating layer is substantially the same (e.g., substantially equal) as a thickness of the third gate insulating layer.

[0018] In one or more embodiments, the display device further includes: a second capacitor connected between the first gate electrode of the first transistor and the first source electrode of the first transistor.

[0019] In one or more embodiments, the second capacitor includes: a sixth source electrode and a sixth drain electrode disposed in a sixth well region of the substrate; a sixth gate electrode over a sixth channel region of the sixth well region; and a sixth gate insulating layer between the sixth channel region and the sixth gate electrode.

[0020] In one or more embodiments, a thickness of the sixth gate insulating layer is substantially the same (e.g., substantially equal) as a thickness of the fifth gate insulating layer.

[0021] In one or more embodiments, the thickness of the sixth gate insulating layer is greater than the thickness of the fifth gate insulating layer.

[0022] In one or more embodiments, the thickness of the sixth gate insulating layer is less than the thickness of the third gate insulating layer.

[0023] In one or more embodiments, in the first pixel and the second pixel adjacent to each other, the first transistor of the first pixel and the first transistor of the second pixel are adjacent to each other.

[0024] In one or more embodiments, in the first pixel and the second pixel adjacent to each other, the first capacitor of the first pixel and the first capacitor of the second pixel are adjacent to each other.

[0025] In one or more embodiments, the first transistor is disposed at one edge of the pixel, and the first capacitor is disposed (e.g., located) at another edge of the pixel.

[0026] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes: forming a first well region, a third well region, and a fifth well region on a substrate; forming a first base insulating layer on a surface (e.g., an entire surface) of the substrate including the first well region, the third well region, and the fifth well region; forming a first photoresist pattern on the first base insulating layer to cover the first well region and the third well region; selectively removing the first base insulating layer using the first photoresist pattern as a mask to form the first base insulating layer having a thickness in the fifth well region that is less (e.g., less than) than a thickness of the first base insulating layer in the first well region and the third well region; removing the first photoresist pattern; forming a second base insulating layer on the first base insulating layer; forming a second photoresist pattern on the second base insulating layer to cover the first well region; and selectively removing the second base insulating layer using the second photoresist pattern as a mask to form the base insulating layer having a first thickness in the first well region, a third thickness in the third well region, and a fifth thickness in the fifth well region, the first thickness being greater than the third thickness and the third thickness being greater than the fifth thickness.

[0027] In one or more embodiments, the method further includes: removing the second photoresist pattern; disposing a first gate electrode on the base insulating layer to overlap the first well region, disposing a third gate electrode on the base insulating layer to overlap the third well region, and disposing a fifth gate electrode on the base insulating layer to overlap the fifth well region; and performing an ion implantation process using the first gate electrode, the third gate electrode, and the fifth gate electrode as masks to form a first low-concentration impurity region in the first well region, a third low-concentration impurity region in the third well region, and a fifth low-concentration impurity region in the fifth well region.

[0028] In one or more embodiments, the method further includes: selectively removing the base insulating layer using the first gate electrode, the third gate electrode, and the fifth gate electrode as masks to form a first gate insulating layer having a first thickness between the first gate electrode and the first well region, a third gate insulating layer having a third thickness between the third gate electrode and the third well region, and a fifth gate insulating layer having a fifth thickness between the fifth gate electrode and the fifth well region.

[0029] In one or more embodiments, the method further includes forming a first sidewall on side surfaces of the first gate insulating layer and the first gate electrode to overlap the first low-concentration impurity region, forming a third sidewall on side surfaces of the third gate insulating layer and the third gate electrode to overlap the third low-concentration impurity region, and forming a fifth sidewall on side surfaces of the fifth gate insulating layer and the fifth gate electrode to overlap the fifth low-concentration impurity region; and performing a high-concentration ion implantation process using the first gate electrode, the first sidewall, the third gate electrode, the third sidewall, the fifth gate electrode, and the fifth sidewall as a mask to form a first source electrode and a first drain electrode in a portion of the first low-concentration impurity region, to form a third source electrode and a third drain electrode in a portion of the third low-concentration impurity region, and to form a fifth source electrode and a fifth drain electrode in a portion of the fifth low-concentration impurity region.

[0030] A display device according to one or more embodiments can increase an operation range in a linear region of a driving transistor, thereby allowing (e.g., enabling) fine gray scale expression of the display device.

[0031] A display device according to one or more embodiments can improve on / off switching capability of a switching transistor.

[0032] A display device according to one or more embodiments can increase capacitance of a capacitor.

[0033] Effects according to one or more embodiments of the present disclosure are not limited to what has been described above, and various other effects will be included in the drawings and the following description. BRIEF DESCRIPTION OF DRAWINGS

[0034] The above and other aspects and features of the present disclosure will become clearer after a detailed description of illustrative, non-limiting embodiments thereof, with reference to the attached drawings, in which:

[0035] Figure 1 is an exploded perspective view illustrating a display device according to one or more embodiments of the present disclosure;

[0036] Figure 2 is a block diagram illustrating a display device according to one or more embodiments of the present disclosure;

[0037] Figure 3 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure;

[0038] Figure 4 is a circuit diagram illustrating a first capacitor of Figure 3 according to one or more embodiments of the present disclosure;

[0039] Figure 5 is a layout diagram illustrating a display panel according to one or more embodiments of the present disclosure;

[0040] Figure 6 and Figure 7 is a layout diagram illustrating a display area of the head-mounted display of Figure 5 ;

[0041] Figure 8 is a cross-sectional view taken along line II-II' of Figure 6 and illustrating a display panel according to one or more embodiments of the present disclosure;

[0042] Figure 9 is a layout diagram illustrating a display area of the head-mounted display of Figure 5 according to one or more embodiments of the present disclosure;

[0043] Figure 10 is a cross-sectional view taken along line X-X' of Figure 9 illustrating a display panel according to one or more embodiments of the present disclosure;

[0044] Figures 11 to 23 is a process cross-sectional view illustrating a method for manufacturing a display device according to one or more embodiments of the present disclosure;

[0045] Figure 24 is a perspective view illustrating a head-mounted display according to one or more embodiments of the present disclosure;

[0046] Figure 25 is an exploded perspective view illustrating a head-mounted display of Figure 24 according to one or more embodiments of the present disclosure; and

[0047] Figure 26 is a perspective view illustrating a head-mounted display according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0048] The advantages and features of the present disclosure and a method for achieving them will become apparent from the following description of example embodiments with reference to the accompanying drawings. However, the present disclosure is not limited to the example embodiments disclosed herein and can be implemented in various different ways. The example embodiments are provided so that the present disclosure is thorough and to fully convey the scope of the present disclosure to those skilled in the art.

[0049] As used herein, the phrase "element A on element B" means that element A can be disposed directly on element B, and / or element A can be disposed indirectly on element B via another element C. Identical reference numerals denote the same elements throughout the description. The drawings given herein are diagrammatic and not drawn to scale, and proportions of the various components can not be necessarily to scale, and the dimensions, proportions, angles, etc. shown are intended to exemplify only.

[0050] The terminology used herein is intended to describe particular embodiments and is not intended to limit the disclosure. It will be understood that the terms "comprises", "comprising", or "has", "having", as used herein, specify the presence of the stated element but do not preclude the presence or addition of one or more other elements. The expressions "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be construed as one X, one Y, one Z or any combination of two or more of X, Y and Z (e.g., XYZ, XYY, YZ, ZZ, and the like). The terms "or" and "and / or" as used herein, include any combination of one or more of the associated listed items.

[0051] Although terms such as first, second, etc. are used to arbitrarily distinguish between elements described by these terms, these terms are not necessarily intended to represent a temporal or other priority of the elements described by these terms. The terms are used merely to distinguish one element from another. Accordingly, as used herein, a first element can be a second element within the technical scope of the present disclosure.

[0052] In view of the entire content of the present disclosure, those of ordinary skill in the art will understand that each suitable feature of various embodiments of the present disclosure can be combined in part or in whole with each other and can be technically linked and operated in various suitable ways, and each embodiment can be implemented independently of each other or in combination with each other in any suitable way unless otherwise specified or implied.

[0053] Spatially relative terms such as "below", "above", etc. can be used for descriptive purposes, to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device is illustrated in the figures as being flipped over, elements depicted below other elements or features would instead be oriented above the other elements or features. Accordingly, the terms "below" and "above" can encompass both an upward and a downward orientation in some embodiments. In some embodiments, the device can be oriented in other directions (for example, rotated 90 degrees or at other orientations) and, accordingly, the spatially relative terms used herein should be interpreted accordingly.

[0054] Various embodiments are described with reference to the accompanying drawings, which illustrate non-limiting embodiments. Accordingly, it will be appreciated that the shapes can vary depending on, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as being limited to the specific shapes illustrated, but should be construed to include variations in shape that occur, for example, due to manufacturing. Accordingly, the shapes illustrated in the drawings can not depict the actual shape of the regions of the device, and the present embodiments are not limited thereto.

[0055] When an embodiment can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or in the reverse order of the described sequence.

[0056] As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximations rather than terms of degree and are intended to account for the inherent biases of measurements or calculations that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” As used herein, the terms “use,” “being used,” and “being exploited” can be considered synonymous with the terms “utilize,” “being exploited,” and “being exploited,” respectively.

[0057] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0058] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0059] Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments of the present disclosure. Figure 2 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0060] refer to Figure 1 and Figure 2 The display device 10 according to one or more embodiments is an apparatus for displaying moving images and / or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and / or ultra-mobile PCs (UMPCs). For example, the display device 10 according to one or more embodiments can be applied as a display unit in a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. The display device 10 according to one or more embodiments can be applied to smartwatches, smartwatch phones, and head-mounted displays (HMDs) for implementing virtual reality and augmented reality.

[0061] The display device 10 according to one or more embodiments includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit (e.g., a power supply unit) 500.

[0062] The display panel 100 can have a planar shape similar to a quadrilateral shape. For example, the display panel 100 can have a planar shape similar to a quadrilateral shape having a short side corresponding to a first direction DR1 and a long side corresponding to a second direction DR2 intersecting the first direction DR1. In the display panel 100, a corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be a right angle or rounded with a curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to the quadrilateral shape, and can be a suitable shape similar to another polygonal shape, a circular shape, and an elliptical shape, etc. The planar shape of the display device 10 can conform to the planar shape of the display panel 100, but the present disclosure is not limited thereto.

[0063] Referring to Figure 2 , the display panel 100 can include a display area DAA for displaying an image and a non-display area NDA for not displaying an image.

[0064] The display area DAA can include a plurality of pixels, a plurality of scan lines GWL and EBL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0065] The plurality of pixels can be arranged in a matrix form in the first direction DR1 and the second direction DR2. The plurality of scan lines GWL and EBL and the plurality of emission control lines EL can extend in the first direction DR1 while being disposed in the second direction DR2. The plurality of data lines DL can extend in the second direction DR2 while being disposed in (e.g., positioned along) the first direction DR1.

[0066] The plurality of scan lines GWL and EBL can include a plurality of write scan lines GWL and a plurality of bias scan lines EBL.

[0067] Each of the plurality of unit pixels UPX can include a plurality of pixels PX1, PX2, and PX3. The plurality of pixels PX1, PX2, and PX3 can include a plurality of pixel transistors as shown in Figure 3 , and the plurality of pixel transistors can be formed (e.g., by a semiconductor process) and can be disposed on a semiconductor substrate SSUB (e.g., see Figure 8 ). In some embodiments, the data driver 700 can include the plurality of pixel transistors. The pixel transistors can be formed of a complementary metal-oxide semiconductor (CMOS).

[0068] Each of the plurality of pixels PX1, PX2, and PX3 can be connected (e.g., coupled) to any one of a plurality of write scan lines GWL, any one of a plurality of bias scan lines EBL, any one of a plurality of emission control lines EL, and any one of a plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL, and can emit light from a light emitting element LE (e.g., see Figure 3 ) according to the data voltage.

[0069] The non-display area NDA can include a scan driver 610, an emission driver 620, and a data driver 700.

[0070] The scan driver 610 can include a plurality of scan transistors, and the emission driver 620 can include a plurality of emission transistors. The plurality of scan transistors and the plurality of emission transistors can be formed on a semiconductor substrate SSUB (e.g., see Figure 8 ) by a semiconductor process. For example, the plurality of scan transistors and the plurality of emission transistors can be formed (e.g., can include) by CMOS (e.g., can include CMOS materials). Although the scan driver 610 is illustrated as being disposed (e.g., located or positioned) at the left side of the display area DAA and the emission driver 620 is disposed at the right side of the display area DAA in Figure 2 , the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 can be disposed not only at the left side of the display area DAA but also at the right side of the display area DAA.

[0071] The scan driver 610 can include a write scan signal output unit 611 and a bias scan signal output unit 612. Each of the write scan signal output unit 611 and the bias scan signal output unit 612 can receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 can generate write scan signals according to the scan timing control signal SCS of the timing control circuit 400, and sequentially output them to the write scan lines GWL. The bias scan signal output unit 612 can generate bias scan signals according to the scan timing control signal SCS, and sequentially output them to the bias scan lines EBL.

[0072] The emission driver 620 can receive an emission timing control signal ECS from the timing control circuit 400. The emission driver 620 can generate emission control signals in response to the emission timing control signal ECS, and sequentially output them to the emission control lines EL.

[0073] The data driver 700 can include a plurality of data transistors, and the plurality of data transistors can be formed on a semiconductor substrate S SUB (see, for example, Figure 8 ) by a semiconductor process (e.g., from a semiconductor process).

[0074] The data driver 700 can receive digital video data DATA and data timing control signals DCS from the timing control circuit 400. The data driver 700 can convert the digital video data DATA into an analog data voltage according to the data timing control signals DCS, and output the analog data voltage to the data line DL. In one or more embodiments, the pixels PX1, PX2, and PX3 are selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected pixels PX1, PX2, and PX3.

[0075] The heat dissipation layer 200 (see Figure 1 ) can overlap the display panel 100 in a third direction DR3 which is a thickness direction of the display panel 100. The heat dissipation layer 200 can be disposed on one surface of the display panel 100 (e.g., on a rear surface thereof). In one or more embodiments, the heat dissipation layer 200 functions to dissipate heat generated from the display panel 100. The heat dissipation layer 200 can include graphite having a relatively high thermal conductivity or a metal layer such as silver (Ag), copper (Cu), or aluminum (Al).

[0076] The circuit board 300 can be electrically connected to the plurality of first pads PD1 (see Figure 5 ) of the first pad portion PDA1 (see Figure 5 ) of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 can be a flexible printed circuit board having a flexible material or a flexible film. Although the circuit board 300 is illustrated as being unfolded in Figure 1 , the circuit board 300 can be bent (e.g., can be foldable). In one or more embodiments, one end portion of the circuit board 300 can be disposed on a rear surface of the display panel 100 and / or a rear surface of the heat dissipation layer 200. The one end portion of the circuit board 300 can be an opposite end portion of another end portion of the circuit board 300 which is electrically connected to the plurality of first pads PD1 (see Figure 5 ) of the first pad portion PDA1 (see Figure 5 ) of the display panel 100 by using the conductive adhesive member.

[0077] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0078] The power supply circuit 500 can generate multiple panel driving voltages based on the external power supply voltage. For example, the power supply circuit 500 can generate a common voltage ELVSS, a driving voltage ELVDD, and an initialization voltage VINT, and supply them to the display panel 100. The following describes... Figure 3 The common voltage ELVSS, drive voltage ELVDD, and initialization voltage VINT are discussed in more detail.

[0079] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In one or more embodiments, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 via the circuit board 300. In one or more embodiments, the common voltage ELVSS, drive voltage ELVDD, and initialization voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 via the circuit board 300.

[0080] In one or more embodiments, similar to the scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 may be disposed in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include a plurality of timing transistors, and each power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on a semiconductor substrate SSUB (e.g., see [reference]) using semiconductor processes. Figure 8 On the data driver 700. For example, multiple timing transistors and multiple power transistors can be formed by CMOS (e.g., may include CMOS). Each of the timing control circuit 400 and the power supply circuit 500 can be disposed on the data driver 700 and the first pad portion of PDA1 (see Figure 5 )between.

[0081] Figure 3is an equivalent circuit diagram of a pixel according to one or more embodiments of the disclosure.

[0082] As shown in Figure 3 The first pixel PX1 can be connected to a write scan line GWL, a bias scan line EBL, an emission control line EL, an initialization voltage line VIL, a data line DL, a driving voltage line VDL, and a common voltage line VSL. Here, the common voltage line VSL can be connected to a common electrode (e.g., a cathode electrode) of the light emitting element LE.

[0083] The first pixel PX1 can include a pixel circuit PC and a light emitting element LE.

[0084] The pixel circuit PC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, and a second capacitor C2.

[0085] The first transistor T1 (e.g., a driving transistor) can include a gate electrode, a source electrode, a drain electrode, and a body electrode. The first transistor T1 can control a source-drain current (hereinafter, a driving current) according to a data voltage applied to the gate electrode. The driving current (e.g., Isd) flowing through a channel region of the first transistor T1 can be proportional to the square of the difference between a threshold voltage Vth and a voltage Vsg between the source electrode and the gate electrode of the first transistor T1 (Isd = k × (Vsg - Vth) 2 ). Here, k is a proportional coefficient determined by the structure and physical characteristics of the first transistor T1, Vsg is the source-gate voltage of the first transistor T1, and Vth is the threshold voltage of the first transistor T1. The gate electrode of the first transistor T1 can be electrically connected to a first node N1, the source electrode thereof can be electrically connected to a second node N2, the drain electrode thereof can be electrically connected to a third node N3, and the body electrode thereof can be electrically connected to the driving voltage line VDL.

[0086] The light emitting element LE can emit light by receiving a drive current. An emission amount or brightness of the light emitting element LE can be proportional to a size of the drive current. The light emitting element LE can be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode. For another example, the light emitting element LE can be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For yet another example, the light emitting element LE can be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot light emitting layer disposed between the first electrode and the second electrode. For yet another example, the light emitting element LE can be a micro light emitting diode. The first electrode of the light emitting element LE can be electrically connected to the third node N3. The second electrode of the light emitting element LE can be connected to the common voltage line VSL. The second electrode of the light emitting element LE can receive a common voltage (e.g., a low potential voltage) ELVSS from the common voltage line VSL.

[0087] The second transistor T2 can be turned on by a write scan signal GW of the write scan line GWL to electrically connect the data line DL with the first node N1. The gate electrode of the second transistor T2 can be electrically connected to the write scan line GWL, the source electrode thereof can be electrically connected to the data line DL, the drain electrode thereof can be electrically connected to the first node N1, and the body electrode thereof can be electrically connected to the drive voltage line VDL. The data line DL can transmit a data voltage Vdt.

[0088] The third transistor T3 can be turned on by an emission control signal EM of the emission control line EL to electrically connect the drive voltage line VDL with the second node N2. The gate electrode of the third transistor T3 can be electrically connected to the emission control line EL, the source electrode thereof can be electrically connected to the drive voltage line VDL, the drain electrode thereof can be electrically connected to the second node N2, and the body electrode thereof can be electrically connected to the drive voltage line VDL.

[0089] The fourth transistor T4 can be turned on by a bias scan signal EB of the bias scan line EBL to electrically connect the third node N3 and the initialization voltage line VIL. The gate electrode of the fourth transistor T4 can be electrically connected to the bias scan line EBL, the source electrode thereof can be electrically connected to the third node N3, the drain electrode thereof can be electrically connected to the initialization voltage line VIL, and the body electrode thereof can be electrically connected to the drive voltage line VDL. In one or more embodiments, a plurality of initialization voltage lines VIL can be provided, and the plurality of initialization voltage lines VIL can be connected to each other. For example, the initialization voltage line VIL can include a plurality of horizontal initialization voltage lines extending along the first direction DR1 and arranged in the second direction DR2, and a plurality of vertical initialization voltage lines extending along the second direction DR2 and arranged along the first direction DR1, and the horizontal initialization voltage lines and the vertical initialization voltage lines can be connected to each other.

[0090] The first capacitor C1 can be electrically connected between the first node N1 and the third node N3. For example, a first electrode of the first capacitor C1 can be electrically connected to the first node N1, and a second electrode of the first capacitor C1 can be electrically connected to the third node N3.

[0091] The second capacitor C2 can be electrically connected between the first node N1 and the second node N2. For example, a first electrode of the second capacitor C2 can be electrically connected to the first node N1, and a second electrode of the second capacitor C2 can be electrically connected to the second node N2.

[0092] The first capacitor C1 can have a larger capacitance than a capacitance of the second capacitor C2.

[0093] When the first transistor T1 and the third transistor T3 are turned on, a drive current can be supplied to the light emitting element LE, such that the light emitting element LE can emit light.

[0094] At least one transistor selected from among the first transistor T1 to the fourth transistor T4 described above can be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the fourth transistor T4 can be a P-type MOSFET. In one or more embodiments, each of the first transistor T1 to the fourth transistor T4 can be an N-type MOSFET. In yet another example, some of the first transistor T1 to the fourth transistor T4 can be a P-type MOSFET, and the others can be an N-type MOSFET.

[0095] Although the first pixel PX1 is illustrated as including four transistors T1 to T4 and two capacitors C1 and C2 in Figure 3 , it should be noted that the present disclosure is not limited to the example shown in Figure 3 . For example, the number of transistors and the number of capacitors of the first pixel PX1 are not limited to the example shown in Figure 3 .

[0096] In one or more embodiments, an equivalent circuit diagram of the second pixel PX2 and an equivalent circuit diagram of the third pixel PX3 can be substantially the same as the equivalent circuit diagram of the first pixel PX1 described in connection with Figure 3 . For example, in one or more embodiments, a circuit of the second pixel PX2 and a circuit of the third pixel PX3 can be substantially the same as the circuit of the first pixel PX1 described in connection with Figure 3 . Accordingly, in the present specification, a description of the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 is omitted.

[0097] Figure 4 is a diagram illustrating a light emitting device according to one or more embodiments of the present disclosure. Figure 3a circuit diagram of the first capacitor.

[0098] In one or more embodiments, as in the example shown in Figure 4 The first capacitor C1 can be implemented as a transistor connected between the first node N1 and the third node N3. In other words, the first capacitor can be (e.g., can include) a metal-oxide-semiconductor (MOS) capacitor. For example, the first capacitor C1 can be a P-type MOS capacitor including a gate electrode connected to the first node N1, a source electrode connected to the third node N3, a drain electrode connected to the third node N3, and a body electrode connected to the third node N3. However, the present disclosure is not limited thereto, and the first capacitor C1 can be an N-type MOS capacitor. The first capacitor C1 can also be referred to as a fifth transistor T5.

[0099] In one or more embodiments, similar to the first capacitor C1 described above, the second capacitor C2 can be implemented as a MOS capacitor. For example, the second capacitor C2 can be a P-type MOS capacitor including a gate electrode connected to the first node N1, a source electrode connected to the second node N2, a drain electrode connected to the second node N2, and a body electrode connected to the second node N2. However, the present disclosure is not limited thereto, and the second capacitor C2 can be an N-type MOS capacitor. The second capacitor C2 can also be referred to as a sixth transistor T6.

[0100] Figure 5 is a layout diagram illustrating a display panel according to one or more embodiments of the present disclosure.

[0101] Referring to Figure 5 The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels arranged in a matrix form. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0102] The scan driver 610 can be disposed at a first side of the display area DAA, and the emission driver 620 can be disposed at a second side of the display area DAA. For example, the scan driver 610 can be disposed at one side of the display area DAA in the first direction DR1, and the emission driver 620 can be disposed at the other side of the display area DAA in the first direction DR1. For example, the scan driver 610 can be disposed at a left side of the display area DAA, and the emission driver 620 can be disposed at a right side of the display area DAA. However, the present disclosure is not limited thereto, and the scan driver 610 and the emission driver 620 can be disposed not only at the first side of the display area DAA but also at the second side of the display area DAA.

[0103] The first pad portion PDA1 can include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 through conductive adhesive members. The first pad portion PDA1 can be disposed at a third side of the display area DAA. For example, the first pad portion PDA1 can be disposed at one side of the display area DAA in the second direction DR2.

[0104] The first pad portion PDA1 can be disposed outside the data driver 700 in the second direction DR2. For example, the first pad portion PDA1 can be disposed closer to an edge of the display panel 100 than the data driver 700.

[0105] The second pad portion PDA2 can include a plurality of second pads PD2 corresponding to inspection pads for testing whether the display panel 100 operates normally. The plurality of second pads PD2 can be connected to a jig or a probe during an inspection process, or can be connected to a circuit board for inspection. The circuit board for inspection can be a printed circuit board made of a suitable rigid material or a suitable flexible printed circuit board made of a suitable flexible material.

[0106] The first distribution circuit 710 distributes data voltages applied through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 can distribute data voltages applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or more) data lines DL, and as a result, the number of the plurality of first pads PD1 can be reduced. The first distribution circuit 710 can be disposed at a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed at one side of the display area DAA in the second direction DR2. For example, the first distribution circuit 710 can be disposed at a lower side of the display area DAA.

[0107] The second distribution circuit 720 distributes signals applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data lines DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to inspect the operation of each of the pixels in the display area DAA. The second distribution circuit 720 can be disposed at a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed at the other side of the display area DAA in the second direction DR2. For example, the second distribution circuit 720 can be disposed at an upper side of the display area DAA.

[0108] Figure 6 and Figure 7 is a layout diagram of a display area of a display device according to one or more embodiments of the present disclosure. Figure 5 ​

[0109] Referring to Figure 6 and Figure 7 Each of the plurality of unit pixels UPX includes a first emission area EA1 that is an emission area of the first pixel PX1, a second emission area EA2 that is an emission area of the second pixel PX2, and a third emission area EA3 that is an emission area of the third pixel PX3. In other words, the unit pixel UPX can include a unit emission area UEA, and the unit emission area UEA includes the first emission area EA1, the second emission area EA2, and the third emission area EA3 described above.

[0110] Referring to Figure 6 and Figure 7 Each of the plurality of pixels includes a first emission area EA1 that is an emission area of the first pixel PX1, a second emission area EA2 that is an emission area of the second pixel PX2, and a third emission area EA3 that is an emission area of the third pixel PX3.

[0111] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 can have a polygonal shape, a circular shape, an elliptical shape, or a non-typical shape (e.g., another suitable shape) in a plan view.

[0112] In one or more embodiments, a maximum length of the first emission area EA1 in the first direction DR1 can be less than a maximum length of the second emission area EA2 in the first direction DR1 and a maximum length of the third emission area EA3 in the first direction DR1. The maximum length of the second emission area EA2 in the first direction DR1 and the maximum length of the third emission area EA3 in the first direction DR1 can be substantially the same.

[0113] In one or more embodiments, a maximum length of the first emission area EA1 in the second direction DR2 can be greater than a maximum length of the second emission area EA2 in the second direction DR2 and a maximum length of the third emission area EA3 in the second direction DR2. The maximum length of the second emission area EA2 in the second direction DR2 can be greater than the maximum length of the third emission area EA3 in the second direction DR2. The maximum length of the first emission area EA1 in the second direction DR2 can be less than the maximum length of the second emission area EA2 in the second direction DR2.

[0114] In one or more embodiments, a maximum length of the first emission area EA1 in the first direction DR1 can be substantially equal to a maximum length of the second emission area EA2 in the first direction DR1 and greater than a maximum length of the third emission area EA3 in the first direction DR1.

[0115] In one or more embodiments, a maximum length of the first emission area EA1 in the second direction DR2 can be greater than a maximum length of the second emission area EA2 in the second direction DR2 and less than a maximum length of the third emission area EA3 in the second direction DR2. The maximum length of the second emission area EA2 in the second direction DR2 can be less than the maximum length of the third emission area EA3 in the second direction DR2. The maximum length of the first emission area EA1 in the second direction DR2 can be less than the maximum length of the third emission area EA3 in the second direction DR2.

[0116] In one or more embodiments, as shown in Figure 6 and Figure 7 , the first emission area EA1, the second emission area EA2, and the third emission area EA3 can have a hexagonal shape formed by six straight lines in a plan view, but the present disclosure is not limited thereto. The first emission area EA1, the second emission area EA2, and the third emission area EA3 can have a polygonal shape other than a hexagonal shape. In one or more embodiments, the first emission area EA1, the second emission area EA2, and the third emission area EA3 can have a circular shape, an elliptical shape, or a non-typical shape (e.g., another suitable shape) in a plan view.

[0117] As shown in Figure 6 , in each of the plurality of pixels, the first emission area EA1 and the second emission area EA2 can be adjacent to each other in the second direction DR2. Further, the first emission area EA1 and the third emission area EA3 can be adjacent to each other in the first direction DR1. In some embodiments, the second emission area EA2 and the third emission area EA3 can be adjacent to each other in the first direction DR1. The area of the first emission area EA1, the area of the second emission area EA2, and the area of the third emission area EA3 can be different from each other.

[0118] In one or more embodiments, as shown in Figure 7 , the first emission area EA1 and the second emission area EA2 can be adjacent to each other in the first direction DR1, the second emission area EA2 and the third emission area EA3 can be adjacent to each other in the first diagonal direction DD1, and the first emission area EA1 and the third emission area EA3 can be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 can be a direction between the first direction DR1 and the second direction DR2 and can refer to a direction inclined by 45 degrees with respect to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction perpendicular to the first diagonal direction DD1.

[0119] The first emission area EA1 can emit light of a first color, the second emission area EA2 can emit light of a second color, and the third emission area EA3 can emit light of a third color. Here, the light of the first color can be light of a blue wavelength band, the light of the second color can be light of a green wavelength band, and the light of the third color can be light of a red wavelength band. For example, the blue wavelength band can be a wavelength band of light whose main peak wavelength is in a range of about 370 nm to about 460 nm, the green wavelength band can be a wavelength band of light whose main peak wavelength is in a range of about 480 nm to about 560 nm, and the red wavelength band can be a wavelength band of light whose main peak wavelength is in a range of about 600 nm to about 750 nm.

[0120] In one or more embodiments, as depicted in Figure 6 and Figure 7 , each of the plurality of pixels can include three emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. For example, in one or more embodiments, each of the plurality of pixels can include four emission areas.

[0121] In some embodiments, for example, the layout of the emission areas of the plurality of pixels is not limited to the layout illustrated in Figure 7 and Figure 8 . For example, as shown in Figure 6 , the emission areas of the plurality of pixels can be arranged in a bar structure in which the emission areas are arranged in a first direction DR1, an RGBG structure in which the emission areas are arranged in a diamond shape (for example, a structure, is a registered trademark of Samsung Display Co., Ltd.), or a hexagonal structure in which the emission areas having a hexagonal shape in a plan view are arranged side by side.

[0122] Figure 8 is a cross-sectional view illustrating an example of the display panel taken along a line II-II’ of Figure 3 .

[0123] Referring to Figure 3 , the display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, a encapsulation layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL. In one or more embodiments, the cover layer CVL and / or the polarizing plate POL can be part of the optical layer OPL.

[0124] The semiconductor backplane SBP can include a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers (including, for example, a first semiconductor insulating layer SINS1 and a second semiconductor insulating layer SINS2) covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to corresponding ones of the plurality of pixel transistors PTR. As used herein, corresponding ones of components can refer to one or more components. The plurality of pixel transistors PTR can be (e.g., can include) the pixel transistors PTR described with reference to FIGS. 1A and 1B. Figure 3 The first to fourth transistors T1 to T4 are described.

[0125] The semiconductor substrate SSUB can be (e.g., can include) a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be (e.g., can include) a substrate doped with a first type impurity. The plurality of well regions WA can be disposed on a top surface of the semiconductor substrate SSUB. The plurality of well regions WA can be regions doped with a second type impurity. The second type impurity can be different from the aforementioned first type impurity. For example, when the first type impurity is a p-type impurity, the second type impurity can be an n-type impurity. In one or more embodiments, when the first type impurity is an n-type impurity, the second type impurity can be a p-type impurity.

[0126] Each of the plurality of well regions WA can include a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode thereof, and a channel region CH disposed between the source region SA and the drain region DA.

[0127] The bottom insulating layer BINS can be disposed between the gate electrode GE and the well region WA. The side insulating layer SINS can be disposed on (e.g., at) a side surface of the gate electrode GE. The side insulating layer SINS can be disposed on the bottom insulating layer BINS.

[0128] Each of the source region SA and the drain region DA can be a region doped with the first type impurity. The gate electrode GE of the pixel transistor PTR can overlap the well region WA in a third direction DR3. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be disposed at one side of the gate electrode GE, and the drain region DA can be disposed at the other side of the gate electrode GE.

[0129] Each of the plurality of well regions WA can further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 can be a region having a lower impurity concentration than that of the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 can be a region having a lower impurity concentration than that of the drain region DA due to the lower insulating layer BINS. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, a distance between the source region SA and the drain region DA can increase. Accordingly, a length of the channel region CH of each of the pixel transistors PTR can increase, such that punch-through and hot carrier phenomena that can be caused by a short channel can be prevented.

[0130] The first semiconductor insulating layer SINS1 can be disposed on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 can be formed of a silicon carbon nitride (SiCN) or a silicon oxide (SiO x ) type inorganic layer, but the disclosure is not limited thereto.

[0131] The second semiconductor insulating layer SINS2 can be disposed on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 can be formed of a silicon oxide (SiO x ) type inorganic layer (e.g., can include a silicon oxide (SiOx) type inorganic layer), but the disclosure is not limited thereto.

[0132] The plurality of contact terminals CTE can be disposed on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE can be connected to a corresponding one of the gate electrode GE, the source region SA, and the drain region DA of a corresponding one of the pixel transistors PTR through a hole that penetrates the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0133] The third semiconductor insulating layer SINS3 can be disposed on a side surface of each of the plurality of contact terminals CTE. A top surface of each of the plurality of contact terminals CTE can be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 can be formed of a silicon oxide (SiO x ) type inorganic layer, but the disclosure is not limited thereto.

[0134] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate such as polyimide. In this case, a thin film transistor can be provided on the glass substrate or the polymer resin substrate. The glass substrate can be a non-bendable rigid substrate, and the polymer resin substrate can be a flexible substrate that can be bent or curved.

[0135] The light emitting element backplane EBP can include a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating layers INS1 to INS9. In some embodiments, for example, the light emitting element backplane EBP includes a plurality of insulating layers INS1 to INS11 disposed between the first conductive layer ML1 and the eighth conductive layer ML8.

[0136] The first conductive layer ML1 to the eighth conductive layer ML8 can be used to connect a plurality of contact terminals CTE exposed from the semiconductor backplane SBP to implement Figure 8 The circuit of the first pixel PX1 illustrated in FIG. 1A. For example, the first transistor T1 to the sixth transistor T6 can be formed on the semiconductor backplane SBP, and the connections of the first transistor T1 to the sixth transistor T6 (e.g., including the first capacitor C1 and the second capacitor C2) can be implemented through the first conductive layer ML1 to the eighth conductive layer ML8. In one or more embodiments, for example, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE can also be implemented through the first conductive layer ML1 to the eighth conductive layer ML8. As used herein and depending on the context, a conductive layer can refer to a plurality of conductive components located at the same layer, or can refer to one conductive component among a plurality of conductive components located at the same layer. As used herein and depending on the context, a via can refer to a plurality of vias located at the same layer, or can refer to one via among a plurality of vias located at the same layer.

[0137] The first insulating layer INS1 can be disposed on the semiconductor backplane SBP. Each of the first vias VA1 can penetrate the first insulating layer INS1 to connect to a corresponding contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 can be disposed on the first insulating layer INS1 and can be connected to a corresponding first via VA1.

[0138] The second insulating layer INS2 can be disposed on the first insulating layer INS1 and the first conductive layer ML1. Each of the second vias VA2 can penetrate the second insulating layer INS2 and be connected to a corresponding exposed first conductive layer ML1. Each of the second conductive layers ML2 can be disposed on the second insulating layer INS2 and can be connected to a corresponding one of the second vias VA2.

[0139] A third insulating layer INS3 can be disposed on the second insulating layer INS2 and the second conductive layer ML2. Each of third vias VA3 can penetrate the third insulating layer INS3 and be connected to a corresponding exposed second conductive layer ML2 of the exposed second conductive layers ML2. Each of third conductive layers ML3 can be disposed on the third insulating layer INS3 and can be connected to a corresponding third via VA3 of the third vias VA3.

[0140] A fourth insulating layer INS4 can be disposed on the third insulating layer INS3 and the third conductive layer ML3. Each of fourth vias VA4 can penetrate the fourth insulating layer INS4 and be connected to a corresponding exposed third conductive layer ML3 of the exposed third conductive layers ML3. Each of fourth conductive layers ML4 can be disposed on the fourth insulating layer INS4 and can be connected to a corresponding fourth via VA4 of the fourth vias VA4.

[0141] A fifth insulating layer INS5 can be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each of fifth vias VA5 can penetrate the fifth insulating layer INS5 and be connected to a corresponding exposed fourth conductive layer ML4 of the exposed fourth conductive layers ML4. Each of fifth conductive layers ML5 can be disposed on the fifth insulating layer INS5 and can be connected to a corresponding fifth via VA5 of the fifth vias VA5.

[0142] A sixth insulating layer INS6 can be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each of sixth vias VA6 can penetrate the sixth insulating layer INS6 and be connected to a corresponding exposed fifth conductive layer ML5 of the exposed fifth conductive layers ML5. Each of sixth conductive layers ML6 can be disposed on the sixth insulating layer INS6 and can be connected to a corresponding sixth via VA6 of the sixth vias VA6.

[0143] A seventh insulating layer INS7 can be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each of seventh vias VA7 can penetrate the seventh insulating layer INS7 and be connected to a corresponding exposed sixth conductive layer ML6 of the exposed sixth conductive layers ML6. Each of seventh conductive layers ML7 can be disposed on the seventh insulating layer INS7 and can be connected to a corresponding seventh via VA7 of the seventh vias VA7.

[0144] The eighth insulating layer INS8 can be provided on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 can penetrate the eighth insulating layer INS8 and be connected to a corresponding exposed seventh conductive layer ML7 of the exposed seventh conductive layers ML7. Each of the eighth conductive layers ML8 can be provided on the eighth insulating layer INS8 and can be connected to a corresponding eighth via VA8 of the eighth vias VA8.

[0145] The first conductive layers ML1 to the eighth conductive layers ML8 and the first vias VA1 to the eighth vias VA8 can be formed of substantially the same material. The first conductive layers ML1 to the eighth conductive layers ML8 and the first vias VA1 to the eighth vias VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The first vias VA1 to the eighth vias VA8 can be made of substantially the same material. The first insulating layers INS1 to the eighth insulating layers INS8 can be formed of a silicon oxide (SiO x ) inorganic layer, but the present disclosure is not limited thereto.

[0146] The thicknesses (e.g., in the third direction DR3) of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be about 1 nm to about 100 nm, the thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be about 100 nm to about 1,000 nm, and the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be about 1 nm to about 100 nm. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be about 100 nm to about 1,000 nm. and the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be about 1 nm to about 100 nm.

[0147] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately... The thickness of each of the seventh through hole VA7 and the eighth through hole VA8 can be approximately

[0148] The ninth insulating layer INS9 can be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 can be made of silicon oxide (SiO2). x ( ) Inorganic layer formation, but this disclosure is not limited thereto.

[0149] Each of the ninth vias VA9 can penetrate the ninth insulating layer INS9 and connect to the corresponding exposed eighth conductive layer ML8. The ninth vias VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. The thickness of the ninth via VA9 can be approximately...

[0150]

[0151] The display element layer (EML) can be disposed on the light-emitting element base plate (EBP). The display element layer (EML) may include light-emitting elements (LE) (e.g., see [link]). Figure 8 Each light-emitting element (LE) includes a reflective electrode layer (RL), a tenth insulating layer (INS10) and an eleventh insulating layer (INS11), a tenth via (VA10), a first electrode (AND), a light-emitting stack (ES), a second electrode (CAT), a pixel-defining layer (PDL), and multiple trenches (TRC).

[0152] A reflective electrode layer RL may be disposed on a ninth insulating layer INS9. The reflective electrode layer RL may include at least one reflective electrode (e.g., at least one of the first to fourth reflective electrodes RL1, RL2, RL3, and RL4). For example, as... Figure 8As illustrated in FIG. 1, the reflective electrode layer RL can include first to fourth reflective electrodes RL1, RL2, RL3, and RL4.

[0153] Each of the first reflective electrodes RL1 can be disposed on the ninth insulating layer INS9 and can be connected to a corresponding ninth via hole VA9. The first reflective electrodes RL1 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the first reflective electrodes RL1 can include titanium nitride (TiN).

[0154] Each of the second reflective electrodes RL2 can be disposed on a corresponding first reflective electrode RL1. The second reflective electrodes RL2 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the second reflective electrodes RL2 can include aluminum (Al).

[0155] Each of the third reflective electrodes RL3 can be disposed on a corresponding second reflective electrode RL2. The third reflective electrodes RL3 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the third reflective electrodes RL3 can include titanium nitride (TiN).

[0156] The fourth reflective electrodes RL4 can be disposed on the third reflective electrodes RL3, respectively. The fourth reflective electrodes RL4 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the fourth reflective electrodes RL4 can include titanium (Ti).

[0157] Since the second reflective electrodes RL2 are electrodes that substantially reflect light from the light emitting elements LE, the thickness of the second reflective electrodes RL2 can be greater than the thickness of each of the first reflective electrodes RL1, the third reflective electrodes RL3, and the fourth reflective electrodes RL4. For example, the thickness of each of the first reflective electrodes RL1, the third reflective electrodes RL3, and the fourth reflective electrodes RL4 can be about 100 nm to 300 nm, and the thickness of the second reflective electrodes RL2 can be about 300 nm to 500 nm. and the thickness of the second reflective electrodes RL2 can be about 300 nm to 500 nm. As used herein and depending on the context, a reflective electrode can refer to a plurality of reflective electrodes located at the same layer, or can refer to one reflective electrode among a plurality of reflective electrodes located at the same layer.

[0158] A tenth insulating layer INS10 can be provided on the ninth insulating layer INS9. The tenth insulating layer INS10 can be provided between reflective electrode layers RL adjacent to each other in a horizontal direction (e.g., in a direction substantially perpendicular to the third direction DR3). The tenth insulating layer INS10 can be provided on the reflective electrode layer RL in the third pixel PX3. The tenth insulating layer INS10 can be formed of a silicon oxide (SiO x ) type inorganic layer, but the present disclosure is not limited thereto.

[0159] An eleventh insulating layer INS11 can be provided on the tenth insulating layer INS10 and the reflective electrode layer RL. The eleventh insulating layer INS11 can be formed of a silicon oxide (SiO x ) type inorganic layer, but the present disclosure is not limited thereto. The tenth insulating layer INS10 and the eleventh insulating layer INS11 can be optical auxiliary layers through which light reflected by the reflective electrode layer RL among light emitted from the light emitting element LE passes. For example, light emitted from the light emitting element LE can be reflected by the reflective electrode layer RL and can pass through the tenth insulating layer INS10 and pass through the eleventh insulating layer INS11.

[0160] To match a resonance distance of light emitted from the light emitting element LE selected from at least one among the first pixel PX1, the second pixel PX2, and the third pixel PX3, the tenth insulating layer INS10 and the eleventh insulating layer INS11 can not be provided under the first electrode AND of the first pixel PX1. For example, the first electrode AND of the first pixel PX1 can be directly provided on the reflective electrode layer RL. The eleventh insulating layer INS11 can be provided under the first electrode AND of the second pixel PX2. The tenth insulating layer INS10 and the eleventh insulating layer INS11 can be provided under the first electrode AND of the third pixel PX3.

[0161] In summary, in the first pixel PX1, the second pixel PX2, and the third pixel PX3, the distance between the first electrode AND and the reflective electrode layer RL can be different. To adjust the distance from the reflective electrode layer RL to the second electrode CAT according to a main wavelength of light emitted from each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the presence or absence of the tenth insulating layer INS10 and / or the eleventh insulating layer INS11 can be set in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example and with reference to Figure 8The distance between the first electrode AND and the reflective electrode layer RL in the third pixel PX3 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 and / or the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1, and the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1, but the present disclosure is not limited thereto.

[0162] In one or more embodiments, a twelfth insulating layer disposed under the first electrode AND of the first pixel PX1 can be further added. In one or more embodiments, the eleventh insulating layer INS11 and the twelfth insulating layer can be disposed under the first electrode AND of the second pixel PX2, and the tenth insulating layer INS10, the eleventh insulating layer INS11, and the twelfth insulating layer can be disposed under the first electrode AND of the third pixel PX3.

[0163] Each of the tenth vias VA10 can penetrate the tenth insulating layer INS10 and / or the eleventh insulating layer INS11 in the second pixel PX2 and the third pixel PX3, and can be connected to the exposed reflective electrode layer RL. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the tenth via VA10 in the second pixel PX2 can be less than the thickness of the tenth via VA10 in the third pixel PX3.

[0164] The first electrode AND of each of the light emitting elements LE can be disposed on the tenth insulating layer INS10 and connected to a corresponding one of the tenth vias VA10. The first electrode AND of each of the light emitting elements LE can be connected to the drain region DA or the source region SA of a corresponding one of the pixel transistors PTR through a corresponding one of the tenth vias VA10, a corresponding one of the first to fourth reflective electrodes RL1 to RL4, a corresponding one of the first to ninth vias VA1 to VA9, a corresponding one of the first to eighth conductive layers ML1 to ML8, and a corresponding one of the contact terminals CTE. The first electrode AND of each of the light emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the first electrode AND of each of the light emitting elements LE can be (e.g., can include) titanium nitride (TiN).

[0165] The pixel defining layer PDL can be disposed on a portion of the first electrode AND of each of the light emitting elements LE. The pixel defining layer PDL can cover edges of the first electrode AND of each of the light emitting elements LE. The pixel defining layer PDL can serve to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0166] The first emission area EA1 can be defined as an area in which the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked to emit light in the first pixel PX1. The second emission area EA2 can be defined as an area in which the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked to emit light in the second pixel PX2. The third emission area EA3 can be defined as an area in which the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked to emit light in the third pixel PX3.

[0167] The pixel defining layer PDL can include first to third pixel defining layers PDL1, PDL2, and PDL3. The first pixel defining layer PDL1 can be disposed on edges of the first electrode AND of each of the light emitting elements LE, the second pixel defining layer PDL2 can be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 can be disposed on the second pixel defining layer PDL2. The first to third pixel defining layers PDL1, PDL2, and PDL3 can be formed of silicon oxide (SiO xan inorganic layer, but the disclosure is not limited thereto. The first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3 can each have a thickness of about

[0168] When the first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3 are formed as one pixel definition layer, the height of the one pixel definition layer PDL increases, so that the first encapsulation inorganic layer TFE1 can be cut off due to step coverage. Step coverage refers to a ratio of a degree of a thin film coated on an inclined portion to a degree of a thin film coated on a flat portion. The lower the step coverage, the more likely the thin film will be cut off at the inclined portion.

[0169] Accordingly, to prevent the first encapsulation inorganic layer TFE1 from being cut off due to step coverage, the first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3 can have a cross-sectional structure of a portion with a step. For example, the width of the first pixel definition layer PDL1 can be greater than the width of the second pixel definition layer PDL2 and the width of the third pixel definition layer PDL3, and the width of the second pixel definition layer PDL2 can be greater than the width of the third pixel definition layer PDL3. The width of the first pixel definition layer PDL1 refers to a horizontal length of the first pixel definition layer PDL1 defined in the first direction DR1 and the second direction DR2.

[0170] Each of the plurality of trenches TRC can penetrate the first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3. In addition, each of the plurality of trenches TRC can penetrate the eleventh insulating layer INS11. The tenth insulating layer INS10 can be partially recessed at each of the plurality of trenches TRC.

[0171] At least one trench TRC can be disposed between adjacent pixels PX1, PX2, and PX3. Although Figure 8 two trenches TRC are illustrated as being disposed between adjacent pixels PX1, PX2, and PX3, the disclosure is not limited thereto.

[0172] The light emitting stack ES can include a plurality of stack layers. Figure 8 A three-series structure including a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3 is illustrated for the light emitting stack ES, but the disclosure is not limited thereto. For example, the light emitting stack ES can have a two-series structure including two intermediate layers.

[0173] ​In the triple series structure, the light emitting stack ES can have a series structure including a plurality of stack layers IL1, IL2, and IL3 that emit different light. For example, the light emitting stack ES can include a first stack layer IL1 that emits light of a first color, a second stack layer IL2 that emits light of a third color, and a third stack layer IL3 that emits light of a second color. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 can be sequentially stacked.

[0174] The first stack layer IL1 can have a structure in which a first hole transport layer, a first organic light emitting layer that emits light of a first color, and a first electron transport layer are sequentially stacked. The second stack layer IL2 can have a structure in which a second hole transport layer, a second organic light emitting layer that emits light of a third color, and a second electron transport layer are sequentially stacked. The third stack layer IL3 can have a structure in which a third hole transport layer, a third organic light emitting layer that emits light of a second color, and a third electron transport layer are sequentially stacked.

[0175] A first charge generation layer for supplying a charge to the second stack layer IL2 and supplying an electron to the first stack layer IL1 can be disposed between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer can include an N-type charge generation layer that supplies an electron to the first stack layer IL1 and a P-type charge generation layer that supplies a hole to the second stack layer IL2. The N-type charge generation layer can include a dopant of a metal material.

[0176] A second charge generation layer for supplying a charge to the third stack layer IL3 and supplying an electron to the second stack layer IL2 can be disposed between the second stack layer IL2 and the third stack layer IL3. The second charge generation layer can include an N-type charge generation layer that supplies an electron to the second stack layer IL2 and a P-type charge generation layer that supplies a hole to the third stack layer IL3.

[0177] The first stack layer IL1 can be disposed on the first electrode AND and the pixel defining layer PDL, and can be disposed on a bottom surface of each of the trenches TRC. The first stack layer IL1 can be separated between the adjacent pixels PX1, PX2, and PX3 due to the trenches TRC. The second stack layer IL2 can be disposed on the first stack layer IL1. The second stack layer IL2 can be separated between the adjacent pixels PX1, PX2, and PX3 due to the trenches TRC. The cavity ESS or the blank space can be disposed between the first stack layer IL1 and the second stack layer IL2. The third stack layer IL3 can be disposed on the second stack layer IL2. The third stack layer IL3 can not be cut by the trenches TRC, and can be disposed to cover the second stack layer IL2 in each of the trenches TRC. For example, in a three-in-series structure, each of the plurality of trenches TRC can be a structure for cutting the first stack layer IL1 and the second stack layer IL2 of the display element layer EML, the first charge generation layer, and the second charge generation layer between the pixels PX1, PX2, and PX3 adjacent to each other. In some embodiments, for example, in a two-in-series structure, each of the trenches TRC can be a structure for cutting the lower intermediate layer and the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer.

[0178] To stably cut the first stack layer IL1 and the second stack layer IL2 of the display element layer EML between the adjacent pixels PX1, PX2, and PX3, a height of each of the plurality of trenches TRC can be greater than a height of the pixel defining layer PDL. The height of each of the plurality of trenches TRC refers to a length of each of the plurality of trenches TRC in the third direction DR3. The height of the pixel defining layer PDL refers to a length of the pixel defining layer PDL in the third direction DR3. To cut the first stack layer to the third stack layer IL1, IL2, and IL3 of the display element layer EML between the adjacent pixels PX1, PX2, and PX3, another structure can exist instead of the trenches TRC. For example, instead of the trenches TRC, an inverted taper-shaped partition wall can be disposed on the pixel defining layer PDL.

[0179] The number of the stack layers IL1, IL2, and IL3 emitting different colors of light is not limited to Figure 9 the number shown in the middle. For example, the light emitting stack ES can include two intermediate layers. In this case, one of the two intermediate layers can be substantially the same as the first stack layer IL1, and the other can include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and supplying charges to the other intermediate layer can be disposed between the two intermediate layers.

[0180] In some embodiments, for example, Figure 5The first to third stack layers IL1, IL2, and IL3 are all disposed in the first to third emission areas EA1, EA2, and EA3, but the disclosure is not limited thereto. For example, the first stack layer IL1 can be disposed in the first emission area EA1 and can not be disposed in the second and third emission areas EA2 and EA3. Also, the second stack layer IL2 can be disposed in the second emission area EA2 and can not be disposed in the first and third emission areas EA1 and EA3. Further, the third stack layer IL3 can be disposed in the third emission area EA3 and can not be disposed in the first and second emission areas EA1 and EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0181] The second electrode CAT can be disposed on the third stack layer IL3. The second electrode CAT can be disposed on the third stack layer IL3 in each of the plurality of trenches TRC. The second electrode CAT can be formed of a transparent conductive material (TCO) such as ITO or IZO, which is capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of the semi-transmissive conductive material, light emission efficiency can be improved in each of the first to third pixels PX1, PX2, and PX3 due to a microcavity effect.

[0182] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE can include at least one inorganic layer TFE1 and TFE2 to prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE can include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0183] The first encapsulation inorganic layer TFE1 can be disposed on the second electrode CAT. The first encapsulation inorganic layer TFE1 can be formed as a multilayer in which one or more inorganic layers selected from silicon nitride (SiN x ), silicon oxynitride (SiON), and silicon oxide (SiO x ) are alternately stacked. The first encapsulation inorganic layer TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0184] The second encapsulation inorganic layer TFE2 can be disposed on the first encapsulation inorganic layer TFE1. The second encapsulation inorganic layer TFE2 can be formed of titanium oxide (TiO x ) or aluminum oxide (AlO x ), but the disclosure is not limited thereto. The second encapsulation inorganic layer TFE2 can be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic layer TFE2 can be less than the thickness of the first encapsulation inorganic layer TFE1.

[0185] The organic layer APL can be a layer for improving interface adhesion between the encapsulation layer TFE and the optical layer OPL. The organic layer APL can be an organic layer such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0186] The optical layer OPL can include a color filter layer CFL, a lens layer, a filler layer, a cover layer, and / or a polarizing plate.

[0187] The color filter layer CFL can include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 can be disposed on the organic layer APL.

[0188] The first color filter CF1 can overlap the first emission area EA1 of the first pixel PX1. The first color filter CF1 can transmit light of a first color (i.e., light of a blue band). The blue band can be about 370 nm to 460 nm. Accordingly, the first color filter CF1 can transmit light of the first color among light emitted from the first emission area EA1.

[0189] The second color filter CF2 can overlap the second emission area EA2 of the second pixel PX2. The second color filter CF2 can transmit light of a second color (i.e., light of a green band). The green band can be about 480 nm to 560 nm. Accordingly, the second color filter CF2 can transmit light of the second color among light emitted from the second emission area EA2.

[0190] The third color filter CF3 can overlap the third emission area EA3 of the third pixel PX3. The third color filter CF3 can transmit light of a third color (i.e., light of a red band). The red band can be about 600 nm to 750 nm. Accordingly, the third color filter CF3 can transmit light of the third color among light emitted from the third emission area EA3.

[0191] The lens layer LSL can include a plurality of lenses LNS. The plurality of lenses LNS can be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS can be a structure for improving a ratio of light directed to the front of the display device 10. Each of the plurality of lenses LNS can have a cross-sectional shape that is convex in the upward direction.

[0192] A fill layer FIL can be disposed on the lens layer LSL. For example, the fill layer FIL can be disposed on the plurality of lenses LNS. The fill layer FIL can have a refractive index (e.g., a predetermined refractive index) such that light propagates in the third direction DR3 at an interface between the fill layer FIL and the plurality of lenses LNS. Further, the fill layer FIL can be a planarization layer. The fill layer FIL can be an organic layer such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0193] A cover layer CVL can be disposed on the fill layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached onto the fill layer FIL. In this case, the fill layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can act as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be directly coated onto the fill layer FIL.

[0194] A polarizing plate POL can be disposed on one surface of the cover layer CVL. The polarizing plate POL can be a structure for preventing visibility reduction caused by reflection of external light. The polarizing plate POL can include a linear polarizing plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (a quarter wave plate), but the present disclosure is not limited thereto. However, when visibility reduction caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2, and CF3, the polarizing plate POL can be omitted.

[0195] Figure 10 FIG. 1 is a layout diagram illustrating a display area of a display panel according to one or more embodiments of the present disclosure. Figure 9

[0196] Figure 9 FIG. 2 is a cross-sectional view illustrating a display panel according to one or more embodiments of the present disclosure, taken along the line X-X’ of Figure 9

[0197] Referring to FIG. 1, Figure 10 A plurality of pixels can be disposed in the display area DAA. For example, Figure 9 FIG. 1 illustrates six pixels, i.e., first to sixth pixels PX1, PX2, PX3, PX4, PX5, and PX6.

[0198] ​​Each of the pixels PX1, PX2, PX3, PX4, PX5, and PX6 can include the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the first capacitor C1 (e.g., a MOS capacitor). In one or more embodiments, although not shown, each of the pixels PX1, PX2, PX3, PX4, PX5, and PX6 can further include a second capacitor C2. In this case, the second capacitor C2 can be a MOS capacitor.

[0199] Since the components of the pixels PX1, PX2, PX3, PX4, PX5, and PX6 are substantially the same, the first pixel PX1 will be described representatively.

[0200] The first pixel PX1 can include the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the first capacitor C1 arranged in a row along the first direction DR1. In one or more embodiments, when the first pixel PX1 further includes the second capacitor C2, the second capacitor C2 can be arranged between the fourth transistor T4 and the first capacitor C1.

[0201] Reference Figure 9 The first transistor T1 can include a first gate electrode GE1, a first source electrode SE1, a first drain electrode DE1, a first gate insulating layer Gox1, a first sidewall SW1, a first well region WA1, a first channel region CH1, and a first low-concentration impurity region LDD1. The first gate insulating layer Gox1 can be arranged (e.g., located or positioned) between the first channel region CH1 and the first gate electrode GE1. The first channel region CH1 can be arranged between the first source electrode SE1 and the first drain electrode DE1 in the first well region WA1. The first low-concentration impurity region LDD1 can be arranged between the first source electrode SE1 and the first channel region CH1 and between the first drain electrode DE1 and the first channel region CH1. The first sidewall SW1 can be arranged on side surfaces of the first gate insulating layer Gox1 and the first gate electrode GE1 to overlap the first low-concentration impurity region LDD1. In this case, in a plan view, the first sidewall SW1 can be arranged on the first low-concentration impurity region LDD1 to surround the side surfaces of the first gate insulating layer Gox1 and the side surfaces of the first gate electrode GE1.

[0202] The second transistor T2 (see Figure 10) can include a second gate electrode GE2, a second source electrode SE2, a second drain electrode DE2, a second gate insulating layer, a second sidewall, a second well region WA2, a second channel region, and a second low-concentration impurity region. The second gate insulating layer can be provided between the second channel region and the second gate electrode GE2. The second channel region can be provided between the second source electrode SE2 and the second drain electrode DE2 in the second well region WA2. The second low-concentration impurity region can be provided between the second source electrode SE2 and the second channel region and between the second drain electrode DE2 and the second channel region. The second sidewall can be provided on side surfaces of the second gate insulating layer and the second gate electrode GE2 to overlap the second low-concentration impurity region. In this case, in a plan view, the second sidewall can be provided on the second low-concentration impurity region to surround the side surfaces of the second gate insulating layer and the side surfaces of the second gate electrode GE2.

[0203] The third transistor T3 can include a third gate electrode GE3, a third source electrode SE3, a third drain electrode DE3, a third gate insulating layer Gox3, a third sidewall SW3, a third well region WA3, a third channel region CH3, and a third low-concentration impurity region LDD3. The third gate insulating layer Gox3 can be provided between the third channel region CH3 and the third gate electrode GE3. The third channel region CH3 can be provided between the third source electrode SE3 and the third drain electrode DE3 in the third well region WA3. The third low-concentration impurity region LDD3 can be provided between the third source electrode SE3 and the third channel region CH3 and between the third drain electrode DE3 and the third channel region CH3. The third sidewall SW3 can be provided on side surfaces of the third gate insulating layer Gox3 and the third gate electrode GE3 to overlap the third low-concentration impurity region LDD3. In this case, in a plan view, the third sidewall SW3 can be provided on the third low-concentration impurity region LDD3 to surround the side surfaces of the third gate insulating layer Gox3 and the side surfaces of the third gate electrode GE3.

[0204] The fourth transistor T4 (see Figure 9 ) can include a fourth gate electrode GE4, a fourth source electrode SE4, a fourth drain electrode DE4, a fourth gate insulating layer, a fourth sidewall, a fourth well region WA4, a fourth channel region, and a fourth low-concentration impurity region. The fourth gate insulating layer can be provided between the fourth channel region and the fourth gate electrode GE4. The fourth channel region can be provided between the fourth source electrode SE4 and the fourth drain electrode DE4 in the fourth well region WA4. The fourth low-concentration impurity region can be provided between the fourth source electrode SE4 and the fourth channel region and between the fourth drain electrode DE4 and the fourth channel region. The fourth sidewall can be provided on side surfaces of the fourth gate insulating layer and the fourth gate electrode GE4 to overlap the fourth low-concentration impurity region. In this case, in a plan view, the fourth sidewall can be provided on the fourth low-concentration impurity region to surround the side surfaces of the fourth gate insulating layer and the side surfaces of the fourth gate electrode GE4.

[0205] The first capacitor C1 can include a fifth gate electrode GE5, a fifth source electrode SE5, a fifth drain electrode DE5, a fifth gate insulating layer Gox5, a fifth sidewall SW5, a fifth well region WA5, a fifth channel region CH5, and a fifth low-concentration impurity region LDD5. The fifth gate insulating layer Gox5 can be disposed between the fifth channel region CH5 and the fifth gate electrode GE5. The fifth channel region CH5 can be disposed between the fifth source electrode SE5 and the fifth drain electrode DE5 in the fifth well region WA5. The fifth low-concentration impurity region LDD5 can be disposed between the fifth source electrode SE5 and the fifth channel region CH5 and between the fifth drain electrode DE5 and the fifth channel region CH5. The fifth sidewall SW5 can be disposed on side surfaces of the fifth gate insulating layer Gox5 and the fifth gate electrode GE5 to overlap the fifth low-concentration impurity region LDD5. In this case, in a plan view, the fifth sidewall SW5 can be disposed on the fifth low-concentration impurity region LDD5 to surround the side surfaces of the fifth gate insulating layer Gox5 and the side surfaces of the fifth gate electrode GE5.

[0206] In one or more embodiments, the second capacitor C2 can include a sixth gate electrode, a sixth source electrode, a sixth drain electrode, a sixth gate insulating layer, a sixth sidewall, a sixth well region, a sixth channel region, and a sixth low-concentration impurity region. The sixth gate insulating layer can be disposed between the sixth channel region and the sixth gate electrode. The sixth channel region can be disposed between the sixth source electrode and the sixth drain electrode in the sixth well region. The sixth low-concentration impurity region can be disposed between the sixth source electrode and the sixth channel region and between the sixth drain electrode and the sixth channel region. The sixth sidewall can be disposed on side surfaces of the sixth gate insulating layer and the sixth gate electrode to overlap the sixth low-concentration impurity region. In this case, in a plan view, the sixth sidewall can be disposed on the sixth low-concentration impurity region to surround the side surfaces of the sixth gate insulating layer and the side surfaces of the sixth gate electrode.

[0207] According to one or more embodiments, the bulk electrode of each of the first to fourth transistors T1 to T4, the first capacitor C1, and the second capacitor C2 can be disposed in a well region on the semiconductor substrate SSUB. In other words, like the source electrode or the drain electrode of each of the above-described transistors, the bulk electrode can be disposed in a separate well region.

[0208] According to one or more embodiments, the thicknesses of the gate insulating layers of at least two transistors can be different from each other. For example, as in Figure 9In the example shown in FIG. 1, the thickness TK1 (hereinafter, referred to as a first thickness) of the first gate insulating layer Gox1 provided in the first transistor T1 can be greater than the thickness TK3 (hereinafter, referred to as a third thickness) of the third gate insulating layer Gox3 provided in the third transistor T3, and the thickness TK3 of the third gate insulating layer Gox3 provided in the third transistor T3 can be greater than the thickness TK5 (hereinafter, referred to as a fifth thickness) of the fifth gate insulating layer Gox5 provided in the first capacitor C1. For example, the third thickness TK3 can be greater than the fifth thickness TK5 and smaller than the first thickness TK1.

[0209] According to one or more embodiments, each of the thickness of the second gate insulating layer of the second transistor T2 and the thickness of the fourth gate insulating layer of the fourth transistor T4 can be substantially the same (e.g., substantially equal) as the above-described third thickness TK3. For example, the thickness of the gate insulating layer of the other transistors (e.g., the second transistor T2 to the fourth transistor T4) can be the same except for the first transistor T1 which is the driving transistor. In other words, among the first transistor T1 to the fourth transistor T4, the first transistor T1 which is the driving transistor can include the gate insulating layer having the greatest thickness TK1 (e.g., the greatest thickness among the gate insulating layers of the first transistor T1 to the fourth transistor T4).

[0210] According to one or more embodiments, the thickness of the sixth gate insulating layer provided in the second capacitor C2 can be substantially the same (e.g., substantially equal) as the thickness of the fifth gate insulating layer Gox5 provided in the first capacitor C1. In one or more embodiments, the thickness of the sixth gate insulating layer can be greater than the thickness TK5 of the fifth gate insulating layer Gox5 and smaller than the thickness of the gate insulating layer provided in any one of the second transistor T2 to the fourth transistor T4. For example, the thickness of the sixth gate insulating layer can be greater than the thickness TK5 of the fifth gate insulating layer Gox5 and can be smaller than the thickness TK3 of the third gate insulating layer.

[0211] Since the first transistor T1 which is the driving transistor includes the relatively thick first gate insulating layer Gox1, the distance between the first gate electrode GE1 and the first channel region CH1 can be increased. Accordingly, the channel resistance of the first transistor T1 can be increased, so that a characteristic curve representing a ratio of a drain current according to a gate-source voltage of the first transistor T1 can have a gentle slope (e.g., a more gentle slope). Thus, the operation range in the linear region of the first transistor T1 can be increased, thereby allowing fine gray scale representation of the display device. For example, increasing the thickness of the first gate insulating layer Gox1 can allow the display device to display gray scale values more finely compared to a thinner first gate insulating layer Gox1.

[0212] In one or more embodiments, the third transistor T3 of the switching transistor includes a third gate insulating layer Gox3 having a thickness greater than that of the fifth gate insulating layer Gox5 and less than that of the first gate insulating layer Gox1, such that the distance between the third gate electrode GE3 and the third channel region CH3 can be smaller than the distance between the first channel region CH1 and the first gate electrode GE1 of the first transistor T1. Therefore, the channel resistance of the third transistor T3 can be reduced, allowing the characteristic curve representing the ratio of leakage current to the gate-source voltage of the third transistor T3 to have a steep slope. Thus, the on / off switching capability of the third transistor T3 can be improved. For the same reasons as the third transistor T3 described above, other switching transistors such as the second transistor T2 and the fourth transistor T4 can also have improved on / off switching capabilities.

[0213] Furthermore, since the first capacitor C1 includes a relatively thin fifth gate insulating layer Gox5, the distance between the fifth gate electrode GE5 and the fifth channel region CH5 (or the distance between the fifth gate electrode GE5 and the semiconductor substrate SSUB) is shortened, and therefore, the capacitance of the first capacitor C1 can be increased.

[0214] According to one or more embodiments, the transistors and capacitors of adjacent pixels can be symmetrically arranged such that the first transistor T1 of adjacent pixels is close to each other. For example, as Figures 11 to 23 As shown, a first pixel PX1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a first capacitor C1 arranged sequentially along a first direction DR1. A second pixel PX2, adjacent to the first pixel PX1 in the opposite direction of the first direction DR1 (hereinafter referred to as the first reverse direction), may also include the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the first capacitor C1 arranged sequentially along the first reverse direction. Accordingly, the first transistor T1 of the first pixel PX1 and the first transistor T1 of the second pixel PX2 may be adjacent to each other in the first direction DR1.

[0215] For example, such as Figure 11 As shown, the first pixel PX1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a first capacitor C1 arranged sequentially along the first direction DR1. The third pixel PX3, adjacent to the first pixel PX1 in the first direction DR1, may include the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the first capacitor C1 arranged sequentially along the first reverse direction. Accordingly, the first capacitor C1 of the first pixel PX1 and the first capacitor C1 of the third pixel PX3 may be adjacent to each other in the first direction DR1.

[0216] According to one or more embodiments, in one pixel, the first capacitor C1 and the first transistor T1 that is a driving transistor can be disposed farthest from each other. For example, the first transistor T1 can be disposed at one edge of the first pixel PX1 and the first capacitor C1 can be disposed at the other edge (e.g., opposite edge) of the first pixel PX1, such that the first transistor T1 and the first capacitor C1 of the first pixel PX1 are farthest from each other in the first direction DR1.

[0217] Figure 11 is a process sectional view illustrating a method for manufacturing a display apparatus according to one or more embodiments.

[0218] As shown in Figure 12 , the first well region WA1, the third well region WA3, and the fifth well region WA5 can be formed on the semiconductor substrate SSUB. Here, the semiconductor substrate can be, for example, a P-type semiconductor substrate SSUB, and each of the first well region WA1, the third well region WA3, and the fifth well region WA5 can be an N-type well region. Thereafter, as shown in Figure 13 , a first base insulating layer BIN1 can be disposed on (e.g., across) the semiconductor substrate SSUB including the well regions. The first base insulating layer BIN1 can be made of SiO x .

[0219] Next, as shown in Figure 14 , a first photoresist pattern PR1 can be disposed on the first base insulating layer BIN1. The first photoresist pattern PR1 can be disposed on the first base insulating layer BIN1 to cover (or overlap with) the well regions except for the fifth well region WA5.

[0220] Thereafter, as shown in Figure 15 , the first base insulating layer BIN1 can be selectively removed using the first photoresist pattern PR1 as a mask. For example, the first base insulating layer BIN1 can be partially removed from a region (e.g., the fifth well region WA5) that is not covered by the first photoresist pattern PR1. In other words, a portion of the first base insulating layer BIN1 on the fifth well region WA5 can be removed. Accordingly, the first base insulating layer BIN1 can be patterned to have a small thickness in the fifth well region WA5 than in the first well region WA1 and the third well region WA3. According to one or more embodiments, the first base insulating layer BIN1 can be removed by an etching (e.g., dry etching) method.

[0221] Next, as shown in Figure 16 , the first photoresist pattern PR1 on the patterned first base insulating layer BIN1 can be removed. The first photoresist pattern PR1 can be removed by a stripping solution.

[0222] Thereafter, as shown in Figure 17 , a second base insulating layer BIN2 can be formed on the patterned first base insulating layer BIN1. The second base insulating layer BIN2 can be formed on the entire surface of the semiconductor substrate including the first base insulating layer BIN1. In this case, since the patterned first base insulating layer BIN1 has a small thickness in the fifth well region WA5, the second base insulating layer BIN2 on the first base insulating layer BIN1 can also have a small thickness in the fifth well region WA5. The second base insulating layer BIN2 can be made of SiO x .

[0223] According to one or more embodiments, the second base insulating layer BIN2 can include the same material as the first base insulating layer BIN1. However, the present disclosure is not limited thereto, and the second base insulating layer BIN2 and the first base insulating layer BIN1 can include different materials so that the second base insulating layer BIN2 and the first base insulating layer BIN1 have different etching rates.

[0224] Next, as shown in Figure 18 , a second photoresist pattern PR2 can be disposed on the second base insulating layer BIN2. The second photoresist pattern PR2 can be disposed on the second base insulating layer BIN2 to cover (or overlap with) the well regions other than the third well region WA3 and the fifth well region WA5 (e.g., the first well region WA1).

[0225] Thereafter, as shown in Figure 19 , the second base insulating layer BIN2 can be selectively removed using the second photoresist pattern PR2 as a mask. For example, the second base insulating layer BIN2 can be removed from the regions (e.g., the third well region WA3 and the fifth well region WA5) not covered by the second photoresist pattern PR2. In other words, the second base insulating layer BIN2 on the third well region WA3 and the fifth well region WA5 can be removed. Accordingly, the second base insulating layer BIN2 can be patterned to be selectively disposed only on the first well region WA1. According to one or more embodiments, the second base insulating layer BIN2 can be removed by an etching (e.g., dry etching) method.

[0226] Next, as shown in Figure 20As shown, the second photoresist pattern PR2 on the patterned second substrate insulating layer BIN2 can be removed. The second photoresist pattern PR2 can be removed by a stripping solution. Accordingly, substrate insulating layers BIN having different thicknesses TK1, TK3, and TK5 can be formed. For example, a substrate insulating layer BIN can be formed having a first thickness TK1 (maximum thickness) in the first well region WA1, a third thickness TK3 (smaller than the first thickness TK1) in the third well region WA3, and a fifth thickness TK5 (minimum thickness) in the fifth well region WA5. Here, when the first substrate insulating layer BIN1 and the second substrate insulating layer BIN2 are made of different materials, the substrate insulating layer BIN can have an interface between the first substrate insulating layer BIN1 and the second substrate insulating layer BIN2. In one or more embodiments, when the first substrate insulating layer BIN1 and the second substrate insulating layer BIN2 are made of the same material, the first substrate insulating layer BIN1 and the second substrate insulating layer BIN2 can be integrally formed without an interface.

[0227] Next, as Figure 21 As shown, the first gate electrode GE1 can be disposed on the substrate insulating layer BIN (e.g., the second substrate insulating layer BIN2) to overlap with the first well region WA1, the third gate electrode GE3 can be disposed on the substrate insulating layer BIN (e.g., the first substrate insulating layer BIN1) to overlap with the third well region WA3, and the fifth gate electrode GE5 can be disposed on the substrate insulating layer BIN (e.g., the first substrate insulating layer BIN1) to overlap with the fifth well region WA5. According to one or more embodiments, each of the first gate electrode GE1, the third gate electrode GE3, and the fifth gate electrode GE5 can be made of polysilicon.

[0228] After that, as Figure 10 As shown, a low-concentration ion (e.g., N-) implantation process can be performed using the first gate electrode GE1, the third gate electrode GE3, and the fifth gate electrode GE5 as masks (e.g., hard masks). Due to the low-concentration ion implantation process, a first low-concentration impurity region LDD1 can be formed in the first well region WA1, a third low-concentration impurity region LDD3 can be formed in the third well region WA3, and a fifth low-concentration impurity region LDD5 can be formed in the fifth well region WA5.

[0229] Next, as Figure 22As shown, the first gate electrode GE1, the third gate electrode GE3, and the fifth gate electrode GE5 can be used as masks to selectively remove the substrate insulating layer BIN. Accordingly, a first gate insulating layer Gox1 with a first thickness TK1 can be formed between the first gate electrode GE1 and the first well region WA1; a third gate insulating layer Gox3 with a third thickness TK3 can be formed between the third gate electrode GE3 and the third well region WA3; and a fifth gate insulating layer Gox5 with a fifth thickness TK5 can be formed between the fifth gate electrode GE5 and the fifth well region WA5. According to one or more embodiments, when the first substrate insulating layer BIN1 and the second substrate insulating layer BIN2 are made of different materials, the first gate insulating layer Gox1 may include a first sub-gate insulating layer formed by the first substrate insulating layer BIN1 and a second sub-gate insulating layer formed by the second substrate insulating layer BIN2, and an interface may exist between the first sub-gate insulating layer and the second sub-gate insulating layer. In one or more embodiments, when the first base insulating layer BIN1 and the second base insulating layer BIN2 are made of the same material, the first gate insulating layer Gox1 may be formed from a base insulating layer BIN that does not include the interface (e.g., see...). Figure 23 ).

[0230] Next, as Figures 11 to 23 As shown, a first sidewall SW1 can be formed on the side surface of the first gate insulating layer Gox1 and the first gate electrode GE1 to overlap with the first low concentration impurity region LDD1, a third sidewall SW3 can be formed on the side surface of the third gate insulating layer Gox3 and the third gate electrode GE3 to overlap with the third low concentration impurity region LDD3, and a fifth sidewall SW5 can be formed on the side surface of the fifth gate insulating layer Gox5 and the fifth gate electrode GE5 to overlap with the fifth low concentration impurity region LDD5.

[0231] Next, as Figure 24 As shown, a high-concentration ion (e.g., N+) implantation process can be performed using the first gate electrode GE1, the first sidewall SW1, the third gate electrode GE3, the third sidewall SW3, the fifth gate electrode GE5, and the fifth sidewall SW5 as masks. Due to the high-concentration ion implantation process, the first source electrode SE1 and the first drain electrode DE1 can be formed in the region of the first low-concentration impurity region LDD1 not covered by the first sidewall SW1; the third source electrode SE3 and the third drain electrode DE3 can be formed in the region of the third low-concentration impurity region LDD3 not covered by the third sidewall SW3; and the fifth source electrode SE5 and the fifth drain electrode DE5 can be formed in the region of the fifth low-concentration impurity region LDD5 not covered by the fifth sidewall SW5. For example, by using high-concentration ion implantation for reverse doping, exposed regions in low-concentration impurity regions can be converted into high-concentration impurity regions. Accordingly, a first transistor T1, a third transistor T3, and a first capacitor C1 can be fabricated.

[0232] In one or more embodiments, the second transistor T2 and the fourth transistor T4 can be manufactured by the same method as that of the third transistor T3 described above, and the second capacitor C2 can be manufactured by the same method as that of the first capacitor C1 described above. In this case, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first capacitor C1, and the second capacitor C2 can be substantially simultaneously manufactured by the processes shown in FIGS. 1A to 1C described above. Figure 25

[0233] Figure 24 is a perspective view illustrating a head-mounted display according to one or more embodiments of the present disclosure. Figure 24 is an exploded perspective view illustrating a head-mounted display according to one or more embodiments of the present disclosure. Figure 25

[0234] Referring to Figure 1 and Figure 2 , the head-mounted display 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0235] The first display device 10_1 provides an image to the left eye of a user, and the second display device 10_2 provides an image to the right eye of the user. Since each of the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 described in connection with Figure 24 and Figure 25 , a description of the first display device 10_1 and the second display device 10_2 is omitted.

[0236] The first optical member 1510 can be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 can be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 can include at least one convex lens.

[0237] The intermediate frame 1400 can be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 serves to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0238] ​​The control circuit board 1600 can be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 through connectors. The control circuit board 1600 can convert an image source input from the outside into digital video data DATA and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connectors.

[0239] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the left eye of the user to the first display device 10_1 and can transmit digital video data DATA corresponding to a right-eye image optimized for the right eye of the user to the second display device 10_2. In one or more embodiments, the control circuit board 1600 can transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0240] The display device housing 1100 serves to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is disposed to cover one open surface of the display device housing 1100. The housing cover 1200 can include a first eyepiece 1210 disposed with the left eye of the user and a second eyepiece 1220 disposed with the right eye of the user. Figure 26 and Figure 26 It is illustrated that the first eyepiece 1210 and the second eyepiece 1220 are separately disposed, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be incorporated into one.

[0241] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical member 1520. Accordingly, the user can view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0242] The head-mounted band 1300 serves to fix the display device housing 1100 to the head of the user so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively maintained to be disposed on the left eye and the right eye of the user. When the display device housing 1100 is implemented to be light in weight and compact, as Figure 26 The head-mounted display 1000 can be provided with a spectacle frame instead of the head-mounted band 1300 as shown in

[0243] In some embodiments, for example, the head-mounted display 1000 can further include a battery for power supply, an external memory slot for accommodating an external memory, and an external connection port for receiving an image source and a wireless communication module. The external connection port can be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module can be a 5G communication module, a 4G communication module, a WiFi module, or a Bluetooth module.

[0244] Figure 26 is a perspective view illustrating a head-mounted display according to one or more embodiments of the disclosure.

[0245] Referring to ​ The head-mounted display 1000_1 according to one or more embodiments can be a glasses-type display device in which a display device housing 1200_1 is implemented in a light-weight and compact manner. The head-mounted display 1000_1 according to one or more embodiments can include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temple pieces 1040 and 1050, an optical member 1060, an optical path changing member 1070, and the display device housing 1200_1.

[0246] The display device housing 1200_1 can include the display device 10_3, the optical member 1060, and the optical path changing member 1070. An image displayed on the display device 10_3 can be magnified by the optical member 1060 and can be provided to the right eye of the user through the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user can view an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image seen through the right-eye lens 1020 are combined through the right eye.

[0247] ​ It is illustrated that the display device housing 1200_1 is disposed at the right end of the support frame 1030, but the disclosure is not limited thereto. For example, the display device housing 1200_1 can be disposed at the left end of the support frame 1030, and in this case, an image of the display device 10_3 can be provided to the left eye of the user. In one or more embodiments, the display device housing 1200_1 can be disposed at both the left end and the right end of the support frame 1030, and in this case, the user can view an image displayed on the display device 10_3 through both the left eye and the right eye.

[0248] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. It will be appreciated by persons skilled in the art that numerous variations on the embodiments described herein will fall within the scope of the disclosure. Accordingly, any measure of the scope of the disclosure is intended to include all such variations as can fall within the scope of one or more claims and their equivalents. It is intended that the scope of the disclosure and the descriptions thereof be determined by the following claims, and that changes in these technical scopes, which consist of a combination of technical features disclosed in the specification and / or accompanying drawings, can be made without departing from the gist of the disclosure. Therefore, the technical scope of the disclosure should be interpreted by the claims and the equivalents thereof.

Claims

1. A display device comprising: a substrate including a first well region, a third well region, and a fifth well region; a first source electrode and a first drain electrode in the first well region; a third source electrode and a third drain electrode in the third well region; a fifth source electrode and a fifth drain electrode in the fifth well region; a first gate electrode over a first channel region of the first well region; a third gate electrode over a third channel region of the third well region; a fifth gate electrode over a fifth channel region of the fifth well region; a first gate insulating layer between the first channel region and the first gate electrode; a third gate insulating layer between the third channel region and the third gate electrode; a fifth gate insulating layer between the fifth channel region and the fifth gate electrode; a first electrode connected to the first drain electrode; a light-emitting layer over the first electrode; and a second electrode over the light-emitting layer, wherein at least two of the first gate insulating layer, the third gate insulating layer, and the fifth gate insulating layer have different thicknesses from each other. The thickness of the third gate insulating layer is greater than the thickness of the fifth gate insulating layer and less than the thickness of the first gate insulating layer.

2. The display device according to claim 1, wherein 3. The display device according to claim 2, further comprising: a first transistor including the first gate electrode, the first source electrode, the first drain electrode, and the first gate insulating layer; a third transistor including the third gate electrode, the third source electrode, the third drain electrode, and the third gate insulating layer; and a first capacitor including the fifth gate electrode, the fifth source electrode, the fifth drain electrode, and the fifth gate insulating layer. The third transistor is connected between a drive voltage line and the first source electrode of the first transistor.

5. The display device according to claim 3, further comprising:

4. The display device according to claim 3, wherein a second transistor connected between a data line and the first gate electrode of the first transistor. The second transistor includes: a second source electrode and a second drain electrode in a second well region of the substrate; 6. The display device of claim 5, wherein, a second gate electrode over a second channel region of the second well region; and a second gate insulating layer between the second channel region and the second gate electrode. The thickness of the second gate insulating layer is equal to the thickness of the third gate insulating layer.

8. The display device according to claim 3, further comprising:

7. The display device of claim 6, wherein, a fourth transistor connected between an initialization voltage line and the first drain electrode of the first transistor. The fourth transistor includes: a fourth source electrode and a fourth drain electrode in a fourth well region of the substrate; 9. The display device of claim 8, wherein, a fourth gate electrode over a fourth channel region of the fourth well region; and a fourth gate insulating layer between the fourth channel region and the fourth gate electrode. The thickness of the fourth gate insulating layer is equal to the thickness of the third gate insulating layer. ​ 10. The display device of claim 9, wherein, ​

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