Display device

Abstract

A display device includes: a plurality of data lines disposed in a display area and extending in a first direction; a plurality of gate lines disposed in the display area, and the plurality of gate lines extending in a second direction intersecting the first direction; a plurality of bypassing data lines electrically connected to the plurality of data lines, and the plurality of bypassing data lines are disposed in a first peripheral area adjacent to the display area; and a plurality of bypassing gate lines electrically connected to the plurality of gate lines, the plurality of bypassing gate lines disposed in the first peripheral region, and the plurality of bypassing gate lines alternately disposed in at least two layers.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display device providing visual information. BACKGROUND

[0002] The display device includes a display area displaying an image and a non-display area disposed outside the display area. Pixels for displaying the image and wirings connected to the pixels are disposed in the display area. In the non-display area, a driver for driving the pixels and a functional module such as a camera module and a sensor module are disposed.

[0003] Recently, a hole can be formed inside the display area to reduce a useless space caused by the non-display area. The functional module can be disposed on the back of the display device to correspond to the hole, and the functional module can detect or recognize an object, a user, etc. disposed on the front of the display device through the hole. In the case where the hole is formed inside the display area, the wirings disposed in the display area can bypass the hole. Accordingly, the wirings are disposed adjacent to edges of the hole so that an image is not displayed, and a peripheral area surrounding the hole can be formed. SUMMARY

[0004] The disclosure provides a display device having improved display quality.

[0005] A display device according to an embodiment of the disclosure can include a plurality of data lines disposed in a display area and extending in a first direction, a plurality of gate lines disposed in the display area and extending in a second direction intersecting the first direction, a plurality of bypass data lines electrically connected to the plurality of data lines and disposed in a first peripheral area adjacent to the display area, and a plurality of bypass gate lines electrically connected to the plurality of gate lines, the plurality of bypass gate lines being disposed in the first peripheral area and alternately disposed in at least two layers.

[0006] In an embodiment, the display area can include a first pixel, a second pixel spaced apart from the first pixel in the second direction, a third pixel spaced apart from the first pixel in a direction opposite to the first direction, and a fourth pixel spaced apart from the third pixel in the second direction, and the plurality of gate lines can include a first gate line electrically connected to the first pixel and extending in the second direction, a second gate line electrically connected to the second pixel and extending in the second direction, a third gate line electrically connected to the third pixel and extending in the second direction, a fourth gate line electrically connected to the fourth pixel and extending in the second direction, a fifth gate line electrically connected to the first pixel, the second pixel, the third pixel, and the fourth pixel and extending in the second direction, and a sixth gate line electrically connected to the first pixel, the second pixel, the third pixel, and the fourth pixel and extending in the second direction.

[0007] In an embodiment, the plurality of bypass gate lines can include first, second, third, fourth, fifth, and sixth bypass gate lines electrically connected to the first, second, third, fourth, fifth, and sixth gate lines, respectively, and disposed in the first peripheral area, and the first, second, fifth, third, fourth, and sixth bypass gate lines can be alternately disposed in the at least two layers.

[0008] In an embodiment, the first, fourth, and fifth bypass gate lines can be disposed on different layers from the second, third, and sixth bypass gate lines.

[0009] In an embodiment, the first gate line can be spaced apart from the fifth gate line by a gap in a range of about 2 μm to about 3.5 μm.

[0010] In an embodiment, one of the plurality of data lines can be electrically connected to the first, second, third, and fourth pixels.

[0011] In an embodiment, the display device can further include a first gate driver electrically connected to the first and third gate lines, a second gate driver electrically connected to the second and fourth gate lines, a third gate driver electrically connected to the fifth gate line, and a fourth gate driver electrically connected to the sixth gate line. The first and third gate drivers can be disposed at one side of a second peripheral area, and the second and fourth gate drivers can be disposed at the other side of the second peripheral area to be spaced apart from the one side of the second peripheral area in the second direction, and the display area is interposed between the one side and the other side of the second peripheral area.

[0012] In an embodiment, the plurality of bypass data lines can be disposed on the plurality of bypass gate lines.

[0013] In an embodiment, the plurality of bypass data lines can be disposed on the same layer.

[0014] In an embodiment, the display device can further include a driving voltage line disposed between the plurality of bypass data lines and the plurality of bypass gate lines in a cross-sectional view. In a plan view, the driving voltage line can overlap the plurality of bypass gate lines.

[0015] In an embodiment, the first peripheral area can be disposed between the display area and a hole area.

[0016] In an embodiment, the display area can include a first pixel, a second pixel spaced apart from the first pixel in the second direction, a third pixel spaced apart from the first pixel in a direction opposite to the first direction, and a fourth pixel spaced apart from the third pixel in the second direction, and the plurality of gate lines can include a first gate line electrically connected to the first pixel and extending in the second direction, a second gate line electrically connected to the second pixel and extending in the second direction, a third gate line electrically connected to the third pixel and extending in the second direction, a fourth gate line electrically connected to the fourth pixel and extending in the second direction, a fifth gate line electrically connected to the first, second, third, and fourth pixels and extending in the second direction, a sixth gate line electrically connected to the first, second, third, and fourth pixels and extending in the second direction, a seventh gate line electrically connected to the first, second, third, and fourth pixels and extending in the second direction, and an eighth gate line electrically connected to the first, second, third, and fourth pixels and extending in the second direction.

[0017] In an embodiment, the plurality of bypass gate lines can include first, second, third, fourth, fifth, sixth, seventh, and eighth bypass gate lines respectively electrically connected to the first, second, third, fourth, fifth, sixth, seventh, and eighth gate lines and disposed in the first peripheral area, and the first, fifth, second, sixth, third, seventh, fourth, and eighth bypass gate lines can be alternately disposed in the at least two layers.

[0018] In an embodiment, the first, second, third, and fourth gate lines and the fifth, sixth, seventh, and eighth gate lines can be alternately disposed on different layers.

[0019] In an embodiment, the first gate line can be spaced apart from the second gate line by a gap in a range of about 2 μm to about 3.5 μm.

[0020] In an embodiment, one of the plurality of data lines can be electrically connected to the first, second, third, and fourth pixels.

[0021] In an embodiment, the display device can further include a first gate driver electrically connected to the first and third gate lines, a second gate driver electrically connected to the second and fourth gate lines, a third gate driver electrically connected to the fifth gate line, a fourth gate driver electrically connected to the sixth gate line, a fifth gate driver electrically connected to the seventh gate line, and a sixth gate driver electrically connected to the eighth gate line. The first, third, and fifth gate drivers can be disposed at one side of a second peripheral area, and the second, fourth, and sixth gate drivers can be disposed at the other side of the second peripheral area to be spaced apart from the one side of the second peripheral area in a second direction, and the display area is interposed between the one side and the other side of the second peripheral area.

[0022] In an embodiment, the plurality of bypass data lines can be disposed on the plurality of bypass gate lines.

[0023] In an embodiment, the plurality of bypass data lines can be disposed on the same layer.

[0024] In an embodiment, the display device can further include a driving voltage line disposed between the plurality of looped data lines and the plurality of looped gate lines in a cross-sectional view. In a plan view, the driving voltage line can overlap the plurality of looped gate lines.

[0025] In the display device according to an embodiment of the disclosure, the planar areas of the plurality of looped gate lines spaced apart from each other can be reduced by alternately disposing the plurality of looped gate lines on (in) two layers. In short, by arranging the looped gate lines spaced apart on (in) different layers in a cross-sectional view to prevent coupling, it is possible to ensure that the size of the display area in which the pixels emit light is wide.

[0026] Accordingly, it is possible to reduce the planar size of the surrounding area surrounding the hole area in the display device, and a user can efficiently use a wider screen when using the display device. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0028] Figure 1 is a perspective view for explaining a display device according to an embodiment of the disclosure.

[0029] Figure 2 is a schematic block diagram for explaining Figure 1 a display device.

[0030] Figure 3 is an enlarged view for explaining a pixel and a gate line disposed in Figure 2 Area A.

[0031] Figure 4 is an enlarged view for explaining a pixel and a data line disposed in Figure 2 Area A.

[0032] Figure 5 is a plan view for explaining a pixel, a gate line, and a data line disposed in Figure 2 Area A.

[0033] Figure 6 is a schematic diagram for explaining an equivalent circuit of one of a plurality of pixels included in Figure 2 a display device.

[0034] Figure 7 is a schematic cross-sectional view taken along Figure 2 line I-I'.

[0035] Figure 8 is an enlarged view for explainingFigure 1 A plan view of the surrounding gate lines and surrounding data lines in the aperture region and the first peripheral region.

[0036] Figure 9 It is along Figure 8 A schematic cross-sectional view taken from line II-II'.

[0037] Figure 10 This is a perspective view used to illustrate a display device according to another embodiment of the present disclosure.

[0038] Figure 11 It is used for explanation Figure 10 A schematic block diagram of a display device.

[0039] Figure 12 It is used to explain the settings Figure 11 A magnified view of the pixels and gate lines in region B.

[0040] Figure 13 It is used to explain the settings Figure 11 A magnified view of the pixels and data lines in region B.

[0041] Figure 14 It is used to explain the settings Figure 11 A planar view of pixels, gate lines, and data lines in region B.

[0042] Figure 15 It is used to illustrate that it includes Figure 11 A schematic diagram of the equivalent circuit of one of a plurality of pixels in a display device.

[0043] Figure 16 It is used to explain the settings Figure 10 A plan view of the surrounding gate lines and surrounding data lines in the aperture region and the first peripheral region.

[0044] Figure 17 It is along Figure 16 A schematic cross-sectional view taken from line III-III'. Detailed Implementation

[0045] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0046] In this specification, a plane may be defined by a first direction D1 and a second direction D2 intersecting the first direction D1. For example, the second direction D2 may be perpendicular to the first direction D1. Furthermore, a third direction D3 may be the normal direction of the plane. For example, the third direction D3 may be perpendicular to the plane formed by the first direction D1 and the second direction D2.

[0047] When an element or layer is referred to as being “on”, “connected to”, or “coupled to” another element or layer, it can be directly on, connected, or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” can refer to physical, electrical, and / or fluidic connectivity in the presence of intervening elements or in the absence of intervening elements. Additionally, when an element is referred to as being “in contact” with another element, etc., the element can be “in electrical contact” or “in physical contact” with the other element; or “indirectly in contact” or “directly in contact” with the other element.

[0048] “About” or “approximately,” as used in this disclosure, includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0049] For purposes of the description hereinafter, spatial or directional terms, such as “below”, “under”, “below”, “lower”, “above”, “upper”, “over”, “higher”, and “side” (e.g., as in “sidewall”), are used with respect to the illustrated orientation of the device as shown in the figures. The spatial or directional terms are used for purposes of the description and the associated drawings and are not intended to be construed as a limitation of the scope of the disclosure. Unless specifically stated otherwise, the spatial or directional terms are intended to encompass all standard positional deviations and orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is turned over, elements described as “below” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both the up and down orientations in accordance with a particular point of view. Moreover, the device can be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and thus, spatially relative descriptions used herein are to be interpreted according to the particular orientation in use.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "comprises," "comprising," "includes," "including," and / or "contains," "containing," are used in the specification, these terms are intended to be inclusive in a manner similar to the terms "comprises" and / or "contains" as these terms are interpreted when employed as descriptive terms in the patent law context. This detailed description is not intended to be limiting.

[0051] Unless otherwise defined or implied herein, all terms used are intended to have the same meaning as commonly understood by one of ordinary skill in the art in the field of the disclosure. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the specification.

[0052] Figure 1 is a perspective view for illustrating a display device according to an embodiment of the disclosure.

[0053] Referring to Figure 1 , the display device DD can include a display area DA that emits light and a peripheral area SA that does not emit light. In a plan view, the peripheral area SA can include a first peripheral area SA1 surrounded by the display area DA and a second peripheral area SA2 surrounding the display area DA. The display device DD can provide an image using light emitted from a plurality of pixels (e.g., pixels PX in Figure 2 ).

[0054] The display device DD can include a hole area HL. The hole area HL can be at least partially surrounded by the display area DA. For example, as shown in Figure 1 , the hole area HL can be completely surrounded by the display area DA. The first peripheral area SA1 can surround the hole area HL. For example, the first peripheral area SA1 can completely surround the hole area HL, the display area DA can completely surround the first peripheral area SA1, and the second peripheral area SA2 can completely surround the display area DA. Accordingly, the first peripheral area SA1 can be disposed between the display area DA and the hole area HL. However, embodiments of the disclosure are not limited thereto.

[0055] The hole area HL can be a transmissive area through which light or / and sound can be output from the display device DD to the outside or through which light or / and sound can be transmitted from the outside.Figure 1 In the present embodiment, the hole region HL is shown to have a circular shape, but embodiments of the present disclosure are not limited thereto. The shape of the hole region HL can also be an elliptical shape or a polygonal shape.

[0056] Figure 2 is a schematic block diagram of a display device for explaining Figure 1 . Figure 3 is an enlarged view for explaining a pixel and a gate line provided in Figure 2 region A. Figure 4 is an enlarged view for explaining a pixel and a data line provided in Figure 2 region A. Figure 5 is a plan view for explaining a pixel, a gate line, and a data line provided in Figure 2 region A. For example, Figure 5 is a plan view showing Figure 3 and Figure 4 overlap.

[0057] Referring to Figures 2 to 5 , the display device DD can include a display panel PNL, a data driver DIC, data lines DL, a gate driver GIC, gate lines GL, a control portion TC, and a power driver PS.

[0058] The display panel PNL can be provided in a display region (e.g., the display region DA in Figure 1 ). The data driver DIC, the data lines DL, the gate driver GIC, the gate lines GL, the control portion TC, and the power driver PS can be provided in a second peripheral region (e.g., the second peripheral region SA2 of Figure 1 ).

[0059] A plurality of pixels PX can be provided in the display panel PNL. The pixels PX can include first pixels PX1, second pixels PX2, third pixels PX3, and fourth pixels PX4. In a plan view, the pixels PX can be repeatedly provided in a matrix form in a first direction D1 and / or a second direction D2.

[0060] For example, the first pixels PX1 and the second pixels PX2 can be adjacent to each other in the second direction D2. For example, the second pixels PX2 can be spaced apart from the first pixels PX1 in the second direction D2. Likewise, the third pixels PX3 can be spaced apart from the first pixels PX1 in a direction opposite to the first direction D1. The fourth pixels PX4 can be spaced apart from the third pixels PX3 in the second direction D2. However, embodiments of the present disclosure are not limited thereto.

[0061] Each of the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 can emit red light, green light, and / or blue light. However, embodiments of the present disclosure are not limited thereto. Each of the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 can emit a combination of colors of red light, green light, and / or blue light.

[0062] The data driver DIC can be spaced apart from the display panel PNL in the first direction D1. The data driver DIC can supply data signals to data lines DL in response to a data control signal provided from the control portion TC. The data lines DL can extend in the first direction D1. The data lines DL can be spaced apart from each other in the second direction D2 and can transmit data signals to the pixels PX.

[0063] One of the plurality of data lines DL can transmit a data signal to the first pixel PX1 and the second pixel PX2. In an embodiment, one of the data lines DL can transmit a data signal to the pixels PX disposed in two columns. For example, as shown in FIG. 1, one of the data lines DL can transmit a data signal to the first pixel PX1 and the second pixel PX2 at the same time. Figure 2

[0064] The gate driver GIC can be disposed at both sides of the display panel PNL. For example, the gate driver GIC can be disposed at both sides of the display panel PNL in the second direction D2. The gate driver GIC can supply gate signals to gate lines GL in response to a gate control signal provided from the control portion TC. The gate lines GL can extend in the second direction D2. The gate lines GL can be spaced apart from each other in the first direction D1 and can transmit gate signals to the pixels PX.

[0065] The gate driver GIC can include a first gate driver GIC1, a second gate driver GIC2, a third gate driver GIC3, and a fourth gate driver GIC4. For example, the first gate driver GIC1 and the third gate driver GIC3 can be spaced apart from the display panel PNL in a direction opposite to the second direction D2. For example, the second gate driver GIC2 and the fourth gate driver GIC4 can be spaced apart from the display panel PNL in the second direction D2. For example, the second gate driver GIC2 and the fourth gate driver GIC4 can be disposed at one side of the second peripheral area SA2 to be spaced apart from the first gate driver GIC1 and the third gate driver GIC3 in the second direction D2 with the display area DA interposed therebetween. However, embodiments of the present disclosure are not limited thereto.

[0066] ​The gate lines GL can include a first gate line GL1, a second gate line GL2, a third gate line GL3, a fourth gate line GL4, a fifth gate line GL5, and a sixth gate line GL6. The first gate line GL1, the second gate line GL2, the third gate line GL3, the fourth gate line GL4, the fifth gate line GL5, and the sixth gate line GL6 can extend in the second direction D2 and be disposed in the display panel PNL. The gate lines GL can be spaced apart from each other in the first direction D1. The gate lines GL can transmit gate signals to the pixels PX.

[0067] The first gate line GL1 can be electrically connected to the first gate driver GIC1 and the first pixel PX1. For example, the first gate line GL1 can receive a first gate signal from the first gate driver GIC1 and transmit the first gate signal to the first pixel PX1. The first gate signal can be a gate write signal (e.g., a gate write signal GW) of the first pixel PX1. Figure 6

[0068] The second gate line GL2 can be electrically connected to the second gate driver GIC2 and the second pixel PX2. For example, the second gate line GL2 can receive a second gate signal from the second gate driver GIC2 and transmit the second gate signal to the second pixel PX2. The second gate signal can be a gate write signal (e.g., a gate write signal GW) of the second pixel PX2. Figure 6

[0069] The third gate line GL3 can be electrically connected to the first gate driver GIC1 and the third pixel PX3. For example, the third gate line GL3 can receive a third gate signal from the first gate driver GIC1 and transmit the third gate signal to the third pixel PX3. The third gate signal can be a gate write signal (e.g., a gate write signal GW) of the third pixel PX3. Figure 6

[0070] The fourth gate line GL4 can be electrically connected to the second gate driver GIC2 and the fourth pixel PX4. For example, the fourth gate line GL4 can receive a fourth gate signal from the second gate driver GIC2 and transmit the fourth gate signal to the fourth pixel PX4. The fourth gate signal can be a gate write signal (e.g., a gate write signal GW) of the fourth pixel PX4. Figure 6

[0071] The fifth gate line GL5 can be electrically connected to the third gate driver GIC3 and the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4. For example, the fifth gate line GL5 can receive a fifth gate signal from the third gate driver GIC3 and transmit the fifth gate signal to the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4. The fifth gate signal can be a gate initialization signal (e.g., a gate initialization signal GI of the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4.​​​​Figure 6 a gate initialization signal (e.g., GI in FIG. 1A), Figure 6 a gate compensation signal (e.g., GC in FIG. 1A), or Figure 6 a gate bias signal (e.g., GB in FIG. 1A).

[0072] The sixth gate line GL6 can be electrically connected to the fourth gate driver GIC4 and the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4. For example, the sixth gate line GL6 can receive a sixth gate signal from the fourth gate driver GIC4 and transmit the sixth gate signal to the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4. The sixth gate signal can be an emission control signal (e.g., EM in FIG. 1A). Figure 6

[0073] Figure 6 is a schematic view for explaining an equivalent circuit of one of a plurality of pixels included in a display device of Figure 2 FIG. 1A.

[0074] Referring to Figure 2 and Figure 6 , each of the plurality of pixels PX of the display device DD can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a first capacitor C1 and a second capacitor C2, and a light emitting diode LED.

[0075] The first transistor T1 can include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 can be connected to the first electrode of the first capacitor C1. The first electrode of the first transistor T1 can be connected to the first electrode of the third transistor T3. A driving voltage ELVDD can be applied to the second electrode of the first transistor T1.

[0076] The second transistor T2 can include a gate electrode, a first electrode, and a second electrode. A gate write signal GW can be applied to the gate electrode of the second transistor T2. The first electrode of the second transistor T2 can be connected to the second electrode of the first capacitor C1. A data signal DATA can be applied to the second electrode of the second transistor T2.

[0077] The third transistor T3 can include a gate electrode, a first electrode, and a second electrode. A gate compensation signal GC can be applied to the gate electrode of the third transistor T3. The first electrode of the third transistor T3 can be connected to the first electrode of the first transistor T1. The second electrode of the third transistor T3 can be connected to the first electrode of the first capacitor C1.

[0078] ​The fourth transistor T4 can include a gate electrode, a first electrode, and a second electrode. A gate initialization signal GI can be applied to the gate electrode of the fourth transistor T4. A first initialization voltage VINT can be applied to the first electrode of the fourth transistor T4. The second electrode of the fourth transistor T4 can be connected to the second electrode of the third transistor T3.

[0079] The fifth transistor T5 can include a gate electrode, a first electrode, and a second electrode. A gate compensation signal GC can be applied to the gate electrode of the fifth transistor T5. A driving voltage ELVDD can be applied to the first electrode of the fifth transistor T5. The second electrode of the fifth transistor T5 can be connected to the second electrode of the first capacitor C1.

[0080] The sixth transistor T6 can include a gate electrode, a first electrode, and a second electrode. An emission control signal EM can be applied to the gate electrode of the sixth transistor T6. The first electrode of the sixth transistor T6 can be connected to the first electrode of the seventh transistor T7. The second electrode of the sixth transistor T6 can be connected to the first electrode of the third transistor T3.

[0081] The seventh transistor T7 can include a gate electrode, a first electrode, and a second electrode. A gate bias signal GB can be applied to the gate electrode of the seventh transistor T7. The first electrode of the seventh transistor T7 can be connected to the first electrode of the sixth transistor T6. A second initialization voltage VAINT can be applied to the second electrode of the seventh transistor T7.

[0082] The first capacitor C1 can include a first electrode and a second electrode. The first electrode of the first capacitor C1 can be connected to the gate electrode of the first transistor T1. The second electrode of the first capacitor C1 can be connected to the first electrode of the second transistor T2. The first capacitor C1 can be a storage capacitor.

[0083] The second capacitor C2 can include a first electrode and a second electrode. The first electrode of the second capacitor C2 can be connected to the second electrode of the first capacitor C1. A driving voltage ELVDD can be applied to the second electrode of the second capacitor C2. The second capacitor C2 can be a sustain capacitor.

[0084] The light emitting diode LED can include a first electrode and a second electrode. The first electrode of the light emitting diode LED can be connected to the first electrode of the sixth transistor T6. A common voltage ELVSS can be applied to the second electrode of the light emitting diode LED.

[0085] Figure 7 is a schematic cross-sectional view taken along the line I-I' of Figure 2

[0086] Referring to Figure 2 and Figure 7 ​The display device DD can include a substrate SUB, a buffer layer BF, a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, and a fourth insulating layer IL4, a transistor TR, a second gate electrode GE2 and a third gate electrode GE3, a conductive pattern CP, a via layer VIA, a light emitting diode LED, a pixel definition layer PDL, a encapsulation layer CL, and the like. The transistor TR can include an active layer ACT, a first gate electrode GE1, a source electrode SE, and a drain electrode DE, and the light emitting diode LED can include a pixel electrode PE, a light emitting layer EL, and a common electrode CE.

[0087] The substrate SUB can be a glass substrate, a metal substrate, a plastic substrate, or the like. However, embodiments of the present disclosure are not limited thereto, and the substrate SUB can be an inorganic layer, an organic layer, or a composite material layer.

[0088] The buffer layer BF can be provided on the substrate SUB. The buffer layer BF can prevent impurities such as oxygen and moisture from penetrating into an upper portion of the substrate SUB. The buffer layer BF can include an inorganic insulating material.

[0089] The active layer ACT can be provided on the buffer layer BF. The active layer ACT can include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, or the like. For example, the oxide semiconductor can include indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), zinc (Zn), or a combination thereof. The silicon semiconductor can include amorphous silicon, polysilicon, or the like. The active layer ACT can include a source region, a drain region, and a channel region provided between the source region and the drain region.

[0090] The first insulating layer IL1 can be provided on the buffer layer BF and the active layer ACT. For example, the first insulating layer IL1 can be provided on the buffer layer BF and cover the active layer ACT. The first insulating layer IL1 can include a silicon compound, a metal oxide, a metal nitride, or the like. The silicon compound that can be used in the first insulating layer IL1 can include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon carbide (SiC x ), silicon oxycarbide (SiO x C y ), silicon oxynitride (SiO x N y ), and silicon carbon nitride (SiC x N y ). The metal oxide and the metal nitride that can be used in the first insulating layer IL1 can include aluminum oxide (Al x O y ), aluminum nitride (Al x Ny ), tantalum oxide (Ta x O y ), hafnium oxide (Hf x O y ), zirconium oxide (Zr x O y ), and titanium oxide (Ti x O y ). These can be used alone or in combination with each other. In another embodiment, the first insulating layer IL1 can have a multi-layer structure including a plurality of insulating layers.

[0091] The first gate electrode GE1 can be disposed on the first insulating layer IL1. In a plan view, the first gate electrode GE1 can overlap the channel region of the active layer ACT. The first gate electrode GE1 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In another embodiment, the first gate electrode GE1 can have a multi-layer structure including a plurality of metal layers.

[0092] The second insulating layer IL2 can be disposed on the first insulating layer IL1 and the first gate electrode GE1. For example, the second insulating layer IL2 can be disposed on the first insulating layer IL1 and cover the first gate electrode GE1. The second insulating layer IL2 can include a silicon compound, a metal oxide, a metal nitride, etc. These can be used alone or in combination with each other. In another embodiment, the second insulating layer IL2 can have a multi-layer structure including a plurality of insulating layers.

[0093] The second gate electrode GE2 can be disposed on the second insulating layer IL2. In a plan view, the second gate electrode GE2 can overlap the first gate electrode GE1. The second gate electrode GE2 can form a capacitor together with the first gate electrode GE1. The second gate electrode GE2 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In another embodiment, the second gate electrode GE2 can have a multi-layer structure including a plurality of metal layers.

[0094] The third insulating layer IL3 can be disposed on the second insulating layer IL2 and the second gate electrode GE2. For example, the third insulating layer IL3 can be disposed on the second insulating layer IL2 and cover the second gate electrode GE2. The third insulating layer IL3 can include a silicon compound, a metal oxide, a metal nitride, etc. These can be used alone or in combination with each other. In another embodiment, the third insulating layer IL3 can have a multi-layer structure including a plurality of insulating layers.

[0095] A third gate electrode GE3 can be disposed on the third insulating layer IL3. The third gate electrode GE3 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In another embodiment, the third gate electrode GE3 can have a multi-layer structure including a plurality of metal layers.

[0096] A fourth insulating layer IL4 can be disposed on the third insulating layer IL3 and the third gate electrode GE3. For example, the fourth insulating layer IL4 can be disposed on the third insulating layer IL3 and cover the third gate electrode GE3. The fourth insulating layer IL4 can include a silicon compound, a metal oxide, a metal nitride, etc. These can be used alone or in combination with each other. In another embodiment, the fourth insulating layer IL4 can have a multi-layer structure including a plurality of insulating layers.

[0097] The source electrode SE, the drain electrode DE, and the conductive pattern CP can be disposed on the fourth insulating layer IL4. The conductive pattern CP can be connected to the third gate electrode GE3 through a contact hole formed by removing a portion of the fourth insulating layer IL4. The source electrode SE can be connected to a source region of the active layer ACT through a contact hole formed by removing a portion of each of the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4, and the drain electrode DE can be connected to a drain region of the active layer ACT through a contact hole formed by removing a portion of each of the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4. Each of the conductive pattern CP, the source electrode SE, and the drain electrode DE can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In another embodiment, each of the conductive pattern CP, the source electrode SE, and the drain electrode DE can have a multi-layer structure including a plurality of metal layers.

[0098] A via layer VIA can be disposed on the fourth insulating layer IL4, the conductive pattern CP, the source electrode SE, and the drain electrode DE. The via layer VIA can cover the conductive pattern CP, the source electrode SE, and the drain electrode DE. For example, the via layer VIA can include an organic material or an inorganic material. The organic material that can be used in the via layer VIA can include a photoresist, a polyacrylic-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acryl-based resin, an epoxy-based resin, etc. These can be used alone or in combination with each other.

[0099] The pixel electrode PE can be disposed on the via layer VIA. The pixel electrode PE can be connected to the drain electrode DE through a contact hole formed by removing a portion of the via layer VIA. The pixel electrode PE can be an anode electrode. The pixel electrode PE can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These can be used alone or in combination with each other. In another embodiment, the pixel electrode PE can have a multi-layer structure including a plurality of metal layers.

[0100] The pixel definition layer PDL can be disposed on the via layer VIA and the pixel electrode PE. The pixel definition layer PDL can cover side surfaces of the pixel electrode PE and expose at least a portion of a top surface of the pixel electrode PE. The pixel definition layer PDL can include an organic material or an inorganic material.

[0101] The light emitting layer EL can be disposed on the pixel electrode PE. The light emitting layer EL can emit red light, green light, or blue light. The light emitting layer EL can include a hole injection layer, a hole transport layer, an organic emission layer, an electron transport layer, and an electron injection layer.

[0102] A common electrode CE can be disposed on the light emitting layer EL. The common electrode CE can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These can be used alone or in combination with each other. In another embodiment, the common electrode CE can have a multi-layer structure including a plurality of metal layers. The common electrode CE can be a cathode electrode.

[0103] Although the display device DD of the disclosure is described based on an organic light emitting diode (OLED) display device according to an embodiment, the configuration of the disclosure is not limited thereto. In other embodiments, the display device DD can be a liquid crystal display (LCD) device, a field emission display (FED) device, a plasma display panel (PDP) display device, or an electrophoretic display (EPD) device.

[0104] Figure 8 is a plan view for explaining the bypass gate lines and the bypass data lines disposed in the hole region and the first peripheral region of Figure 1 .

[0105] Referring to Figure 1 and Figure 8 , the first bypass gate line RGL1 and the bypass data line RDL can be disposed adjacent to the hole region HL of the display device DD.

[0106] The first bypass gate line RGL1 can be disposed in the first peripheral region SA1. The first bypass gate line RGL1 can bypass the hole region HL along the first peripheral region SA1. For example, as Figure 8As shown in FIG. 1, the first routing gate line RGL1 can be connected to the first gate line GL1 and can be disposed in the first peripheral area SA1 surrounding the hole area HL. In Figure 8 In FIG. 1, only one routing gate line (i.e., the first routing gate line RGL1) is provided, but embodiments of the disclosure are not limited thereto. The first peripheral area SA1 can further include at least one more routing gate line (see Figure 9 ).

[0107] The routing data line RDL can be disposed in the first peripheral area SA1. The routing data line RDL can be disposed in the first peripheral area SA1 to bypass the hole area HL along the first peripheral area SA1. For example, as shown in FIG. 1, the routing data line RDL can be connected to one of the plurality of data lines DL and can be disposed in the first peripheral area SA1 to bypass the hole area HL. Figure 8

[0108] Figure 9 is a schematic cross-sectional view taken along line II-II' of Figure 8 As described in some configurations in FIG. 1 can be repeated with the configurations described in FIG. 2, so repeated contents can be omitted or simplified. Figure 9 Figure 7 Referring to and

[0109] , the substrate SUB, the buffer layer BF, the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4, the via layer VIA, the first routing gate line RGL1, the second routing gate line RGL2, the third routing gate line RGL3, the fourth routing gate line RGL4, the fifth routing gate line RGL5, and the sixth routing gate line RGL6, the driving voltage line DVL, and the first routing data line RDL1 and the second routing data line RDL2 can be disposed in the hole area HL (see Figure 7 ). Figure 9 Figure 8 In an embodiment, the first routing gate line RGL1, the second routing gate line RGL2, the third routing gate line RGL3, the fourth routing gate line RGL4, the fifth routing gate line RGL5, and the sixth routing gate line RGL6 can be alternately disposed in different layers. For example, the first routing gate line RGL1, the second routing gate line RGL2, the third routing gate line RGL3, the fourth routing gate line RGL4, the fifth routing gate line RGL5, and the sixth routing gate line RGL6 can be alternately disposed on the first insulating layer IL1 and the second insulating layer IL2.

[0110]

[0111] ​​​The first, fourth, and fifth runaround gate lines RGL1, RGL4, and RGL5 can be disposed on the same layer. The first, fourth, and fifth runaround gate lines RGL1, RGL4, and RGL5 can be disposed on the first insulating layer IL1. For example, the first, fourth, and fifth runaround gate lines RGL1, RGL4, and RGL5 can be disposed on the first insulating layer IL1 and can be covered by the second insulating layer IL2.

[0112] In an embodiment, the first and fifth runaround gate lines RGL1 and RGL5 can be disposed at a separation distance DT in the second direction D2. For example, the separation distance DT can be in a range of about 2 µm to about 5 µm. For example, the separation distance DT can be in a range of about 2 µm to about 3.5 µm. The separation distance DT can be a distance between each of the plurality of runaround gate lines disposed on the same layer. By arranging the runaround gate lines at the separation distance DT, coupling between the runaround gate lines can be prevented.

[0113] The second, third, and sixth runaround gate lines RGL2, RGL3, and RGL6 can be disposed on the same layer. The second, third, and sixth runaround gate lines RGL2, RGL3, and RGL6 can be disposed on the second insulating layer IL2. For example, the second, third, and sixth runaround gate lines RGL2, RGL3, and RGL6 can be disposed on the second insulating layer IL2 and can be covered by the third insulating layer IL3.

[0114] The first and second runaround data lines RDL1 and RDL2 can be disposed on the fourth insulating layer IL4. For example, the first and second runaround data lines RDL1 and RDL2 can be disposed on the same layer. However, embodiments of the disclosure are not limited thereto.

[0115] Since the first, fourth, and fifth runaround gate lines RGL1, RGL4, and RGL5 are disposed on the first insulating layer IL1 and the second, third, and sixth runaround gate lines RGL2, RGL3, and RGL6 are disposed on the second insulating layer IL2, the size of the first peripheral area SA1 can be reduced. In short, since the first, second, third, fourth, fifth, and sixth runaround gate lines RGL1, RGL2, RGL3, RGL4, RGL5, and RGL6 are alternately disposed in different layers, the size of the area disposed in the second direction D2 can be reduced.

[0116] However, embodiments of the disclosure are not limited thereto. The first runaround gate line RGL1, the second runaround gate line RGL2, the third runaround gate line RGL3, the fourth runaround gate line RGL4, the fifth runaround gate line RGL5, and the sixth runaround gate line RGL6 can be freely alternately disposed with each other on the first insulating layer IL1 and the second insulating layer IL2. The first runaround gate line RGL1, the second runaround gate line RGL2, the third runaround gate line RGL3, the fourth runaround gate line RGL4, the fifth runaround gate line RGL5, and the sixth runaround gate line RGL6 can be disposed on an insulating layer other than the first insulating layer IL1 and the second insulating layer IL2.

[0117] The driving voltage line DVL can be disposed on the third insulating layer IL3. The driving voltage line DVL can transmit a driving voltage (e.g., a driving voltage ELVDD) to the pixels (e.g., the pixels PX in the pixel PX). Figure 6 Figure 2 The driving voltage line DVL can transmit the driving voltage to the pixels (e.g., the pixels PX in the pixel PX).

[0118] In an embodiment, in a plan view, the driving voltage line DVL can overlap the first runaround gate line RGL1, the second runaround gate line RGL2, the third runaround gate line RGL3, the fourth runaround gate line RGL4, the fifth runaround gate line RGL5, and the sixth runaround gate line RGL6. Since, in a cross-sectional view, the driving voltage line DVL can be between the first runaround gate line RGL1, the second runaround gate line RGL2, the third runaround gate line RGL3, the fourth runaround gate line RGL4, the fifth runaround gate line RGL5, and the sixth runaround gate line RGL6 and the first runaround data line RDL1 and the second runaround data line RDL2, a coupling effect between the first runaround gate line RGL1, the second runaround gate line RGL2, the third runaround gate line RGL3, the fourth runaround gate line RGL4, the fifth runaround gate line RGL5, and the sixth runaround gate line RGL6 and the first runaround data line RDL1 and the second runaround data line RDL2 can be prevented.

[0119] The first runaround data line RDL1 and the second runaround data line RDL2 can be disposed on the fourth insulating layer IL4. The first runaround data line RDL1 and the second runaround data line RDL2 can transmit a data signal to the pixels (e.g., the pixels PX in the pixel PX). As Figure 2 indicated in FIG. 1A, each of the first runaround data line RDL1 and the second runaround data line RDL2 can apply a data signal to the pixels PX disposed in two columns. Figure 2

[0120] Figure 10 is a perspective view for explaining a display device according to another embodiment of the disclosure. Figure 10 may have the same configuration as Figure 1 ​​The configuration described in

[0121] Reference Figure 10 , the display device DD' can include a display area DA' that emits light and a peripheral area SA' that does not emit light. The peripheral area SA' can include a first peripheral area SA1' surrounded by the display area DA' and a second peripheral area SA2' surrounding the display area DA'.

[0122] The display device DD' can include a hole region HL'. The hole region HL' can be at least partially surrounded by the display area DA'. For example, as shown in Figure 10 The hole region HL' can be completely surrounded by the display area DA' as shown in

[0123] Figure 11 is a schematic block diagram for explaining a display device of Figure 10 . Figure 12 is an enlarged view for explaining a pixel and a gate line provided in a region B of Figure 11 . Figure 13 is an enlarged view for explaining a pixel and a data line provided in a region B of Figure 11 . Figure 14 is a plan view for explaining a pixel, a gate line, and a data line provided in a region B of Figure 11 . Figure 14 is a plan view showing Figure 12 and Figure 13 overlapping each other. Figure 11 , Figure 12 , Figure 13 and Figure 14 can have substantially the same configuration as that described in Figure 2 , Figure 3 , Figure 4 and Figure 5 . Thus, the repeated content can be omitted or simplified.

[0124] Reference Figure 11 , Figure 12 , Figure 13 and Figure 14 , the display device DD' can include a display panel PNL', a data driver DIC', a data line DL', a gate driver GIC', a gate line GL', a control portion TC', and a power driver PS'.

[0125] A plurality of pixels PX' can be provided in the display panel PNL'. The pixel PX' can include a first pixel PX1', a second pixel PX2', a third pixel PX3', and a fourth pixel PX4'. In a plan view, the pixels PX' can be repeatedly provided in a matrix form in a first direction D1 and / or a second direction D2.

[0126] The data driver DIC' can be spaced apart from the display panel PNL' in the first direction D1. The data driver DIC' can supply data signals to the data lines DL' in response to a data control signal provided from the control part TC'. The data lines DL' can extend in the first direction D1. The data lines DL' can be spaced apart from each other in the second direction D2, and can transmit data signals to the pixels PX'.

[0127] The gate driver GIC' can be disposed at both sides of the display panel PNL'. For example, the gate driver GIC' can be disposed at both sides of the display panel PNL' in the second direction D2. The gate driver GIC' can supply gate signals to the gate lines GL' in response to a gate control signal provided from the control part TC'. The gate lines GL' can extend in the second direction D2. The gate lines GL' can be spaced apart from each other in the first direction D1, and can transmit gate signals to the pixels PX'.

[0128] The gate driver GIC' can include a first gate driver GIC1', a second gate driver GIC2', a third gate driver GIC3', a fourth gate driver GIC4', a fifth gate driver GIC5', and a sixth gate driver GIC6'. For example, the first gate driver GIC1', the third gate driver GIC3', and the fifth gate driver GIC5' can be spaced apart from the display panel PNL' in a direction opposite to the second direction D2. In contrast, the second gate driver GIC2', the fourth gate driver GIC4', and the sixth gate driver GIC6' can be spaced apart from the display panel PNL' in the second direction D2. For example, the second gate driver GIC2', the fourth gate driver GIC4', and the sixth gate driver GIC6' can be disposed at one side of the second peripheral area SA2' to be spaced apart from the first gate driver GIC1', the third gate driver GIC3', and the fifth gate driver GIC5' in the second direction D2, and the display area DA' (see Figure 10 ) is interposed between the first gate driver GIC1', the third gate driver GIC3', and the fifth gate driver GIC5' and the second gate driver GIC2', the fourth gate driver GIC4', and the sixth gate driver GIC6'. However, embodiments of the present disclosure are not limited thereto.

[0129] The gate lines GL' can include a first gate line GL1', a second gate line GL2', a third gate line GL3', a fourth gate line GL4', a fifth gate line GL5', a sixth gate line GL6', a seventh gate line GL7', and an eighth gate line GL8'. The gate lines GL' can extend in the second direction D2 and be disposed in the display panel PNL'. The gate lines GL' can be spaced apart from each other in the first direction D1. The gate lines GL' can transmit a gate signal to the pixels PX'.

[0130] The first gate line GL1' can be electrically connected to the first gate driver GIC1' and the first pixel PX1'. For example, the first gate line GL1' can receive a first gate signal from the first gate driver GIC1' and transmit the first gate signal to the first pixel PX1'. The first gate signal can be a gate write signal (e.g., a gate write signal GW) of the first gate driver GIC1'. Figure 15

[0131] The second gate line GL2' can be electrically connected to the second gate driver GIC2' and the second pixel PX2'. For example, the second gate line GL2' can receive a second gate signal from the second gate driver GIC2' and transmit the second gate signal to the second pixel PX2'. The second gate signal can be a gate write signal (e.g., a gate write signal GW) of the second gate driver GIC2'. Figure 15

[0132] The third gate line GL3' can be electrically connected to the first gate driver GIC1' and the third pixel PX3'. For example, the third gate line GL3' can receive a third gate signal from the first gate driver GIC1' and transmit the third gate signal to the third pixel PX3'. The third gate signal can be a gate write signal (e.g., a gate write signal GW) of the first gate driver GIC1'. Figure 15

[0133] The fourth gate line GL4' can be electrically connected to the second gate driver GIC2' and the fourth pixel PX4'. For example, the fourth gate line GL4' can receive a fourth gate signal from the second gate driver GIC2' and transmit the fourth gate signal to the fourth pixel PX4'. The fourth gate signal can be a gate write signal (e.g., a gate write signal GW) of the second gate driver GIC2'. Figure 15

[0134] ​​​​The fifth gate line GL5' can be electrically connected to the third gate driver GIC3' and the first, second, third, and fourth pixels PX1', PX2', PX3', and PX4'. For example, the fifth gate line GL5' can receive a fifth gate signal from the third gate driver GIC3' and transmit the fifth gate signal to the first, second, third, and fourth pixels PX1', PX2', PX3', and PX4'. The fifth gate signal can be a gate initialization signal or a gate compensation signal (e.g., the gate initialization signal GI or the gate compensation signal GC in Figure 15 ).

[0135] The sixth gate line GL6' can be electrically connected to the fourth gate driver GIC4' and the first, second, third, and fourth pixels PX1', PX2', PX3', and PX4'. For example, the sixth gate line GL6' can receive a sixth gate signal from the fourth gate driver GIC4' and transmit the sixth gate signal to the first, second, third, and fourth pixels PX1', PX2', PX3', and PX4'. The third gate signal can be a gate bias signal (e.g., the gate bias signal GB in Figure 15 ).

[0136] The seventh gate line GL7' can be electrically connected to the fifth gate driver GIC5' and the first, second, third, and fourth pixels PX1', PX2', PX3', and PX4'. For example, the seventh gate line GL7' can receive a seventh gate signal from the fifth gate driver GIC5' and transmit the seventh gate signal to the first, second, third, and fourth pixels PX1', PX2', PX3', and PX4'. The seventh gate signal can be a first emission control signal (e.g., the first emission control signal EM1 in Figure 15 ).

[0137] The eighth gate line GL8' can be electrically connected to the sixth gate driver GIC6' and the first, second, third, and fourth pixels PX1', PX2', PX3', and PX4'. For example, the eighth gate line GL8' can receive an eighth gate signal from the sixth gate driver GIC6' and transmit the eighth gate signal to the first, second, third, and fourth pixels PX1', PX2', PX3', and PX4'. The eighth gate signal can be a second emission control signal (e.g., the second emission control signal EM2 in Figure 15 ).

[0138] Figure 11 is a schematic view for explaining an equivalent circuit of one of a plurality of pixels included in the display apparatus of Figure 11 .

[0139] Referring to Figure 15and Figure 16 Each of the plurality of pixels PX' of the display device DD' can include a first transistor T1', a second transistor T2', a third transistor T3', a fourth transistor T4', a fifth transistor T5', a sixth transistor T6', a seventh transistor T7', an eighth transistor T8', and a ninth transistor T9', a first capacitor C1' and a second capacitor C2', and a light emitting diode LED'.

[0140] The first transistor T1' can include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1' can be connected to the first electrode of the first capacitor C1'. The first electrode of the first transistor T1' can be connected to the first electrode of the third transistor T3'. The second electrode of the first transistor T1' can be connected to the second electrode of the eighth transistor T8'.

[0141] The second transistor T2' can include a gate electrode, a first electrode, and a second electrode. A gate write signal GW can be applied to the gate electrode of the second transistor T2'. The first electrode of the second transistor T2' can be connected to the second electrode of the first capacitor C1'. A data signal DATA' can be applied to the second electrode of the second transistor T2'.

[0142] The third transistor T3' can include a gate electrode, a first electrode, and a second electrode. A gate compensation signal GC can be applied to the gate electrode of the third transistor T3'. The first electrode of the third transistor T3' can be connected to the first electrode of the first transistor T1'. The second electrode of the third transistor T3' can be connected to the first electrode of the first capacitor C1'.

[0143] The fourth transistor T4' can include a gate electrode, a first electrode, and a second electrode. A gate initialization signal GI can be applied to the gate electrode of the fourth transistor T4'. A first initialization voltage VINT can be applied to the first electrode of the fourth transistor T4'. The second electrode of the fourth transistor T4' can be connected to the second electrode of the third transistor T3'.

[0144] The fifth transistor T5' can include a gate electrode, a first electrode, and a second electrode. The gate compensation signal GC can be applied to the gate electrode of the fifth transistor T5'. A reference voltage VREF can be applied to the first electrode of the fifth transistor T5'. The second electrode of the fifth transistor T5' can be connected to the second electrode of the first capacitor C1'.

[0145] The sixth transistor T6' can include a gate electrode, a first electrode, and a second electrode. A second emission control signal EM2 can be applied to the gate electrode of the sixth transistor T6'. The first electrode of the sixth transistor T6' can be connected to the first electrode of the seventh transistor T7'. The second electrode of the sixth transistor T6' can be connected to the first electrode of the third transistor T3'.

[0146] The seventh transistor T7' can include a gate electrode, a first electrode, and a second electrode. A gate bias signal GB can be applied to the gate electrode of the seventh transistor T7'. The first electrode of the seventh transistor T7' can be connected to the first electrode of the sixth transistor T6'. A second initialization voltage VAINT can be applied to the second electrode of the seventh transistor T7'.

[0147] The eighth transistor T8' can include a gate electrode, a first electrode, and a second electrode. A bias control signal EB can be applied to the gate electrode of the eighth transistor T8'. A bias voltage VBIAS can be applied to the first electrode of the eighth transistor T8'. The second electrode of the eighth transistor T8' can be connected to the second electrode of the first transistor T1'.

[0148] The ninth transistor T9' can include a gate electrode, a first electrode, and a second electrode. A first emission control signal EM1 can be applied to the gate electrode of the ninth transistor T9'. The first electrode of the ninth transistor T9' can be connected to the second electrode of the first transistor T1'. A driving voltage ELVDD can be applied to the second electrode of the ninth transistor T9'.

[0149] The first capacitor C1' can include a first electrode and a second electrode. The first electrode of the first capacitor C1' can be connected to the gate electrode of the first transistor T1'. The second electrode of the first capacitor C1' can be connected to the first electrode of the second transistor T2'. The first capacitor C1' can be a storage capacitor.

[0150] The second capacitor C2' can include a first electrode and a second electrode. The first electrode of the second capacitor C2' can be connected to the second electrode of the first capacitor C1'. A driving voltage ELVDD can be applied to the second electrode of the second capacitor C2'. The second capacitor C2' can be a sustain capacitor.

[0151] The light emitting diode LED' can include a first electrode and a second electrode. The first electrode of the light emitting diode LED' can be connected to the first electrode of the sixth transistor T6'. A common voltage ELVSS can be applied to the second electrode of the light emitting diode LED'.

[0152] Figure 10 is for illustrating a configuration in which the first capacitor C1' and the second capacitor C2' are disposed in the sustain circuit 200. Figure 16a plan view of the bypass gate lines and the bypass data lines in the hole region and the first peripheral region. Since Figure 8 the configuration described in Figure 10 is substantially the same as the configuration described in , the repeated content can be omitted or simplified.

[0153] Figure 16 Referring to Figure 17 and , the bypass gate lines RGL' and the bypass data lines RDL' can be disposed adjacent to the hole region HL' of the display device DD'.

[0154] The bypass gate lines RGL' can be disposed in the first peripheral region SA1'. For example, the first bypass gate line RGL1' can bypass the hole region HL' along the first peripheral region SA1'.

[0155] The bypass data lines RDL' can be disposed in the first peripheral region SA1'. The bypass data lines RDL' can bypass the hole region HL' along the first peripheral region SA1'.

[0156] Figure 16 is a schematic cross-sectional view taken along line III-III' of Figure 17 . Since Figure 9 some of the configurations described in Figure 16 may be repeated with the configurations described in , the repeated content can be omitted or simplified.

[0157] Figure 17 Referring to Figure 15 and , the substrate SUB, the buffer layer BF, the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4, the via layer VIA, the first bypass gate line RGL1', the second bypass gate line RGL2', the third bypass gate line RGL3', the fourth bypass gate line RGL4', the fifth bypass gate line RGL5', the sixth bypass gate line RGL6', the seventh bypass gate line RGL7', and the eighth bypass gate line RGL8', the driving voltage line DVL', and the first bypass data line RDL1' and the second bypass data line RDL2' can be disposed in the hole region HL'.

[0158] In embodiments, the first, second, third, fourth, fifth, sixth, seventh, and eighth runaround gate lines RGL1', RGL2', RGL3', RGL4', RGL5', RGL6', RGL7', and RGL8' can be alternately disposed in different layers. For example, the first, second, third, fourth, fifth, sixth, seventh, and eighth runaround gate lines RGL1', RGL2', RGL3', RGL4', RGL5', RGL6', RGL7', and RGL8' can be alternately disposed on the first and fourth insulating layers IL1 and IL4.

[0159] The first, second, third, and fourth runaround gate lines RGL1', RGL2', RGL3', and RGL4' can be disposed on the same layer. The first, second, third, and fourth runaround gate lines RGL1', RGL2', RGL3', and RGL4' can be disposed on the fourth insulating layer IL4. For example, the first, second, third, and fourth runaround gate lines RGL1', RGL2', RGL3', and RGL4' can be disposed on the fourth insulating layer IL4 and covered by the via layer VIA.

[0160] In embodiments, the first and second runaround gate lines RGL1' and RGL2' can be disposed at a separation distance DT' in the second direction D2. For example, the separation distance DT' can be in a range from about 2 pm to about 5 pm. For example, the separation distance DT' can be in a range from about 2 pm to about 3.5 pm.

[0161] The fifth, sixth, seventh, and eighth runaround gate lines RGL5', RGL6', RGL7', and RGL8' can be disposed on the same layer. The fifth, sixth, seventh, and eighth runaround gate lines RGL5', RGL6', RGL7', and RGL8' can be disposed on the first insulating layer IL1. For example, the fifth, sixth, seventh, and eighth runaround gate lines RGL5', RGL6', RGL7', and RGL8' can be disposed on the first insulating layer IL1 and covered by the second insulating layer IL2.

[0162] The first, second, third, and fourth runaround gate lines RGL1', RGL2', RGL3', and RGL4' can be disposed on the fourth insulating layer IL4, and the fifth, sixth, seventh, and eighth runaround gate lines RGL5', RGL6', RGL7', and RGL8' can be disposed on the first insulating layer IL1, thereby reducing the size of the first peripheral area SA1'. In short, the first, second, third, fourth, fifth, sixth, seventh, and eighth runaround gate lines RGL1', RGL2', RGL3', RGL4', RGL5', RGL6', RGL7', and RGL8' can be alternately disposed on different layers, thereby the size of the area disposed in the second direction D2 can be reduced.

[0163] However, embodiments of the present disclosure are not limited thereto. The first, second, third, fourth, fifth, sixth, seventh, and eighth runaround gate lines RGL1', RGL2', RGL3', RGL4', RGL5', RGL6', RGL7', and RGL8' can be freely alternately disposed on the first and fourth insulating layers IL1 and IL4. The first, second, third, fourth, fifth, sixth, seventh, and eighth runaround gate lines RGL1', RGL2', RGL3', RGL4', RGL5', RGL6', RGL7', and RGL8' can be disposed on an insulating layer other than the first and fourth insulating layers IL1 and IL4.

[0164] The driving voltage line DVL' can be disposed on the second insulating layer IL2. The driving voltage line DVL' can transmit a driving voltage (e.g., a driving voltage ELVDD in Figure 11 Figure 11 The driving voltage line DVL' can transmit the driving voltage to a pixel (e.g., a pixel PX' of

[0165] ​In an embodiment, in a plan view, the drive voltage line DVL' can overlap the first routing gate line RGL1', the second routing gate line RGL2', the third routing gate line RGL3', the fourth routing gate line RGL4', the fifth routing gate line RGL5', the sixth routing gate line RGL6', the seventh routing gate line RGL7', and the eighth routing gate line RGL8'. The drive voltage line DVL' can prevent a coupling effect between the first routing gate line RGL1', the second routing gate line RGL2', the third routing gate line RGL3', and the fourth routing gate line RGL4' and the fifth routing gate line RGL5', the sixth routing gate line RGL6', the seventh routing gate line RGL7', and the eighth routing gate line RGL8' by being disposed between the first routing gate line RGL1', the second routing gate line RGL2', the third routing gate line RGL3', and the fourth routing gate line RGL4' and the fifth routing gate line RGL5', the sixth routing gate line RGL6', the seventh routing gate line RGL7', and the eighth routing gate line RGL8' in a cross-sectional view.

[0166] The first routing data line RDL1' and the second routing data line RDL2' can be disposed on the via layer VIA. For example, the first routing data line RDL1' and the second routing data line RDL2' can be disposed on the same layer. In another embodiment, in a cross-sectional view, the first routing data line RDL1' and the second routing data line RDL2' can be disposed on the first routing gate line RGL1', the second routing gate line RGL2', the third routing gate line RGL3', the fourth routing gate line RGL4', the fifth routing gate line RGL5', the sixth routing gate line RGL6', the seventh routing gate line RGL7', and the eighth routing gate line RGL8'.

[0167] The first routing data line RDL1' and the second routing data line RDL2' can transmit a data signal to a pixel (e.g., a pixel PX' of FIG. 1). Figure 11 As shown in FIG. 1, each of the first routing data line RDL1' and the second routing data line RDL2' can apply a data signal to the pixels PX' disposed in two columns. ​

[0168] ​Accordingly, since the first, second, third, fourth, fifth, sixth, seventh, and eighth circumferential gate lines RGL1', RGL2', RGL3', RGL4', RGL5', RGL6', RGL7', and RGL8' are alternately disposed on different layers in the first peripheral area SA1', the size of the first peripheral area SA1' can be reduced. In short, if the first, second, third, fourth, fifth, sixth, seventh, and eighth circumferential gate lines RGL1', RGL2', RGL3', RGL4', RGL5', RGL6', RGL7', and RGL8' are disposed on the same layer, a wide area extending in the second direction D2 is required, and the size in the second direction D2 can be reduced by alternately arranging the first, second, third, fourth, fifth, sixth, seventh, and eighth circumferential gate lines RGL1', RGL2', RGL3', RGL4', RGL5', RGL6', RGL7', and RGL8' on different layers, thereby reducing the size of the first peripheral area SA1'.

[0169] Accordingly, the planar size of the surrounding area surrounding the hole area in the display device can be reduced, and a user can effectively use a wider screen when using the display device.

[0170] The present disclosure can be applied to a display device and an electronic device including the display device. For example, the present disclosure can be applied to a high-resolution smart phone, a mobile phone, a smart pad, a smart watch, a tablet personal computer (PC), a car navigation system, a television, a computer monitor, a laptop computer, etc.

[0171] The above description is an example of technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and changes. Accordingly, the above-described embodiments of the present disclosure can be implemented alone or in combination with each other.

[0172] Accordingly, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The scope of protection of the present disclosure should be interpreted by the appended claims, and all technical spirits within the equivalent scope should be interpreted as included in the scope of the present disclosure.

Claims

1. A display device, characterized by comprising: The display device includes: a plurality of data lines disposed in a display area and extending in a first direction; a plurality of gate lines disposed in the display area and extending in a second direction intersecting the first direction; a plurality of bypass data lines electrically connected to the plurality of data lines and disposed in a first peripheral area adjacent to the display area; and a plurality of bypass gate lines electrically connected to the plurality of gate lines, the plurality of bypass gate lines disposed in the first peripheral area, and the plurality of bypass gate lines alternately disposed in at least two layers. 2.The display device of claim 1, wherein: the display area includes: a first pixel; a second pixel spaced apart from the first pixel in the second direction; a third pixel spaced apart from the first pixel in a direction opposite to the first direction; and a fourth pixel spaced apart from the third pixel in the second direction, and the plurality of gate lines includes: a first gate line electrically connected to the first pixel and extending in the second direction; a second gate line electrically connected to the second pixel and extending in the second direction; a third gate line electrically connected to the third pixel and extending in the second direction; a fourth gate line electrically connected to the fourth pixel and extending in the second direction; a fifth gate line electrically connected to the first pixel, the second pixel, the third pixel, and the fourth pixel and extending in the second direction; and a sixth gate line electrically connected to the first pixel, the second pixel, the third pixel, and the fourth pixel and extending in the second direction. 3.The display device of claim 2, wherein: the plurality of bypass gate lines includes a first bypass gate line, a second bypass gate line, a third bypass gate line, a fourth bypass gate line, a fifth bypass gate line, and a sixth bypass gate line electrically connected to the first gate line, the second gate line, the third gate line, the fourth gate line, the fifth gate line, and the sixth gate line, respectively, and disposed in the first peripheral area, and 4. The display device according to claim 3, wherein the first bypass gate line, the second bypass gate line, the fifth bypass gate line, the third bypass gate line, the fourth bypass gate line, and the sixth bypass gate line are alternately disposed in the at least two layers.

5. The display device according to claim 4, wherein the first bypass gate line, the fourth bypass gate line, and the fifth bypass gate line are disposed on different layers from the second bypass gate line, the third bypass gate line, and the sixth bypass gate line.

6. The display device according to claim 2, wherein the first gate line is spaced apart from the fifth gate line by a gap in a range of 2 µm to 3.5 µm.

7. The display device according to claim 1, wherein one of the plurality of data lines is electrically connected to the first pixel, the second pixel, the third pixel, and the fourth pixel. the plurality of bypass data lines are disposed on the plurality of bypass gate lines. 8.The display device of claim 1, wherein: the display area includes: a first pixel; a second pixel spaced apart from the first pixel in the second direction; a third pixel spaced apart from the first pixel in a direction opposite to the first direction; and a fourth pixel spaced apart from the third pixel in the second direction, and the plurality of gate lines include: a first gate line electrically connected to the first pixel and extending in the second direction; a second gate line electrically connected to the second pixel and extending in the second direction; a third gate line electrically connected to the third pixel and extending in the second direction; a fourth gate line electrically connected to the fourth pixel and extending in the second direction; a fifth gate line electrically connected to the first pixel, the second pixel, the third pixel, and the fourth pixel and extending in the second direction; a sixth gate line electrically connected to the first pixel, the second pixel, the third pixel, and the fourth pixel and extending in the second direction; a seventh gate line electrically connected to the first pixel, the second pixel, the third pixel, and the fourth pixel and extending in the second direction; and an eighth gate line electrically connected to the first pixel, the second pixel, the third pixel, and the fourth pixel and extending in the second direction. 9.The display device of claim 8, wherein the plurality of bypass gate lines include first, second, third, fourth, fifth, sixth, seventh, and eighth bypass gate lines electrically connected to the first, second, third, fourth, fifth, sixth, seventh, and eighth gate lines, respectively, and disposed in the first peripheral area, and the first, fifth, second, sixth, third, seventh, fourth, and eighth bypass gate lines are alternately disposed in the at least two layers.

10. The display device according to claim 9, wherein the first, second, third, and fourth gate lines are alternately disposed on different layers from the fifth, sixth, seventh, and eighth gate lines, and the first gate line is spaced apart from the second gate line by a gap in a range of 2 μm to 3.5 μm.

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