Semiconductor packaging structure

Abstract

The utility model belongs to the technical field of semiconductors, and provides a semiconductor packaging structure which comprises a lead frame, a first chip, a second chip, a third chip and a conductive metal layer, the lead frame is provided with a first chip carrying area, a second chip carrying area and a third chip carrying area, the first chip is inversely connected to the first chip carrying area, and the second chip is inversely connected to the third chip carrying area. The second chip is inversely connected to the second slide area, the third chip is positively connected to the third slide area, and the conductive metal layer is formed on the first chip, the second chip and the third chip. The first chip and the second chip are inversely arranged on the lead frame, the third chip is positively arranged on the lead frame, the interconnection among the first chip, the second chip and the third chip and the leading-out of functional pins are realized by utilizing the specially-made lead frame and the conductive metal layer, and meanwhile, the semiconductor packaging of a leadless structure is realized; the problems of large lead resistance and loop inductance caused by the lead are effectively avoided, and the performance of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor packaging structure. BACKGROUND

[0002] Drive MOSFET (DrMOS) is a power module composed of a drive IC and a MOSFET chip, which is widely used in power supply, motor drive and other fields. In order to improve the integration, the drive IC and the MOSFET chip (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) are usually packaged as one device. The emergence of this integration technology greatly improves the performance of the device. The DrMOS device usually includes a drive chip, an upper MOS chip (HSMOS) and a lower MOS chip (LSMOS), and the three chips are spread in a tiled form.

[0003] In the existing packaging method of the DrMOS device, part of the electrodes in the drive chip, the upper MOS chip and the lower MOS chip are electrically interconnected through a copper clamp, and various functional pin pads on the drive chip are led out through gold wires or copper wires. Although this connection method realizes the connection between the chips and the leading out of the functional pin pads, the thin diameter of the lead wires introduces high lead resistance and loop inductance, which adversely affects the performance of the DrMOS device. Based on the above problems, the present application provides a semiconductor packaging structure for reducing or avoiding the generation of lead resistance and loop inductance in the device. CONTENT OF THE UTILITY MODEL

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a semiconductor packaging structure to solve the technical problems of the prior art that the semiconductor packaging structure has high lead resistance and loop inductance.

[0005] To achieve the above-mentioned purpose and other related purposes, the present application provides a semiconductor packaging structure, which comprises a lead frame, a first chip, a second chip, a third chip and a conductive metal layer.

[0006] The lead frame is provided with a first carrier area, a second carrier area and a third carrier area, the second carrier area is connected with the third carrier area, and the first carrier area is arranged in a spaced manner with the third carrier area.

[0007] The first chip is flip-chip connected to the first carrier area, the second chip is flip-chip connected to the second carrier area, and the third chip is flip-chip connected to the third carrier area; and

[0008] The conductive metal layer is formed on the first chip, the second chip and the third chip.

[0009] Optionally, the first die region comprises a first die island and a driving pin group, the driving pin group is located at the outer periphery of the first die island and extends to the outside of the lead frame, and comprises a first driving pin, a second driving pin and a third driving pin.

[0010] The first driving pin is connected to the first die island, the second driving pin and the third driving pin are both arranged to be spaced apart from the first die island, and the second driving pin is connected to the second die region.

[0011] Optionally, the first chip is a driving chip, a surface of the first chip close to one side of the first die region comprises a first type of driving pin pad and a second type of driving pin pad, the first type of driving pin pad is connected to the first die island, the second type of driving pin pad is respectively connected to the second driving pin and the third driving pin, and the second type of driving pin pad is arranged to be misaligned with the first die island.

[0012] Optionally, the second die region comprises a second die island and an upper tube pin group, the second die island is connected to the third die region, the upper tube pin group is located at the outer periphery of the second die island and extends to the outside of the lead frame, and comprises a first upper tube pin, a second upper tube pin and a first lead pin.

[0013] The first upper tube pin, the second upper tube pin and the first lead pin are all arranged to be spaced apart from the second die island, and the first upper tube pin is connected to the first die region.

[0014] Optionally, the second chip is a MOSFET chip, a surface of the second chip close to one side of the second die region comprises a gate pad and a source pad, the source pad of the second chip is connected to the second die island, the gate pad of the second chip is respectively connected to the first upper tube pin and the second upper tube pin, and the gate pad of the second chip is arranged to be misaligned with the second die island.

[0015] Optionally, a surface of the second chip away from one side of the second die region comprises a drain pad, the conductive metal layer comprises a first metal layer, and the first metal layer covers the drain pad of the second chip and the first lead pin.

[0016] Optionally, the third die region comprises a third die island and a lower tube pin group, the third die island is connected with the second die region, and the lower tube pin group is located at the outer periphery of the third die island and extends to the outside of the lead frame, and comprises a first lower tube pin, a second lead pin and a third lead pin.

[0017] The first lower tube pin is connected to the third die island, and the second lead pin and the third lead pin are both arranged at intervals from the third die island.

[0018] Optionally, the third chip is a MOSFET chip, and the surface of the third chip close to one side of the third die region comprises a drain pad, the drain pad of the third chip is welded to the third die island, and is arranged at a position different from the second lead pin and the third lead pin.

[0019] Optionally, the surface of the third chip away from one side of the third die region comprises a source pad and a gate pad, and the conductive metal layer comprises a second metal layer and a third metal layer.

[0020] The second metal layer covers the source pad of the third chip, the second lead pin and at least part of the first chip, and the third metal layer covers the gate pad of the third chip and the third lead pin.

[0021] Optionally, the lead frame has a first direction and a second direction perpendicular to each other, the first die region and the second die region are sequentially distributed along the first direction and are located on the same side of the third die region along the second direction.

[0022] As described above, the semiconductor packaging structure provided by the application has at least the following beneficial effects:

[0023] In the semiconductor packaging structure, the first chip and the second chip are flip-chip mounted on the lead frame, and the third chip is right-angle mounted on the lead frame, the interconnection between the first chip, the second chip and the third chip and the leading-out of functional pins are realized by using the specially designed lead frame and the conductive metal layer, the semiconductor packaging structure without lead is realized, the problems of large lead resistance and loop inductance caused by the lead are effectively avoided, the inductance and resistance of the device are reduced, and the performance of the device is improved; and the plastic encapsulation layer on the surface of the device can be thinned to the surface of the conductive metal layer, the heat dissipation effect is improved, the thermal resistance is reduced, and the service life of the device is prolonged. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation to the scope. For those of ordinary skill in the art, other related drawings can also be obtained without creative effort based on these drawings.

[0025] Figure 1 A structural schematic diagram of a semiconductor package structure provided by the embodiments of the present application is shown.

[0026] Figure 2 A structural schematic diagram of the structure after the first chip, the second chip and the third chip are mounted to the lead frame provided by the embodiments of the present application is shown.

[0027] Figure 3 A structural schematic diagram of the lead frame provided by the embodiments of the present application is shown.

[0028] Figures 4 to 6 Structural schematic diagrams of the first to third chips provided by the embodiments of the present application are shown respectively.

[0029] Figure 7 A structural schematic diagram of the plastic sealing layer provided by the embodiments of the present application is shown.

[0030] Figure 8 A structural schematic diagram of the plastic sealing layer with an opening provided by the optional embodiments in the embodiments of the present application is shown.

[0031] Figure 9 A structural schematic diagram of the structure after the plastic sealing layer is thinned provided by the optional embodiments in the embodiments of the present application is shown.

[0032] Schematic diagram of the reference signs:

[0033] 10, lead frame; 11, first die region; 111, first die island; 112, set of drive pins; 1121, first drive pin; 1122, second drive pin; 1123, third drive pin; 113, first tie; 12, second die region; 121, second die island; 122, set of upper tube pins; 1221, first upper tube pin; 1222, second upper tube pin; 1224, first lead pin; 123, second tie; 13, third die region; 131, third die island; 132, set of lower tube pins; 1321, first lower tube pin; 1322, second lead pin; 1323, third lead pin; 21, first chip; 211, first type of drive pin pad; 212, second type of drive pin pad; 22, second chip; 221, source pad of second chip; 222, gate pad of second chip; 23, third chip; 231, source pad of third chip; 232, gate pad of third chip; 30, conductive metal layer; 31, first metal layer; 32, second metal layer; 33, third metal layer; 40, plastic encapsulation layer; 41, opening. DETAILED DESCRIPTION

[0034] In order to make the technical purposes, technical solutions and technical effects of the present application clearer, the technical solutions in the present application will be described clearly and completely in combination with embodiments below. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0035] Therefore, the detailed description of the embodiments of the present application below is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application. In addition, the terms “first”, “second” are only for descriptive purposes, and cannot be understood as indicating or implying relative importance.

[0036] In the description of the present application, it should be noted that the orientations or positional relationships indicated by the terms “center”, “longitudinal”, “lateral”, “upper”, “lower”, “front”, “rear”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer” and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0037] In the description of the application, it should be noted that unless otherwise explicitly defined and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection. In addition, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the application. In the description, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0038] The embodiment provides a semiconductor packaging structure for reducing or avoiding the generation of lead resistance and loop inductance caused by leads in a semiconductor device. Referring to Figure 1 The semiconductor packaging structure of the embodiment includes a lead frame 10, a first chip 21, a second chip 22, a third chip 23 and a conductive metal layer 30.

[0039] Referring to Figure 1 and Figure 2 The lead frame 10 is provided with a first carrier area 11, a second carrier area 12 and a third carrier area 13 for placing the first chip 21, the second chip 22 and the third chip 23 respectively. The first carrier area 11 is spaced apart from the third carrier area 13, and the second carrier area 12 is connected to the third carrier area 13. Optionally, the pins of the first carrier area 11 and the pins of the second carrier area 12 can be interconnected to connect the first carrier area 11 and the second carrier area 12. The first chip 21 is flip-chip connected to the first carrier area 11, the second chip 22 is flip-chip connected to the second carrier area 12, the third chip 23 is flip-chip connected to the third carrier area 13, and the conductive metal layer 30 is formed on the first chip 21, the second chip 22 and the third chip 23.

[0040] In an optional embodiment, the first chip 21 is a drive chip (Drive IC), the second chip 22 is an upper MOSFET chip (HSMOS), and the third chip 23 is a lower MOSFET chip (LSMOS). By mounting the first chip 21 and the second chip 22 on the lead frame 10 in a flip-chip manner and mounting the third chip 23 on the lead frame 10 in a face-down manner, the first chip 21, the second chip 22, and the third chip 23 can be interconnected through the lead frame 10 and the conductive metal layer 30, respectively, and the functional pin pads thereof can be led out through the pins in the lead frame 10, realizing a leadless semiconductor packaging structure, effectively avoiding the problem of high lead resistance and loop inductance caused by thin leads, reducing the inductance and resistance of the device, and improving the performance of the device.

[0041] In an optional embodiment, the lead frame 10 has a first direction and a second direction, the first direction and the second direction are perpendicular to each other, the first die region 11 and the second die region 12 are arranged along the first direction in sequence, and the first die region 11 and the second die region 12 are located on the same side of the third die region 13 along the second direction.

[0042] Referring to Figure 3 The first die region 11 includes a first die island 111 and a drive pin group 112, the first die island 111 is a placement region of the first chip 21, the drive pin group 112 is located at the outer periphery of the first die island 111, the drive pin group 112 can also extend to the outside of the lead frame 10, and is used to lead out the functional pins of the first chip 21. The drive pin group 112 includes a plurality of drive pins, and the plurality of drive pins are arranged at intervals from each other. Optionally, the drive pin group 112 is located at the outer periphery of the first die island 111 and at the edge region of the lead frame 10. Further, a first connecting rib 113 can also be arranged in the first die region 11 to support the lead frame.

[0043] In an optional embodiment, the drive pin group 112 includes a first drive pin 1121, a second drive pin 1122, and a third drive pin 1123. The first drive pin 1121 is connected with the first die island 111, and the number of the first drive pin 1121 can be one or more. Optionally, the first drive pin 1121 extends to contact the first die island 111, so that the first drive pin 1121 is connected with the first die island 111. The drive pin group 112 includes a plurality of first drive pins 1121, for example, the number of the first drive pin 1121 is two or other appropriate number, and the plurality of first drive pins 1121 are arranged at intervals from each other at the outer periphery of the first die island 111.

[0044] The second driving pin 1122 and the third driving pin 1123 are both arranged apart from the first carrier island 111, and the second driving pin 1122 is connected to the second carrier region 12. The number of the second driving pin 1122 and the third driving pin 1123 can be one or more. Optionally, the second driving pin 1122 is in a side-lying T-shaped structure, one end of which extends to the outside of the lead frame 10, and the other end of which extends to contact the second carrier region 12. The number of the third driving pin 1123 can be six, eight, eleven or other suitable numbers. The plurality of third driving pins 1123 are arranged apart from each other at the outer periphery of the first carrier island 111. The number of the second driving pin 1122 can be one.

[0045] With reference to Figure 2 and Figure 4 The first chip 21 is a driving chip. The first chip 21 is provided with a first type of driving pin pad 211 and a second type of driving pin pad 212 on the surface close to the side of the first carrier region 11. The number of the first type of driving pin pad 211 and the number of the second type of driving pin pad 212 can be one or more. Optionally, the number of the first type of driving pin pad 211 and the number of the second type of driving pin pad 212 are both plural, and the plurality of first type of driving pin pads 211 and the plurality of second type of driving pin pads 212 are arranged apart from each other. The first type of driving pin pad 211 and the second type of driving pin pad 212 are connected to various control ports corresponding to the first chip 21. Through the above-mentioned various types of driving pads, the first chip 21 can work normally to control the semiconductor packaging structure to work.

[0046] In an optional embodiment, the first type of driving pin pad 211 is connected to the first carrier island 111 and is arranged in a staggered manner with the second driving pin 1122 and the third driving pin 1123. The first driving pin 1121 is connected to the first carrier island 111. Through the first driving pin 1121, the first type of driving pin pad 211 can be led out. Optionally, the first type of driving pin pad 211 can be welded to the first carrier island 111 by solder, or can be connected to the first carrier island 111 by other suitable means.

[0047] In an optional embodiment, the second type of driving pin pad 212 is connected to the second driving pin 1122, the position of the second driving pin 1122 is matched with the position of the second type of driving pin pad 212, so that the second type of driving pin pad 212 can be connected with the second driving pin 1122 after the first chip 21 is installed, and is arranged in a staggered manner with the first carrier island 111, the first driving pin 1121 and the third driving pin 1123; the second type of driving pin pad 212 can be led out through the second driving pin 1122, and the second type of driving pin pad 212 is connected with the second chip 22. Optionally, the second type of driving pin pad 212 can be welded to the second driving pin 1122 by soldering, or can be connected to the second driving pin 1122 by other suitable means. In this embodiment, the staggered arrangement can be understood as that in the top view of the semiconductor package structure, there is no overlapping area between the outline areas of the two.

[0048] In an optional embodiment, the second type of driving pin pad 212 is also connected to the third driving pin 1123, the position of the third driving pin 1123 is matched with the position of the second type of driving pin pad 212, so that the second type of driving pin pad 212 can be connected with the third driving pin 1123, and is arranged in a staggered manner with the first carrier island 111, the first driving pin 1121 and the second driving pin 1122; the second type of driving pin pad 212 can be led out through the third driving pin 1123. Optionally, the second type of driving pin pad 212 can be welded to the third driving pin 1123 by soldering, or can be connected to the third driving pin 1123 by other suitable means.

[0049] Referring to Figure 3 The second carrier area 12 includes a second carrier island 121 and an upper tube pin group 122, the second carrier island 121 is a placement area of the second chip 22, the upper tube pin group 122 is located at the outer periphery of the second carrier island 121, the upper tube pin can also extend to the outside of the lead frame 10, and is used for leading out the electrode of the second chip 22. The upper tube pin group 122 has a plurality of upper tube pins, and the upper tube pin group 122 is located at the outer periphery of the second carrier island 121 and at the edge area of the lead frame 10, and the plurality of upper tube pins are arranged in a spaced manner. Further, the second carrier area 12 can also be provided with a second connecting rib 123 for supporting the lead frame.

[0050] In an optional embodiment, the upper tube pin group 122 includes a first upper tube pin 1221, a second upper tube pin 1222, and a first lead pin 1224. The first upper tube pin 1221, the second upper tube pin 1222, and the first lead pin 1224 are all arranged in a spaced manner with the second carrier island 121, and the first upper tube pin 1221 is connected with the first carrier region 11; optionally, the first upper tube pin 1221 has a convex portion near one side of the first carrier region 11, and the convex portion extends to contact the first carrier region 11; further, the first upper tube pin 1221 is connected with the second driving pin 1122. The number of the first upper tube pin 1221, the second upper tube pin 1222, and the first lead pin 1224 can be one or more; optionally, the number of the first upper tube pin 1221 is one, for example, and the number of the second upper tube pin 1222 and the first lead pin 1224 is three, for example; wherein the plurality of second upper tube pins 1222 are arranged in a spaced manner, and the plurality of first lead pins 1224 are interconnected.

[0051] With reference to Figure 2 and Figure 5 , the second chip 22 is a MOSFET chip, and the surface of the second chip 22 near one side of the second carrier region 12 has a source pad and a gate pad. The source pad 221 of the second chip is electrically connected with the source electrode of the second chip 22, and the gate pad 222 of the second chip is electrically connected with the gate electrode of the second chip 22. The number of the source pad 221 of the second chip and the number of the gate pad 222 of the second chip can both be one or more and arranged in a spaced manner.

[0052] In an optional embodiment, the source pad 221 of the second chip is connected to the second carrier island 121 and arranged in a staggered manner with the first upper tube pin 1221, the second upper tube pin 1222, and the first lead pin 1224. Optionally, the source pad 221 of the second chip can be welded to the second carrier island 121 by solder or connected to the second carrier island 121 by other suitable means.

[0053] In an optional embodiment, the gate pad 222 of the second chip is connected to the first upper tube pin 1221, the position of the first upper tube pin 1221 is matched with the position of the gate pad 222 of the second chip, so that the gate pad 222 of the second chip is connected to the first upper tube pin 1221 and is arranged in a staggered manner with the second carrier island 121, the second upper tube pin 1222 and the first lead pin 1224; through the first upper tube pin 1221, the gate pad 222 of the second chip is led out, and the second chip 22 is connected to the first chip 21 through the first upper tube pin 1221. Optionally, the gate pad 222 of the second chip can be soldered to the first upper tube pin 1221 by solder, or can be connected to the first upper tube pin 1221 by other suitable means.

[0054] In an optional embodiment, the gate pad 222 of the second chip is also connected to the second upper tube pin 1222, the position of the second upper tube pin 1222 is matched with the position of the gate pad 222 of the second chip, so that the gate pad 222 of the second chip is connected to the second upper tube pin 1222 and is arranged in a staggered manner with the second carrier island 121, the second upper tube pin 1222 and the first lead pin 1224; through the second upper tube pin 1222, the gate pad 222 of the second chip is led out, and the second chip 22 is connected to the first chip 21 through the second upper tube pin 1222. Optionally, the gate pad 222 of the second chip can be soldered to the second upper tube pin 1222 by solder, or can be connected to the second upper tube pin 1222 by other suitable means.

[0055] In an optional embodiment, referring to Figure 1 , the second chip 22 is a MOSFET chip, the surface of the second chip 22 away from the second carrier region 12 side has a drain pad, the drain pad of the second chip is electrically connected with the drain electrode of the second chip, and the conductive metal layer 30 includes a first metal layer 31, the first metal layer 31 covers the drain pad of the second chip and the first lead pin 1224. Optionally, the first metal layer 31 may, for example, be a copper clamp, which can be soldered on the drain pad of the second chip and the first lead pin 1224 by solder to realize the leading-out of the drain pad of the second chip.

[0056] Referring to Figure 3The third die region 13 includes a third die island 131 and a lower lead group 132. The third die island 131 is a placement region of the third chip 23 and is connected to the second die region 12. The lower lead group 132 is located at the outer periphery of the third die island 131 and can also extend to the outside of the lead frame 10 to realize the lead-out of the electrodes of the third chip 23. The lower lead group 132 includes a plurality of lower leads. Optionally, the lower lead group 132 is located at the outer periphery of the third die island 131 and at the edge region of the lead frame 10, and the plurality of lower leads are spaced apart from each other.

[0057] In an optional embodiment, the lower lead group 132 includes a first lower lead 1321, a second lead 1322, and a third lead 1323. The first lower lead 1321 is connected to the third die island 131. The number of the first lower lead 1321 can be one or a plurality of leads spaced apart from each other at the outer periphery of the third die island 131. Optionally, the number of the first lower lead 1321 is four, and the four first lower leads 1321 are respectively distributed at the four top corner positions of the third die island 131. The second lead 1322 and the third lead 1323 are spaced apart from the third die island 131. The number of the second lead 1322 and the third lead 1323 can be one or a plurality of leads. Optionally, the lower lead group 132 includes a plurality of second leads 1322, and the plurality of second leads 1322 are interconnected. The lower lead group 132 includes one first lead 1224.

[0058] Referring to Figure 2 The third chip 23 is a MOSFET chip. The surface of the third chip 23 close to the third die region 13 has a drain pad. The drain pad of the third chip is electrically connected to the drain electrode of the third chip. The drain pad of the third chip is connected to the third die island 131 and is arranged in a staggered manner with the second lead 1322 and the third lead 1323. The first lower lead 1321 is connected to the third die island 131, and the drain pad of the third chip can be led out through the first lower lead 1321. Optionally, the drain pad of the third chip can be soldered to the third die island 131 or connected to the third die island 131 by other suitable methods.

[0059] Referring to Figure 2 and Figure 6 The third chip 23 is a MOSFET chip. The surface of the third chip 23 away from the third die region 13 has a source pad and a gate pad. The source pad 231 of the third chip is electrically connected to the source electrode of the third chip 23, and the gate pad 232 of the third chip is electrically connected to the gate electrode of the third chip 23. Referring to Figure 1The conductive metal layer 30 further comprises a second metal layer 32 and a third metal layer 33, and the second metal layer 32 and the third metal layer 33 are both copper clamps. The second metal layer 32 covers the source pad 231 of the third chip, the second lead pin 1322, and at least part of the first chip 21, thereby realizing the interconnection between the first chip 21 and the third chip 23, and realizing the lead-out of the source pad 231 of the third chip and the drain pad of the first chip through the second lead pin 1322. The third metal layer 33 covers the gate pad 232 of the third chip and the third lead pin 1323, thereby realizing the lead-out of the gate pad 232 of the third chip. Optionally, the first chip 21 is a driving chip, and the first chip 21 has a third type of driving lead pin pad on the side away from the first carrier area 11, and the second metal layer 32 further covers the third type of driving lead pin pad.

[0060] In the embodiment, referring to Figure 7 , the semiconductor packaging structure further comprises a plastic encapsulation layer 40, which covers the lead frame 10, the first chip 21, the second chip 22, the third chip 23, and the conductive metal layer 30, so as to protect the internal structure of the device. Optionally, referring to Figure 8 and Figure 9 , the plastic encapsulation layer 40 covers part of the conductive metal layer 30, and the plastic encapsulation layer 40 is provided with an opening 41 exposing part of the conductive metal layer 30. The exposed conductive metal layer 30 helps to improve the heat dissipation performance of the semiconductor packaging structure and reduce the thermal resistance of the device. Further, the semiconductor packaging structure is thinned so that the surface of the plastic encapsulation layer 40 away from the lead frame body is flush with the top surface of the conductive metal layer 30 away from the lead frame body, further optimizing the heat dissipation effect of the semiconductor packaging structure and improving the performance of the device.

[0061] As described above, in the semiconductor packaging structure of the embodiment, the first chip 21 and the second chip 22 are flip-chip mounted on the lead frame 10, and the third chip 23 is face-down mounted on the lead frame 10. Through the specially designed lead frame 10 and the conductive metal layer 30, the first chip 21, the second chip 22, and the third chip 23 are interconnected, and the functional lead pin pads of each chip can be led out from the lead pin of the lead frame 10, realizing a leadless semiconductor packaging structure, effectively avoiding the problems of large lead resistance and loop inductance caused by the lead, reducing the inductance and resistance of the device, and improving the performance of the device. Moreover, the plastic encapsulation layer 40 on the surface of the device can be thinned to the surface of the conductive metal layer 30, improving the heat dissipation effect, reducing the thermal resistance, and further improving the performance of the device.

[0062] The above embodiments are only illustrative of the principles of the present application and its effects, and are not intended to limit the present application. Any modification, change or combination of the above embodiments made by those skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A semiconductor packaging structure, characterized in that, It includes a lead frame, a first chip, a second chip, a third chip, and a conductive metal layer; The lead frame is provided with a first substrate area, a second substrate area and a third substrate area, the second substrate area is connected to the third substrate area, and the first substrate area and the third substrate area are spaced apart; The first chip is flip-chip connected to the first wafer carrier area, the second chip is flip-chip connected to the second wafer carrier area, and the third chip is upright-mounted connected to the third wafer carrier area; and The conductive metal layer is formed on the first chip, the second chip, and the third chip.

2. The semiconductor packaging structure according to claim 1, characterized in that, The first wafer carrier region includes a first wafer carrier island and a drive pin group. The drive pin group is located on the outer periphery of the first wafer carrier island and extends to the outside of the lead frame, and includes a first drive pin, a second drive pin, and a third drive pin. The first drive pin is connected to the first wafer island, the second drive pin and the third drive pin are both spaced apart from the first wafer island, and the second drive pin is connected to the second wafer area.

3. The semiconductor packaging structure according to claim 2, characterized in that, The first chip is a driver chip. The surface of the first chip near the first substrate area includes a first type of driver pin pad and a second type of driver pin pad. The first type of driver pin pad is connected to the first substrate island. The second type of driver pin pad is connected to the second driver pin and the third driver pin, respectively. Furthermore, the second type of driver pin pad is staggered from the first substrate island.

4. The semiconductor packaging structure according to claim 1, characterized in that, The second wafer carrier region includes a second wafer carrier island and an upper tube pin group. The second wafer carrier island is connected to the third wafer carrier region. The upper tube pin group is located on the outer periphery of the second wafer carrier island and extends to the outside of the lead frame, including a first upper tube pin, a second upper tube pin, and a first lead pin. The first upper transistor pin, the second upper transistor pin, and the first lead pin are all spaced apart from the second wafer island, and the first upper transistor pin is connected to the first wafer area.

5. The semiconductor packaging structure according to claim 4, characterized in that, The second chip is a MOSFET chip. The surface of the second chip near the second substrate area includes a gate pad and a source pad. The source pad of the second chip is connected to the second substrate island. The gate pad of the second chip is connected to the first upper MOSFET pin and the second upper MOSFET pin, respectively. Furthermore, the gate pad of the second chip is staggered from the second substrate island.

6. The semiconductor packaging structure according to claim 4, characterized in that, The surface of the second chip away from the second substrate area includes a drain pad, and the conductive metal layer includes a first metal layer that covers the drain pad and the first lead of the second chip.

7. The semiconductor packaging structure according to claim 1, characterized in that, The third wafer carrier region includes a third wafer carrier island and a lower diode pin group. The third wafer carrier island is connected to the second wafer carrier region. The lower diode pin group is located on the outer periphery of the third wafer carrier island and extends to the outside of the lead frame, including a first lower diode pin, a second lead pin, and a third lead pin. The first lower tube pin is connected to the third wafer island, and the second lead and the third lead are both spaced apart from the third wafer island.

8. The semiconductor packaging structure according to claim 7, characterized in that, The third chip is a MOSFET chip. The surface of the third chip near the third substrate area includes a drain pad. The drain pad of the third chip is connected to the third substrate island and is staggered with the second lead and the third lead.

9. The semiconductor packaging structure according to claim 7, characterized in that, The surface of the third chip on the side away from the third substrate region includes source pads and gate pads, and the conductive metal layer includes a second metal layer and a third metal layer. The second metal layer covers the source pad of the third chip, the second lead, and at least a portion of the first chip, and the third metal layer covers the gate pad and the third lead of the third chip.

10. The semiconductor packaging structure according to claim 1, characterized in that, The lead frame has a first direction and a second direction that are perpendicular to each other. The first substrate area and the second substrate area are arranged sequentially along the first direction and are located on the same side of the third substrate area along the second direction.

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