Packaging substrate and semiconductor packaging structure

Abstract

The utility model discloses a packaging substrate and a semiconductor packaging structure, the packaging substrate comprises at least two stacked substrates, each substrate comprises a glass core plate, one or more conductive through holes, a first rewiring structure and a second rewiring structure, the glass core plate is provided with a first surface and a second surface which are opposite to each other, and the first surface and the second surface are opposite to each other. The one or more conductive through holes penetrate through the glass core plate, the first rewiring structure is located on the first surface of the glass core plate and electrically connected with the conductive through holes, and the second rewiring structure is located on the second surface of the glass core plate and electrically connected with the conductive through holes; the one or more interconnection conductive columns are arranged between the two adjacent substrates and separate the two adjacent substrates so as to form an air dielectric layer between the two adjacent substrates; the interconnection conductive column is electrically connected with the first redistribution structure and the second redistribution structure which are located on the two sides of the interconnection conductive column and on the substrate. In this way, more chips can be packaged, the overall cost and power consumption are lower, and buckling deformation caused by thermal stress is effectively reduced.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a packaging substrate and a semiconductor packaging structure. Background Technology

[0002] With the rapid development of high-tech fields, especially the high-speed advancement of artificial intelligence (AI), processor chip package sizes are becoming increasingly larger, and the warpage of large-size FCBGA packaging substrates is facing a bottleneck. Glass substrates can overcome the warpage problem of organic substrates in large-size AI chip packaging, strengthening the structure of GPU processors and achieving better electrical and mechanical reliability. Glass substrates can be used to replace silicon and organic interposers. Interposers are generally made of silicon (COWOS-S), organic materials (COWOS-R), or a combination of silicon and organic materials (COWOS-L). Glass substrates directly utilize glass interposers to achieve interconnections between chips and between chips and external components. By leveraging the advantages of glass—low cost, good electrical performance, and low warpage—the defects of organic and silicon materials can be overcome, resulting in more stable and efficient connections and reduced production costs.

[0003] In related technologies, the packaging structure constructed by multiple stacked substrates can further reduce the possibility of warpage, but its thermal stress is high, which is not conducive to maintaining the temperature stability of the packaging substrate. Utility Model Content

[0004] This invention aims to at least partially solve one of the technical problems in the aforementioned technologies. Therefore, the purpose of this invention is to provide a packaging substrate and semiconductor packaging structure that interconnects and packages a multilayer glass substrate, allowing for the packaging of more chips in a smaller footprint, resulting in lower overall cost and power consumption. Furthermore, it reduces thermal stress, effectively minimizing warping caused by thermal stress and improving electrical performance.

[0005] To achieve the above objectives, this utility model provides a packaging substrate, comprising:

[0006] At least two stacked substrates, each substrate including a glass core plate, one or more conductive vias, a first rewiring structure and a second rewiring structure, the glass core plate having opposing first and second surfaces, one or more conductive vias penetrating the glass core plate, the first rewiring structure being located on the first surface of the glass core plate and electrically connected to the conductive vias, and the second rewiring structure being located on the second surface of the glass core plate and electrically connected to the conductive vias;

[0007] One or more interconnect conductive pillars are disposed between two adjacent substrates and spaced apart to form an air dielectric layer between the two adjacent substrates; the interconnect conductive pillars are electrically connected to a first rewiring structure and a second rewiring structure located on substrates on both sides thereof.

[0008] According to this utility model, a packaging substrate using at least two stacked substrates reduces the possibility of warpage. By using air as a dielectric layer between adjacent stacked substrates, the overall thermal expansion coefficient of the packaging substrate is reduced, effectively minimizing warpage caused by thermal stress and preventing excessive heat accumulation within the substrate, thus helping to maintain temperature stability. Furthermore, the air dielectric layer improves the insulation performance of the packaging substrate, reducing the risk of short circuits and enhancing its reliability and stability. It also reduces signal loss and delay during transmission, improving signal transmission speed and quality, and thus enhancing the electrical performance of the packaging substrate. Moreover, it simplifies the manufacturing process and reduces the weight of the packaging substrate. Interconnecting and packaging multilayer glass substrates allows for the packaging of more chips in a smaller footprint, resulting in lower overall cost and power consumption, significantly improving future data centers and AI products.

[0009] In addition, the packaging substrate proposed above according to this utility model may also have the following additional technical features:

[0010] Optionally, each of the substrates further includes a first solder resist layer and a second solder resist layer, wherein the first solder resist layer is disposed on the side of the first redistribution structure away from the glass core board, and the second solder resist layer is disposed on the side of the second redistribution structure away from the glass core board.

[0011] Furthermore, the first solder mask layer has one or more first conductive pillars electrically connected to the first rewiring structure, and the second solder mask layer has one or more second conductive pillars electrically connected to the second rewiring structure; the first conductive pillars and second conductive pillars on two adjacent substrates are connected one-to-one to form one or more interconnect conductive pillars.

[0012] Furthermore, both the first conductive post and the second conductive post are metal posts, and the first conductive posts and the second conductive posts on two adjacent substrates are connected by thermo-press bonding or laser ablation.

[0013] Furthermore, the metal pillar is an electroplated copper pillar.

[0014] Furthermore, the height of the first conductive post is 10μm-20μm; the height of the second conductive post is 10μm-20μm.

[0015] Furthermore, the thickness of the air dielectric layer is 20μm-40μm. Thus, the air dielectric layer effectively prevents corrosion of the electroplated copper pillars and the glass substrate, achieving high-precision, high-density interconnection of the packaging substrate.

[0016] Furthermore, both the first and second wiring structures include at least one metal wiring layer and at least one dielectric layer, wherein the material of the dielectric layer of the first wiring structure is the same as or different from the material of the dielectric layer of the second wiring structure.

[0017] To achieve the above objectives, a second aspect of this utility model provides a semiconductor packaging structure, comprising:

[0018] chip;

[0019] As described above, the chip is disposed on the packaging substrate and electrically connected to the packaging substrate.

[0020] According to the semiconductor packaging structure of this utility model, the packaging substrate formed by interconnecting and packaging the above-mentioned multilayer glass substrates allows for packaging more chips in a smaller area; and the interconnecting and packaging of multilayer glass substrates can effectively solve the problem of warping of large-size FCBGA packaging substrates; furthermore, when interconnecting and packaging multilayer glass substrates, using air as the dielectric insulating layer between adjacent substrates can better solve the problems of thermal stress and heat dissipation. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the packaging substrate according to an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the process for manufacturing a glass core board according to an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram illustrating the process of fabricating each substrate according to an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram illustrating the process of fabricating each substrate according to an embodiment of the present invention;

[0025] Label Explanation:

[0026] Substrate 100, glass core board 110, first surface 110a, second surface 110b, conductive via 120, first rewiring structure 130, second rewiring structure 140, first solder resist layer 150, second solder resist layer 160.

[0027] Interconnecting conductive post 200, first conductive post 210, second conductive post 220;

[0028] Air medium layer 300. Detailed Implementation

[0029] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.

[0030] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0031] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a packaging substrate provided in an embodiment of the present invention. The packaging substrate includes at least two stacked substrates 100. Each substrate 100 includes a glass core plate 110, one or more conductive vias 120, a first rewiring structure 130, and a second rewiring structure 140. The glass core plate 110 has opposing first surfaces 110a and second surfaces 110b. One or more conductive vias 120 penetrate the glass core plate 110. The first rewiring structure 130 is located on the first surface 110a of the glass core plate 110 and is electrically connected to the conductive vias 120. The second rewiring structure 140 is located on the second surface 110b of the glass core plate 110 and is electrically connected to the conductive vias 120. Understandably, each substrate 100 uses a glass core plate 110 as a support. A first rewiring structure 130 and a second rewiring structure 140 are respectively fabricated on the upper surface (i.e., the first surface 110a) and lower surface (i.e., the second surface 110b) of the glass core plate 110. The glass core plate 110 interconnects the first rewiring structure 130 and the second rewiring structure 140 by fabricating TGV holes penetrating the upper and lower surfaces and metallizing the TGV holes to form conductive vias 120. The stacked substrates 100 are not limited to... Figure 1 The two in the middle can be stacked and interconnected using multilayer substrates 100 as needed.

[0032] The packaging substrate also includes one or more interconnect conductive pillars 200, disposed between two adjacent substrates 100 and spaced apart to form an air dielectric layer 300 between the two adjacent substrates 100; the interconnect conductive pillars 200 are electrically connected to a first rewiring structure 130 and a second rewiring structure 140 located on the substrates 100 on both sides thereof. That is, when multiple substrates 100 are stacked, two adjacent substrates 100 are interconnected through the connection of the interconnect conductive pillars 200, and the interconnect conductive pillars 200 have a certain height so that a gap is left between the two adjacent substrates 100 to form an air dielectric layer 300.

[0033] Therefore, the packaging substrate provided according to the embodiments of this utility model, by using at least two stacked substrates 100, can reduce the possibility of warpage. By using air as a dielectric layer between adjacent stacked substrates 100, the overall thermal expansion coefficient of the packaging substrate can be reduced, more effectively reducing warpage caused by thermal stress, and preventing excessive heat accumulation inside the substrate 100, which is beneficial for maintaining the temperature stability of the packaging substrate. Furthermore, the air dielectric layer 300 can improve the insulation performance of the packaging substrate, reduce the risk of short circuits in the substrate 100, and improve the reliability and stability of the packaging substrate. It can also reduce signal loss and delay during transmission, improve signal transmission speed and quality, and improve the electrical performance of the packaging substrate. Moreover, it can simplify the process and reduce the weight of the packaging substrate. Interconnecting and packaging multilayer glass substrates allows for packaging more chips in a smaller footprint, resulting in lower overall cost and power consumption, significantly improving future data centers and AI products.

[0034] As an example, such as Figure 1 As shown, each substrate 100 further includes a first solder resist layer 150 and a second solder resist layer 160. The first solder resist layer 150 is disposed on the side of the first redistribution structure 130 away from the glass core board 110, and the second solder resist layer 160 is disposed on the side of the second redistribution structure 140 away from the glass core board 110. Thus, the outer surface of the redistribution structure is protected by the solder resist layers.

[0035] More specifically, the first solder mask layer 150 has one or more first conductive pillars 210 electrically connected to the first rewiring structure 130, and the second solder mask layer 160 has one or more second conductive pillars 220 electrically connected to the second rewiring structure 140; the first conductive pillars 210 and second conductive pillars 220 on two adjacent substrates 100 are connected one-to-one to form one or more interconnect conductive pillars 200. That is, for each substrate 100, first conductive pillars 210 are first fabricated on its first solder mask layer 150, and second conductive pillars 220 are fabricated on its second solder mask layer 160. Then, the opposing first conductive pillars 210 and second conductive pillars 220 on two adjacent substrates 100 are connected and stacked. After the first conductive pillars 210 and second conductive pillars 220 are connected to form interconnect conductive pillars 200, the interconnection between the two adjacent substrates 100 is realized. The number of first conductive pillars 210 and the number of second conductive pillars 220 are the same and are one-to-one.

[0036] Furthermore, both the first conductive pillar 210 and the second conductive pillar 220 are metal pillars, and the first conductive pillar 210 and the second conductive pillar 220 on two adjacent substrates 100 are connected by thermocompression bonding or laser melting. That is, after forming the first solder resist layer 150 and the second solder resist layer 160 on each substrate 100, metal pillars can be directly fabricated on the first solder resist layer 150 and the second solder resist layer 160. Then, when the substrates 100 are stacked, the opposing metal pillars on two adjacent substrates 100 are connected into one piece by thermocompression bonding or laser melting to form interconnecting conductive pillars 200.

[0037] More specifically, the metal pillar is an electroplated copper pillar. That is to say, the electroplated copper pillar technique can be used to fabricate metal pillars on the first solder mask layer 150 and the second solder mask layer 160, which serve as the first conductive pillar 210 and the second conductive pillar 220, respectively.

[0038] The height of the first conductive post 210 can be 10μm-20μm; the height of the second conductive post 220 can be 10μm-20μm. More specifically, the height of each first conductive post 210 is the same, the height of each second conductive post 220 is the same, and the heights of the first conductive post 210 and the second conductive post 220 can be the same or different.

[0039] Furthermore, the thickness of the air dielectric layer 300 is 20μm-40μm. Thus, the air dielectric layer 300 can effectively prevent corrosion of the electroplated copper pillars and glass substrate, achieving high-precision and high-density interconnection of the packaging substrate; the air dielectric layer 300 is formed after the two substrates 100 are stacked by connecting the first conductive pillar 210 and the second conductive pillar 220 to form interconnect conductive pillars 200, and the gap between the two substrates 100 is excluding the interconnect conductive pillars 200.

[0040] As an example, both the first wiring structure 130 and the second wiring structure 140 include at least one metal wiring layer and at least one dielectric layer. The number of metal wiring layers and dielectric layers in the first wiring structure 130 and the second wiring structure 140 can be designed according to actual needs, for example... Figure 1 Both the first wiring structure 130 and the second wiring structure 140 include three metal wiring layers and three dielectric layers, but the number of layers is not limited to this. The material of the dielectric layer of the first wiring structure 130 and the material of the dielectric layer of the second wiring structure 140 can be the same or different. For example, the dielectric layer of both the first wiring structure 130 and the second wiring structure 140 can be ABF layers.

[0041] The following is an example illustrating the fabrication process of the aforementioned packaging substrate:

[0042] First, refer to Figure 2 First, a glass core plate 110 is fabricated. Specifically, a glass plate is prepared as the core plate material to provide a glass core plate 110 after surface polishing and cleaning. The glass core plate 110 mainly serves a supporting and connecting function and can be made of materials such as quartz or borosilicate glass. The glass core plate 110 has a first surface 110a and a second surface 110b. As an example, the thickness of the glass core plate 110 is 50μm to 1mm.

[0043] Based on the aforementioned glass core plate 110, TGV holes are fabricated using methods such as plasma etching, laser ablation, laser-induced etching, and focused discharge. The TGV holes penetrate the glass core plate 110.

[0044] Based on the glass core plate 110 with TGV holes formed above, a seed copper layer is deposited inside the TGV holes and on the surface of the glass core plate 110 by means such as physical vapor deposition (PVD) or chemical vapor deposition (PTH).

[0045] Based on the glass core board 110 described above, the holes are filled by methods such as electroplating or metal conductive adhesive.

[0046] Based on the aforementioned glass core board 110, the seed copper layer and the over-plated copper layer are etched away by means such as excimer laser etching or plasma etching to form conductive vias 120 on the glass core board 110.

[0047] Subsequently, based on the glass core board 110 with the conductive via 120 formed above, the inner layer circuitry on the glass core board 110 is fabricated by, for example, pattern transfer (dry film application → exposure → development → etching → film removal), and the inner layer circuitry is electrically connected to the conductive via 120.

[0048] Next, refer to Figure 3Based on the glass core board 110 with the inner layer circuitry formed above, fine circuitry layers (and add-on layers) on the top surface (first surface 110a) and bottom surface (first surface 110b) of the glass core board 110 are fabricated by applying ABF film → laser drilling → Desmear + PTH → applying dry film → exposure → development → VCP → film removal → flash etching. The line width / spacing of the fine circuitry on the top surface can be 8 / 8μm to 10 / 10μm. In this way, a first rewiring structure 130 electrically connected to the inner layer circuitry can be formed on the inner layer circuitry of the first surface 110a of the glass core board 110, and a second rewiring structure 140 electrically connected to the inner layer circuitry can be formed on the inner layer circuitry of the second surface 110b of the glass core board 110.

[0049] Then, refer to Figure 4 Based on the glass core board 110 that forms the first wiring structure 130 and the second wiring structure 140 as described above, a solder resist layer and electroplated copper pillars are fabricated on the glass core board 110 through a process of green oil coating → green oil (exposure) → green oil (development) → photocuring + thermal curing → electroplating copper pillars / nickel / tin. The height of the electroplated copper pillars is 10μm-20μm. In this way, a first solder resist layer 150 and a first conductive pillar 210 are formed on the outer surface of the first wiring structure 130, and the first conductive pillar 210 is electrically connected to the metal wiring layer of the first wiring structure 130. A second solder resist layer 160 and a second conductive pillar 220 are formed on the outer surface of the second wiring structure 140, and the second conductive pillar 220 is electrically connected to the metal wiring layer of the second wiring structure 140. This completes the fabrication of each substrate 100.

[0050] Finally, multiple substrates 100 are stacked, and the first conductive pillar 210 and the second conductive pillar 220 on opposite sides of two adjacent substrates 100 are connected by thermo-press bonding (TCBThermo Compression Bonding) to form interconnect conductive pillars 200, thereby achieving high-precision, high-strength, and high-reliability interconnection between the bottom surface of the glass substrate and the copper-plated layer on the top surface of the glass substrate.

[0051] Furthermore, embodiments of this utility model also propose a semiconductor packaging structure, including a chip and the aforementioned packaging substrate. The chip can be packaged on the packaging substrate according to the needs of different products. Existing technologies for chip packaging on the packaging substrate will not be described in detail here.

[0052] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0053] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0054] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0055] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0056] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0057] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A packaging substrate, characterized in that, include: At least two stacked substrates, each substrate including a glass core plate, one or more conductive vias, a first rewiring structure and a second rewiring structure, the glass core plate having opposing first and second surfaces, one or more conductive vias penetrating the glass core plate, the first rewiring structure being located on the first surface of the glass core plate and electrically connected to the conductive vias, and the second rewiring structure being located on the second surface of the glass core plate and electrically connected to the conductive vias; One or more interconnect conductive pillars are disposed between two adjacent substrates and spaced apart to form an air dielectric layer between the two adjacent substrates; the interconnect conductive pillars are electrically connected to a first rewiring structure and a second rewiring structure located on substrates on both sides thereof.

2. The packaging substrate as described in claim 1, characterized in that, Each of the substrates further includes a first solder resist layer and a second solder resist layer, wherein the first solder resist layer is disposed on the side of the first redistribution structure away from the glass core board, and the second solder resist layer is disposed on the side of the second redistribution structure away from the glass core board.

3. The packaging substrate as described in claim 2, characterized in that, The first solder mask layer has one or more first conductive pillars electrically connected to the first rewiring structure, and the second solder mask layer has one or more second conductive pillars electrically connected to the second rewiring structure; The first and second conductive pillars on two adjacent substrates are connected in a one-to-one correspondence to form one or more of the interconnecting conductive pillars.

4. The packaging substrate as described in claim 3, characterized in that, Both the first conductive post and the second conductive post are metal posts, and the first conductive posts and the second conductive posts on two adjacent substrates are connected by thermo-press bonding or laser ablation.

5. The packaging substrate as described in claim 4, characterized in that, The metal pillar is an electroplated copper pillar.

6. The packaging substrate as described in claim 3, characterized in that, The height of the first conductive post is 10μm-20μm; the height of the second conductive post is 10μm-20μm.

7. The packaging substrate as described in claim 1, characterized in that, The thickness of the air medium layer is 20μm-40μm.

8. The packaging substrate as described in claim 1, characterized in that, Both the first and second wiring structures include at least one metal wiring layer and at least one dielectric layer. The dielectric layer of the first wiring structure may be made of the same or different material than the dielectric layer of the second wiring structure.

9. A semiconductor packaging structure, characterized in that, include: chip; The packaging substrate as described in any one of claims 1-8, wherein the chip is disposed on the packaging substrate and electrically connected to the packaging substrate.

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