Testing device with multi-type interfaces and multi-type equipment testing system
By using testing devices and systems with multiple interface types, the problem of high testing costs for SerDes products has been solved, enabling testing of devices with different interface specifications and reducing testing difficulty and costs.
Patent Information
- Application Number
- CN202423246951.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2034-12-25
AI Technical Summary
SerDes product testing costs are high, and existing solutions result in persistently high testing costs.
A test device with multiple interface types is provided, including a first circuit board and a serial integrated chip, which supports the testing of devices such as PCIe, SATA and XGMAC. The device connects to interfaces such as M.2, U.2, AIC and XGMAC through a second circuit board and multiple connectors, enabling the testing of devices with different interface specifications and reducing testing costs.
The elimination of the need to repurchase adaptation servers reduces the testing difficulty and cost of high-speed SerDes products, enabling testing of products with various interface types.
Smart Images
Figure CN223911241U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of hardware testing, and in particular to a test device with multiple types of interfaces and a multiple-type device test system. BACKGROUND
[0002] Various high-speed SerDes products account for an increasingly high proportion in server hardware systems. Limited by the test environment of SerDes products, a test service area needs to establish a working environment from a processor to a test unit, to an interface unit, and then to a hardware under test. With the development of AI, the demand for SerDes interface products is increasing dramatically, but the cost of servers is extremely high, resulting in high test costs of SerDes interface products. According to the procurement idea of purchasing servers corresponding to the interface form of products in the existing scheme, a very high SerDes product test cost will be caused. CONTENT OF THE UTILITY MODEL
[0003] The present application mainly provides a test device with multiple types of interfaces and a multiple-type device test system to solve the problem of high test cost of SerDes products.
[0004] To solve the above technical problems, one technical solution adopted by the present application is to provide a test device with multiple types of interfaces, comprising: a first circuit board, a serial integrated chip and a first high-speed connector arranged on the first circuit board, the serial integrated chip being in communication connection with the first high-speed connector; a second circuit board, a second high-speed connector and multiple types of connectors arranged on the second circuit board, the second high-speed connector being in communication connection with the multiple types of connectors through a serializer-deserializer protocol; the first high-speed connector and the second high-speed connector being in communication connection, and the multiple types of connectors including at least two of an M.2 connector, a U.2 connector, an AIC connector, a SATA connector or an XGMAC connector.
[0005] In some embodiments, the first high-speed connector and the second high-speed connector are both MCIO connectors or slimSAS connectors.
[0006] In some embodiments, the test device further comprises a memory, the serial integrated chip comprises a memory control module, and the memory is connected to the memory control module.
[0007] In some embodiments, the first circuit board further comprises a physical layer module and an RJ45 interface, a first end of the physical layer module being connected to an RGMII interface of the serial integrated chip, and a second end of the physical layer module being connected to the RJ45 interface.
[0008] In some embodiments, the test device further comprises a power seat, a first power management integrated circuit and a second power management integrated circuit; a first end of the first power management integrated circuit is connected to a first end of the power seat, a second end of the first power management integrated circuit is connected to the serial integrated chip, a second end of the power seat is connected to the first high-speed connector, a first end of the second power management integrated circuit is connected to the second high-speed connector, and a second end of the second power management integrated circuit is connected to the M.2 connector, the U.2 connector, the AIC connector, the SATA connector or the XGMAC connector.
[0009] In some embodiments, the second circuit board further comprises a temperature sensor connected to a third end of the second power management integrated circuit for collecting the temperature of the plurality of connectors.
[0010] In some embodiments, the test device further comprises a first fan connector, and the serial integrated chip further comprises a PWM module, the first fan connector is connected to the PWM module, and the first fan connector is further used to connect a fan for dissipating heat of the serial integrated chip.
[0011] In some embodiments, the second circuit board further comprises a second fan connector, the PWM module is further connected to the first high-speed connector, the second fan connector is connected to the second high-speed connector, and the second fan connector is further used to connect a fan for dissipating heat of the plurality of connectors.
[0012] In some embodiments, the test device further comprises a user indicator light, and the serial integrated chip further comprises a general input and output module, the user indicator light is connected to the general input and output module.
[0013] To solve the above problems, the application further provides another multi-type device test system, which comprises a host computer, a test device as described above and a plurality of devices to be tested, and the plurality of devices to be tested comprise at least two of the M.2 solid state disk, the U.2 solid state disk, the AIC solid state disk, the SATA disk or the XGMAC optical module.
[0014] The beneficial effects of this application are as follows: Unlike existing technologies, this application discloses a testing device and a multi-type device testing system with multiple interfaces. It utilizes a first circuit board and a serial integrated chip and a first high-speed connector mounted on the first circuit board. The serial integrated chip communicates with the first high-speed connector, issuing commands or information to control the testing process. The serial integrated chip supports testing of PCIe, SATA, and XGMAC devices. A second circuit board and a second high-speed connector and multiple connectors mounted on the second circuit board are also present. The second high-speed connector communicates with the multiple connectors via a serializer and deserializer protocol. The first and second high-speed connectors are also communicatively connected, enabling command or information transmission between the second and first circuit boards. The multiple connectors include at least two of M.2, U.2, AIC, SATA, or XGMAC connectors, allowing for the connection of devices with various interface specifications for testing. This eliminates the need to purchase compatible servers, reducing testing costs and enabling testing of various high-speed SerDes products, thus lowering the testing difficulty and cost. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:
[0016] Figure 1 This is a schematic diagram of the structure of an embodiment of the testing device with multiple types of interfaces provided in this application;
[0017] Figure 2 Is it like this? Figure 1 A schematic diagram of the structure of a test unit of the test apparatus shown in the figure;
[0018] Figure 3 Is it like this? Figure 1 A schematic diagram of another embodiment of the test unit of the test device shown;
[0019] Figure 4 Is it like this? Figure 1 A schematic diagram of another embodiment of the test apparatus shown;
[0020] Figure 5 Is it like this? Figure 1 A schematic diagram of another embodiment of the test apparatus shown;
[0021] Figure 6 Is it like this? Figure 1 A schematic diagram of another embodiment of the test apparatus shown;
[0022] Figure 7 is a structural schematic diagram of another embodiment of the test unit of the test device as shown in Figure 1
[0023] Figure 8 is a structural schematic diagram of an embodiment of the multi-type device test system provided by the present application. DETAILED DESCRIPTION
[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.
[0025] The terms “first”, “second”, “third” in the embodiments of the present application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by “first”, “second”, “third” can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of “a plurality of” is at least two, for example, two, three, etc., unless otherwise specifically limited. In addition, the terms “include” and “have” and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.
[0026] In this document, the term “embodiment” means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears in various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily independent or alternative to other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.
[0027] Referring to Figure 1 , Figure 1 is an embodiment of the test device provided by the present application with a multi-type interface. Figure 1 is a structural schematic diagram of an embodiment of the test device provided by the present application with a multi-type interface, which includes:
[0028] The test unit 100 includes a first circuit board 10, a serializer / deserializer system on chip (SerDes SOC) and a first high-speed connector 12 disposed on the first circuit board 10, and the serializer / deserializer system on chip 11 is in communication connection with the first high-speed connector 12.
[0029] The interface unit 200 includes a second circuit board 20, a second high-speed connector 21 and a multi-type connector 22 disposed on the second circuit board 20, the second high-speed connector 21 is in communication connection with the multi-type connector 22 through a serializer / deserializer protocol, and the first high-speed connector 12 and the second high-speed connector 21 are in communication connection, and the multi-type connector 22 includes at least two of an M.2 connector, a U.2 connector, an AIC connector, a SATA connector or an XGMAC connector.
[0030] The serializer / deserializer system on chip 11 supports testing of devices of types such as PCIe, SATA and XGMAC, the serializer / deserializer system on chip 11 is connected with the first high-speed connector 12, the first high-speed connector 12 is connected with the second high-speed connector 21 through a connection line, and the second high-speed connector 21 is connected with the multi-type connector 22, so that the serializer / deserializer system on chip 11 can perform testing on external cards connected with each connector.
[0031] Among them, the first circuit board 10 and the second circuit board 20 are in transmission of multiple serDes protocols through the first high-speed connector 12 and the second high-speed connector 21, including PCIe, SATA and XGMAC, etc.
[0032] The multi-type connector 22 is used to connect external cards of corresponding interface types for testing of functions and performance of the external cards, specifically, the M.2 connector is used to connect an M.2 solid state disk for testing, the U.2 connector is used to connect a U.2 solid state disk for testing, the AIC connector is used to connect an AIC network card or a Raid card for testing, the SATA connector is used to connect a SATA hard disk for testing, and the XGMAC connector is used to connect an XGMAC optical module for testing.
[0033] The multi-type connector 22 is disposed on the second circuit board 20, compatible with M.2 interface, U.2 interface, AIC interface, SATA interface and XGMAC interface, etc., so that products of various interface types can be tested without the need to manufacture multiple test mainboards, thereby reducing the testing cost of multi-type interface products.
[0034] Optionally, the first high-speed connector 12 is a MCIO (Modular Connector Input Output) connector or a slimSAS (slim Serial Attached SCSI) connector, and the second high-speed connector 21 is a MCIO connector or a slimSAS connector correspondingly.
[0035] The MCIO connector adopts a modular design, facilitating assembly and maintenance. This design enables users to select or replace different modules according to actual needs, thereby improving flexibility and scalability. Meanwhile, the MCIO connector supports high-speed data transmission, which can meet the high requirements of modern electronic devices on data transmission rate and bandwidth. In addition, the MCIO connector adopts a compact layout design, which can provide multiple connection points with the serial integrated chip 11 in a limited space.
[0036] The slimSAS connector is a connector under the high-speed data transmission interface protocol, which supports a transmission rate of up to 24 Gbps and can meet the needs of large-capacity data storage and high-speed data transmission. Meanwhile, the slimSAS connector adopts a compact structure design and has a small physical size, which is suitable for devices in a limited space. In addition, the slimSAS connector has high reliability characteristics, which can ensure the stability and accuracy of data transmission.
[0037] Optionally, the bit width of the MCIO connector and the serial integrated chip 11 can be compatible with X2, X4, X8, and X16; the bit width of the M.2 and U.2 connectors is X4; and the bit width of the AIC connector can be set to X4, X8, or X16.
[0038] Optionally, the bit width of the multiple types of connectors 22 is X16, which can be downward compatible with the channel number of X8 or X4. In the case of uninterrupted power supply, the external card is hot-plugged, which completely simulates the actual application scenario of the product.
[0039] Further, referring to Figure 2 , the test device 1000 further includes a memory 13, the serial integrated chip 11 includes a memory control module M1, and the memory 13 is connected to the memory control module M1.
[0040] The memory 13 is connected to the serial integrated chip 11 through the memory control module M1, and is used for data caching of the serial integrated chip 11.
[0041] Specifically, the type of the memory 13 can be a DDR5 memory 13, a DDR4 memory 13, or other memories 13 suitable for high-speed data transmission, which are not limited in the present application.
[0042] Further, referring to Figure 3The test unit 100 further comprises a physical layer module 16 and an RJ45 interface 17. The first end of the physical layer module 16 is connected to the RGMII interface P1 of the serial integrated chip 11, and the second end of the physical layer module 16 is connected to the RJ45 interface 17.
[0043] The physical layer (PHY) module is responsible for connecting the data link layer device and the physical medium, ensuring smooth data communication between devices.
[0044] Specifically, the physical layer module 16 acts as a converter between analog signals on the cable and digital signals on the device. When transmitting data, it converts the parallel data from the MAC layer into a serial stream of data, encodes the data according to the physical layer coding rules, and then converts the data into an analog signal for transmission. When receiving data, it converts the received analog signal into a digital signal and decodes it to recover the original data, establishing a communication connection between the serial integrated chip 11 and the host computer 300 through the RJ45 interface 17.
[0045] Optionally, referring to Figure 4 The test device 1000 further comprises a power seat 14, a first power management integrated circuit 15, and a second power management integrated circuit 23. The first end of the first power management integrated circuit 15 (PMIC) is connected to the first end of the power seat 14, the second end of the first power management integrated circuit 15 is connected to the serial integrated chip 11, the second end of the power seat 14 is connected to the first high-speed connector 12, the first end of the second power management integrated circuit 23 is connected to the second high-speed connector 21, and the second end of the second power management integrated circuit 23 is connected to the M.2 connector, the U.2 connector, the AIC connector, the SATA connector, or the XGMAC connector.
[0046] The power seat 14 is the power inlet of the entire test device 1000, responsible for receiving external power input.
[0047] The first power management integrated circuit 15 is responsible for managing the power received from the power seat 14 and distributing it to other components in the test device 1000.
[0048] The second power management integrated circuit 23 is responsible for managing additional power paths to provide power for different storage devices or network interfaces.
[0049] Specifically, the serial integrated chip 11 controls the second power management integrated circuit 23 through IIC, and when the serial integrated chip 11 identifies that there is an external card on each connector, the serial integrated chip 11 controls the second power management integrated circuit 23 to output the required power supply of the product to each product form connector, and then communication is performed.
[0050] Wherein, the XGMAC connector cannot identify whether an external optical module is inserted, and can be identified by an external dial switch; the power supply of the optical module needs to be turned off, and the dial switch is set to OFF, otherwise the second power management integrated circuit 23 will always supply power to the optical module.
[0051] Through the two power management integrated circuits, the test device 1000 can efficiently manage the power input and distribute the power according to the needs of different components.
[0052] Referring to Figure 5 Optionally, the interface unit 200 further comprises a temperature sensor 24 connected to the third end of the second power management integrated circuit 23, for collecting the temperature of the plurality of connectors 22.
[0053] The temperature sensor 24 can monitor the temperature of each type of connector connected to the second power management integrated circuit 23 in real time, and feed back the collected temperature of each type of connector to the serial integrated chip 11 of the test unit 100 through IIC communication.
[0054] Referring to Figure 6 Optionally, the test unit 100 further comprises a first fan connector 16, and the serial integrated chip 11 further comprises a PWM module M2, the first fan connector 16 being connected to the PWM module M2, and the first fan connector 16 being further used for connecting a fan for cooling the serial integrated chip 11.
[0055] The first fan connector 16 is connected to the PWM module M2, and it serves as an interface between the fan and the test unit 100, responsible for transmitting the PWM signal to the fan to control the speed of the fan. Through the fan connected to the fan connector, the serial integrated chip 11 can be effectively cooled to prevent overheating under long-time work or high load.
[0056] Optionally, the PWM module M2 can intelligently adjust the speed of the fan according to the temperature of the serial integrated chip 11 or other related parameters. When the temperature of the chip rises, the PWM module M2 will increase the pulse width, thereby increasing the speed of the fan to enhance cooling; when the temperature of the chip decreases, the speed of the fan will be correspondingly reduced to save energy and reduce noise.
[0057] Further, the interface unit 200 further comprises a second fan connector 25, the PWM module M2 is further connected to the first high-speed connector 12, the second fan connector 25 is connected to the second high-speed connector 21, and the second fan connector 25 is further used to connect the fan for dissipating heat of the multi-type connector 22.
[0058] The second fan connector 25 is connected to the second high-speed connector 21, and obtains the control signal from the PWM module M2 through the connection between the first high-speed connector 12 and the second high-speed connector 21, so as to control the rotating speed of the fan. Through the fan connected to the fan connector, the multi-type connector 22 can be effectively cooled to prevent overheating under long-time work or high load.
[0059] Optionally, the PWM module M2 can intelligently adjust the rotating speed of the fan according to the temperature of the multi-type connector 22 collected by the temperature sensor 24 of the serial integrated chip 11. When the temperature of the multi-type connector 22 rises, the PWM module M2 increases the pulse width, so as to increase the rotating speed of the fan to strengthen cooling; when the temperature of the multi-type connector 22 decreases, the rotating speed of the fan is correspondingly reduced to save energy and reduce noise.
[0060] Optionally, referring to Figure 7 , the test unit 100 further comprises a user indicator light 17, and the serial integrated chip 11 further comprises a general-purpose input / output module M3, and the user indicator light 17 is connected to the general-purpose input / output (GPIO) module.
[0061] The user indicator light 17 is connected to the general-purpose input / output module M3 of the serial integrated chip 11. The general-purpose input / output module M3 is a commonly used input / output interface, which allows the serial integrated chip 11 to exchange data with external devices such as the user indicator light 17.
[0062] The user indicator light 17 can directly indicate the hot-plug state, other connection state and test state such as power supply state of various connectors in the test unit 100 through different flashing modes or color changes, so that the user can quickly understand the working state of the test unit 100.
[0063] Referring to Figure 8 , Figure 8 is a structural schematic diagram of an embodiment of the multi-type device test system 2000 provided by the present application, comprising a host computer 300, a test device 1000 as described above and multi-type devices to be tested 400, and the multi-type devices to be tested 400 comprise at least two of M.2 solid state disks, U.2 solid state disks, AIC solid state disks, SATA disks or XGMAC optical modules.
[0064] The host computer 300 is responsible for controlling and scheduling the entire test process, can send instructions to the test device 1000 according to the preset test scheme, to realize the test of different types of devices to be tested. The host computer 300 is also used to receive the data collected from the device to be tested by the test device 1000, and process and analyze.
[0065] Different from the prior art, the application provides a test device 1000 with multiple types of interfaces and a multiple-type device test system 2000. By setting multiple types of connectors on the interface unit 200, devices with different interface specifications, such as external cards, can be tested. At the same time, a serial integrated chip 11 supporting PCIe, SATA, and XGMAC type devices is used to connect devices with multiple specifications for testing, without the need to purchase an adapted server, reducing testing costs, realizing the testing of various high-speed SerDes products, and reducing the testing difficulty and cost of high-speed SerDes products.
[0066] The above is only an embodiment of the application, and does not limit the patent scope of the application. Any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the application.
Claims
1. A test apparatus having multiple types of interfaces, characterized by, The test device comprises: a first circuit board, a serial integrated chip and a first high-speed connector arranged on the first circuit board, the serial integrated chip being in communication connection with the first high-speed connector; a second circuit board, a second high-speed connector and a multi-type connector arranged on the second circuit board, the second high-speed connector being in communication connection with the multi-type connector; the first high-speed connector and the second high-speed connector are in communication connection, and the multi-type connector comprises at least two of an M.2 connector, a U.2 connector, an AIC connector, a SATA connector or an XGMAC connector.
2. The test device of claim 1, wherein, The first high-speed connector and the second high-speed connector are both MCIO connectors or slimSAS connectors.
3. The test device of claim 1, wherein, The test device further comprises a memory, the serial integrated chip comprises a memory control module, and the memory is connected to the memory control module.
4. The test device of claim 1, wherein, The first circuit board further comprises a physical layer module and an RJ45 interface, a first end of the physical layer module being connected to an RGMII interface of the serial integrated chip, and a second end of the physical layer module being connected to the RJ45 interface.
5. The test device of claim 1, wherein, The test device further comprises a power seat, a first power management integrated circuit and a second power management integrated circuit; a first end of the first power management integrated circuit being connected to a first end of the power seat, a second end of the first power management integrated circuit being connected to the serial integrated chip, a second end of the power seat being connected to the first high-speed connector, a first end of the second power management integrated circuit being connected to the second high-speed connector, and a second end of the second power management integrated circuit being connected to the M.2 connector, the U.2 connector, the AIC connector, the SATA connector or the XGMAC connector.
6. The test device of claim 5, wherein, The second circuit board further comprises a temperature sensor, the temperature sensor being connected to a third end of the second power management integrated circuit and used for collecting the temperature of the multi-type connector.
7. The test device of claim 1, wherein, The test device further comprises a first fan connector, the serial integrated chip further comprises a PWM module, the first fan connector being connected to the PWM module, and the first fan connector being further used for connecting a fan for dissipating heat of the serial integrated chip.
8. The test device of claim 7, wherein, The second circuit board further comprises a second fan connector, the PWM module is further connected to the first high-speed connector, the second fan connector is connected to the second high-speed connector, and the second fan connector is further used for connecting a fan for dissipating heat of the multi-type connector.
9. The test device of claim 1, wherein, The test device further comprises a user indicator light, and the serial integrated chip further comprises a general-purpose input-output module, the user indicator light being connected to the general-purpose input-output module.
10. A multi-type device testing system, comprising: The test device comprises: a host computer, the test device as claimed in any one of claims 1-9, and a plurality of devices to be tested, the plurality of devices to be tested comprising at least two of an M.2 solid-state disk, a U.2 solid-state disk, an AIC solid-state disk, a SATA disk or an XGMAC optical module.