Quick-response bias protection hardware circuit
By introducing a fast-response bias protection hardware circuit into the converter and using a sampling and comparator to monitor the bus voltage, the problems of slow response and low reliability of converter bias protection are solved, and fast response and self-locking protection are achieved.
Patent Information
- Application Number
- CN202520365575.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-04
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2035-03-04
AI Technical Summary
Existing converters suffer from slow bias protection response time and low reliability, and traditional methods rely on software protection, resulting in sluggish response.
The system employs a fast-response bias protection hardware circuit. It samples the bus voltage through a sampling module and compares it with a reference signal using first and second comparators to control the conduction or cutoff of the optocoupler isolator, thereby achieving real-time monitoring and protection of the bus voltage.
It achieves a fast response time of less than 20μs and high reliability protection, with a self-locking function, fault reset after power failure, and blocking of drive pulses.
Smart Images
Figure CN223912238U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of bias protection circuit, specifically a quick response's bias protection hardware circuit. BACKGROUND
[0002] During the working process of the converter, overvoltage protection needs to be carried out on it, and the traditional overvoltage protection generally samples the upper half bus voltage and the lower half bus voltage, and compares the sampling results with the over-limit reference voltage, but this method only carries out overvoltage protection on the capacitor voltage; in the prior art, software protection is generally used to carry out overvoltage protection on the converter, the sampling circuit converts the bus voltage into a voltage signal, the voltage signal is converted into a digital quantity through an A / D converter, the MCU program reads the conversion results of the two groups of voltages, and the MCU program judges according to the conversion results; when the bias is serious, the bus is protected by software, and this method has slow response time and low reliability. UTILITY MODEL CONTENTS
[0003] In order to solve the problems of slow response time and low reliability of bias protection in the prior art, the utility model provides a quick response bias protection hardware circuit, which has short response time and is more reliable.
[0004] In order to achieve the above-mentioned purpose, the utility model adopts the specific scheme that a quick response bias protection hardware circuit, comprising a sampling module, a reference module, a detection module and a bus control module;
[0005] The sampling module is used for sampling the bus voltage and outputting NVOPU signals and NVOPD signals;
[0006] The reference module is used for providing first reference signals and second reference signals;
[0007] The detection module comprises a first logic circuit, a second logic circuit and an optocoupler isolator;
[0008] The first logic circuit comprises a first comparator and a MOS tube Q19, the NVOPU signals and the first reference signals are respectively input to two input ends of the first comparator, the first comparator outputs a first control signal according to the NVOPU signals and the first reference signals, and the MOS tube Q19 controls the conduction or cutoff of the optocoupler isolator according to the first control signal;
[0009] The second logic circuit comprises a second comparator and a MOS tube Q20, the NVOPD signals and the second reference signals are respectively input to two input ends of the second comparator, and the second comparator outputs a third control signal according to the NVOPD signals and the second reference signals, and the MOS tube Q20 controls the conduction or cutoff of the optocoupler isolator according to the third control signal;
[0010] When the optocoupler isolator is turned on, the second control signal is output.
[0011] The bus control module is used to control the driving pulse of the bus according to the second control signal.
[0012] As an optimization of the above-mentioned fast-response bias protection hardware circuit, the output end of the first comparator is connected with a diode D56, the positive electrode of the diode D56 is connected with the output end of the first comparator, and the negative electrode of the diode D56 is connected with the input end of the first comparator inputting the NVOPU signal.
[0013] As another optimization of the above-mentioned fast-response bias protection hardware circuit, the input end of the first comparator inputting the first reference signal is connected with a resistor R381.
[0014] As another optimization of the above-mentioned fast-response bias protection hardware circuit, the gate end of the MOS tube Q19 is connected with a diode D58, the positive electrode of the diode D58 is connected with the gate end of the MOS tube Q19, and the negative electrode of the diode D58 is connected with the output end of the first comparator.
[0015] As another optimization of the above-mentioned fast-response bias protection hardware circuit, the output end of the second comparator is connected with a diode D60, the positive electrode of the diode D60 is connected with the output end of the second comparator, and the negative electrode of the diode D60 is connected with the input end of the second comparator inputting the NVOPD signal.
[0016] As another optimization of the above-mentioned fast-response bias protection hardware circuit, the input end of the first comparator inputting the second reference signal is connected with a resistor R384.
[0017] As another optimization of the above-mentioned fast-response bias protection hardware circuit, the gate end of the MOS tube Q20 is connected with a diode D61, the positive electrode of the diode D61 is connected with the gate end of the MOS tube Q20, and the negative electrode of the diode D61 is connected with the output end of the second comparator.
[0018] As another optimization of the above-mentioned fast-response bias protection hardware circuit, the positive electrode of the optocoupler isolator is connected with the gate end of the MOS tube Q19 and the gate end of the MOS tube Q20 respectively, and the negative electrode of the optocoupler isolator is connected with the drain end of the MOS tube Q19 and the drain end of the MOS tube Q20 respectively.
[0019] As another optimization of the above-mentioned fast-response bias protection hardware circuit, the source end of the MOS tube Q19 is connected with the resistor R383 and the resistor R380 in series.
[0020] As another optimization scheme of the above-mentioned fast-response bias protection hardware circuit, the source end of the MOS tube Q20 is connected in series with the resistor R386 and the resistor R382.
[0021] Compared with the prior art, the utility model has the following beneficial effects:
[0022] 1. The utility model provides a fast -response bias protection hardware circuit samples the midpoint voltage of bus, and exports NVOPU signal and NVOPD signal, compares NVOPU signal and first reference signal and NVOPD signal and second reference signal through first comparator and second comparator respectively, and exports first control signal and third control signal, MOS tube Q19 controls the conduction or cut -off of photo -coupler isolator according to first control signal, MOS tube Q20 controls the conduction or cut -off of photo -coupler isolator according to third control signal, exports second control signal when photo -coupler isolator conduction, and bus control module controls the drive pulse of bus according to second control signal, when bus bias, photo -coupler isolator exports second control signal, makes bus control module block drive pulse, possesses 20us below protection speed, response time is short, and the reliability is high.
[0023] 2. In the utility model, the positive pole of diode D56 is connected with the output end of first comparator, the negative pole of diode D56 is connected with the input end of first comparator on input NVOPU signal, the positive pole of diode D60 is connected with the output end of second comparator, the negative pole of diode D60 is connected with the input end of second comparator on input NVOPD signal, so that bias protection hardware circuit realizes self -locking after protection, resets after power failure, and blocks drive pulse. BRIEF DESCRIPTION OF DRAWINGS
[0024] Figure 1 It is the circuit diagram of sampling module;
[0025] Figure 2 It is the circuit diagram of reference module, detection module and bus control module. DETAILED DESCRIPTION
[0026] The technical scheme of the utility model will be further described in detail in combination with specific embodiments, and the parts not detailed and disclosed in the following embodiments of the utility model should be understood as the prior art known or should be known by the person skilled in the art.
[0027] EMBODIMENT
[0028] A fast-response bias protection hardware circuit, comprising a sampling module, a reference module, a detection module and a bus control module;Wherein, the circuit of the sampling module is as Figure 1As shown, the sampling module is used for sampling the bus voltage and outputting the NVOPU signal and the NVOPD signal.
[0029] The circuit of the reference module is as shown in Figure 2 As shown, the reference module is used for providing the first reference signal and the second reference signal, in the embodiment, the first reference signal is 3.3V, and the second reference signal is -3.3V.
[0030] The detection module includes a first logic circuit, a second logic circuit and an optocoupler, and the circuit of the detection module is as shown in Figure 2 As shown, the first logic circuit includes a first comparator (U27A) in Figure 2 and a MOS tube Q19, the NVOPU signal and the first reference signal are respectively input to two input terminals of the first comparator, the first comparator outputs a first control signal according to the NVOPU signal and the first reference signal, and the MOS tube Q19 controls the conduction or cut-off of the optocoupler according to the first control signal. In the embodiment, the input terminal of the first comparator for inputting the NVOPU signal is the first input terminal, and the second input terminal for inputting the first reference signal is connected with a resistor R381. The source terminal and the gate terminal of the MOS tube Q19 are both connected with the output terminal of the first comparator, and the drain terminal of the MOS tube Q19 is connected with the negative electrode of the optocoupler. In the embodiment, a diode D58 is arranged between the gate terminal of the MOS tube Q19 and the output terminal of the first comparator, the positive electrode of the diode D58 is connected with the gate terminal of the MOS tube Q19, and the negative electrode of the diode D58 is connected with the output terminal of the first comparator; the source terminal of the MOS tube Q19 is connected in series with a resistor R383 and a resistor R380.
[0031] In the embodiment, the output terminal of the first comparator is connected with a diode D56, the positive electrode of the diode D56 is connected with the output terminal of the first comparator, and the negative electrode of the diode D56 is connected with the input terminal of the first comparator for inputting the NVOPU signal, i.e. the negative electrode of the diode D56 is connected with the first input terminal of the first comparator.
[0032] The output terminal of the first comparator is connected with a resistor R379.
[0033] The second logic circuit includes a second comparator (U27B) in Figure 2The NVOPD signal and the second reference signal are input to two input terminals of the second comparator respectively, and the second comparator outputs a third control signal according to the NVOPD signal and the second reference signal, and the MOS transistor Q20 controls the conduction or cutoff of the opto-isolator according to the third control signal. In the embodiment, the input terminal of the second comparator for inputting the NVOPD signal is a third input terminal, the input terminal of the second comparator for inputting the second reference signal is a fourth input terminal, and the fourth input terminal is connected with a resistor R384. The source terminal and the gate terminal of the MOS transistor Q20 are connected with the output terminal of the second comparator, and the drain terminal of the MOS transistor Q20 is connected with the negative electrode of the opto-isolator. In the embodiment, a diode D61 is arranged between the gate terminal of the MOS transistor Q20 and the output terminal of the second comparator, the positive electrode of the diode D61 is connected with the gate terminal of the MOS transistor Q20, and the negative electrode of the diode D61 is connected with the output terminal of the second comparator; the source terminal of the MOS transistor Q20 is connected with the resistor R386 and the resistor R382 in series.
[0034] In the embodiment, the output terminal of the second comparator is connected with a diode D60, the positive electrode of the diode D60 is connected with the output terminal of the second comparator, and the negative electrode of the diode D60 is connected with the input terminal of the second comparator for inputting the NVOPD signal, that is, the negative electrode of the diode D60 is connected with the third input terminal of the second comparator.
[0035] The output terminal of the second comparator is connected with the R385.
[0036] The positive electrode of the opto-isolator is connected with the gate terminal of the MOS transistor Q19 and the gate terminal of the MOS transistor Q20 respectively, and the negative electrode of the opto-isolator is connected with the drain terminal of the MOS transistor Q19 and the drain terminal of the MOS transistor Q20 respectively. The opto-isolator outputs a second control signal when it is turned on.
[0037] The circuit of the bus control module is shown as U29 in the figure, and the bus control module is used for controlling the driving pulse of the bus according to the second control signal. Figure 2
[0038] The working principle of the utility model is as follows:
[0039] The sampling module samples the bus voltage and outputs the NVOPU signal and the NVOPD signal, when the bus voltage is balanced, the NVOPU signal is less than 3.3V, the output terminal of the first comparator is turned on, and the output terminal is pulled to a level close to -5V, at this time, the diode D56 is reversely cut off, the diode D58 is turned on, and then the gate terminal of the MOS transistor Q19 is pulled to a level close to -5V, the MOS transistor Q19 is turned off, the drain terminal of the MOS transistor Q19 outputs a high level to the ground, the opto-isolator is cut off, and a high level is output without fault. Figure 2
[0040] When the bus voltage is biased to the positive polarity, the NVOPU signal is greater than 3.3V, the output of the first comparator is cut off, and the output pin of the first comparator is pulled up to a level close to +5V through R379. At this time, diode D56 is turned on, diode D58 is turned off, and MOSFET Q19 is turned on under the DC bias provided by R380 and R383, which in turn turns on the optocoupler isolator and outputs the second control signal (low level) to report a fault. The bus control module blocks the bus drive pulse according to the second control signal. At the same time, the first comparator feeds back a high level (+5V) greater than 3.3V to the first input terminal through diode D56, and the output of the first comparator is cut off, that is, the output of the first comparator maintains a high level (+5V) to form a self-locking.
[0041] When the bus voltage is balanced, the NVOPD signal is greater than -3.3V, the output of the second comparator is turned on, and the output pin is pulled to a level close to -5V. At this time, diode D60 is reverse-biased and diode D61 is turned on, which sets the gate level of MOSFET Q20 to ( Figure 2 When pin 1 of MOSFET Q20 is pulled to near -5V, MOSFET Q20 is turned off, which in turn causes the drain terminal of MOSFET Q20 to output a high level to ground. The optocoupler isolator is then turned off and outputs a high level without reporting a fault.
[0042] When the bus voltage is negatively biased, the NVOPD signal is less than -3.3V, the output of the second comparator is cut off, and the output pin is pulled up to a level close to +5V via R385. At this time, diode D60 is turned on, diode D61 is turned off, and MOSFET Q20 is turned on under the DC bias provided by R382 and R386. The optocoupler isolator is turned on and outputs the second control signal (low level) to report a fault. The bus control module blocks the bus drive pulse according to the second control signal. At the same time, diode D60 feeds back a high level to the third input, causing the feedback signal of diode D60 to pull the NVOPD signal to -5V. The output of the second comparator is in the off state, that is, the output of the second comparator is kept at a high level to form a self-locking mechanism.
[0043] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A fast responding bias protection hardware circuit, characterized by: The sampling module, the reference module, the detection module and the bus control module are included. The sampling module is used for sampling the bus voltage and outputting the NVOPU signal and the NVOPD signal. The reference module is used for providing the first reference signal and the second reference signal. The detection module includes the first logic circuit, the second logic circuit and the optocoupler isolator. The first logic circuit includes the first comparator and the MOS tube Q19, the NVOPU signal and the first reference signal are input to two input terminals of the first comparator respectively, the first comparator outputs the first control signal according to the NVOPU signal and the first reference signal, and the MOS tube Q19 controls the conduction or the cut-off of the optocoupler isolator according to the first control signal. The second logic circuit includes the second comparator and the MOS tube Q20, the NVOPD signal and the second reference signal are input to two input terminals of the second comparator respectively, and the second comparator outputs the third control signal according to the NVOPD signal and the second reference signal, and the MOS tube Q20 controls the conduction or the cut-off of the optocoupler isolator according to the third control signal. The second control signal is output when the optocoupler isolator is conducted. The bus control module is used for controlling the driving pulse of the bus according to the second control signal.
2. A fast responding bias protection hardware circuit as claimed in claim 1, characterized in that: The output terminal of the first comparator is connected with the diode D56, the positive electrode of the diode D56 is connected with the output terminal of the first comparator, and the negative electrode of the diode D56 is connected with the input terminal of the first comparator inputting the NVOPU signal.
3. A fast responding bias protection hardware circuit as claimed in claim 1, wherein: The input terminal of the first comparator inputting the first reference signal is connected with the resistor R381.
4. A fast responding bias protection hardware circuit as claimed in claim 1, wherein: The gate terminal of the MOS tube Q19 is connected with the diode D58, the positive electrode of the diode D58 is connected with the gate terminal of the MOS tube Q19, and the negative electrode of the diode D58 is connected with the output terminal of the first comparator.
5. A fast responding bias protection hardware circuit as claimed in claim 1, wherein: The output terminal of the second comparator is connected with the diode D60, the positive electrode of the diode D60 is connected with the output terminal of the second comparator, and the negative electrode of the diode D60 is connected with the input terminal of the second comparator inputting the NVOPD signal.
6. A fast responding bias protection hardware circuit as claimed in claim 1, wherein: The input terminal of the first comparator inputting the second reference signal is connected with the resistor R384.
7. A fast responding bias protection hardware circuit as claimed in claim 1, wherein: The gate terminal of the MOS tube Q20 is connected with the diode D61, the positive electrode of the diode D61 is connected with the gate terminal of the MOS tube Q20, and the negative electrode of the diode D61 is connected with the output terminal of the second comparator.
8. A fast responding bias protection hardware circuit as claimed in claim 1, wherein: The positive electrode of the optocoupler isolator is connected with the gate terminal of the MOS tube Q19 and the gate terminal of the MOS tube Q20 respectively, and the negative electrode of the optocoupler isolator is connected with the drain terminal of the MOS tube Q19 and the drain terminal of the MOS tube Q20 respectively.
9. A fast responding bias protection hardware circuit as claimed in claim 1, wherein: The source terminal of the MOS tube Q19 is connected with the resistor R383 and the resistor R380 in series.
10. A fast responding bias protection hardware circuit as claimed in claim 1, wherein: The source terminal of the MOS tube Q20 is connected with the resistor R386 and the resistor R382 in series.