QFN packaging structure

Abstract

The utility model discloses a QFN packaging structure, which comprises a heat dissipation substrate, a plurality of chips, a plurality of pins, a plurality of leads and a mold sealing body, and is characterized in that the heat dissipation substrate comprises a first metal layer, a ceramic layer and a second metal layer, the first metal layer, the ceramic layer and the second metal layer are sequentially stacked, and the first metal layer comprises a plurality of base islands which are mutually spaced; the plurality of chips are connected to the sides, back to the ceramic layer, of the corresponding base islands; the plurality of pins are arranged around the heat dissipation substrate, and the pins and the heat dissipation substrate are mutually spaced; the plurality of leads are electrically connected to the corresponding chips and the pins; the molding body covers the heat dissipation substrate, the chip, the pins and the leads, and part of the surfaces of the second metal layer and the pins are exposed out of the molding body. The embodiment can simplify the process steps and improve the efficiency.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor manufacturing, especially to a QFN package structure. BACKGROUND

[0002] For the traditional QFN package (Quad Flat No-leads Package, square flat no-lead package), one preparation process is to first etch the upper surface of the copper substrate to form a pin area and a base island area, and then perform subsequent chip connection, lead connection and first molding, etc. operations, and then etch the lower surface of the copper substrate again after the first molding, so as to completely remove the remaining copper layer between the base island areas, between the pin areas, and between the base island area and the pin area, and finally perform a second molding operation to fill the gap generated by the second etching. However, this process needs to go through two etchings and two moldings, which is complex and affects the production efficiency of the package structure. SUMMARY

[0003] The utility model aims at at least solving one of the technical problems existing in the prior art. Therefore, the utility model provides a QFN package structure which can simplify the process and improve the efficiency.

[0004] According to the QFN package structure of the first embodiment of the utility model, it comprises:

[0005] The heat dissipation substrate comprises a first metal layer, a ceramic layer and a second metal layer, the first metal layer, the ceramic layer and the second metal layer are sequentially stacked, the first metal layer comprises a plurality of base islands spaced from each other;

[0006] A plurality of chips are connected to the side of the base island opposite to the ceramic layer;

[0007] A plurality of pins are arranged around the heat dissipation substrate, and the pins and the heat dissipation substrate are spaced from each other;

[0008] A plurality of leads are electrically connected to the corresponding chips and pins;

[0009] The molding body covers the heat dissipation substrate, the chips, the pins and the leads, and part of the surface of the second metal layer and the pins is exposed to the molding body.

[0010] According to the package structure of the first embodiment of the utility model, at least the following beneficial effects are achieved:

[0011] The heat dissipation substrate is used to replace the traditional copper substrate in the embodiment, the base island can take the ceramic layer at the lower layer as a connecting and supporting carrier to maintain its own position, therefore, the upper metal layer of the heat dissipation substrate can be etched to directly obtain the base islands arranged at intervals, without the need of secondary etching, and accordingly, without the need of secondary mold sealing, so that the process steps can be simplified and the efficiency can be improved.

[0012] In other embodiments of the present application, along the stacking direction of the first metal layer, the ceramic layer and the second metal layer, the side of the pin away from the chip is flush with the side of the second metal layer away from the chip.

[0013] In other embodiments of the present application, the second metal layer has a first side and a second side, the ceramic layer has a third side corresponding to the first side and a fourth side corresponding to the second side, and the distance between the fourth side and the second side is greater than the distance between the first side and the third side.

[0014] In other embodiments of the present application, the heat dissipation substrate further comprises an insulating layer, the insulating layer is arranged on the side of the ceramic layer away from the chip, the thickness of the insulating layer is equal to the thickness of the second metal layer, and the insulating layer is arranged between the fourth side and the second side.

[0015] In other embodiments of the present application, the insulating layer is an insulating ink coated on the surface of the ceramic layer.

[0016] In other embodiments of the present application, the projection of each base island on the ceramic layer is located within the projection of the insulating layer and the second metal layer on the ceramic layer.

[0017] In other embodiments of the present application, the plurality of chips includes at least one power chip, the plurality of base islands includes at least one power base island, the power chip is connected to the power base island, and the projection of the power base island on the ceramic layer at least partially overlaps with the projection of the second metal layer on the ceramic layer.

[0018] In other embodiments of the present application, the plurality of chips includes at least one power chip and at least one control chip, the plurality of base islands includes at least one power base island and at least one control base island, the power chip is connected to the power base island, and the control chip is connected to the control base island.

[0019] Additional aspects and advantages of the present application will be given in part in the following description, and will become apparent from the following description, or will be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein:

[0021] Figure 1 This is a three-dimensional schematic diagram showing the front of the packaging structure in an embodiment of the present utility model;

[0022] Figure 2 for Figure 1 A 3D schematic diagram of the back of the packaged structure is shown.

[0023] Figure 3 for Figure 1 Side view of the encapsulation structure;

[0024] Figure 4 for Figure 3 Enlarged view of region A in the middle;

[0025] Figure 5 for Figure 1 Front view of the encapsulation structure.

[0026] Figure label:

[0027] QFN package structure 10;

[0028] Heat dissipation substrate 100, first metal layer 110, base island 111, power base island 111a, control base island 111b, second metal layer 120, first side 121, second side 122, ceramic layer 130, third side 131, fourth side 132, insulating layer 140;

[0029] Chip 200, power chip 210, control chip 220;

[0030] Pin 300;

[0031] Lead wire 400. Detailed Implementation

[0032] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0033] In the description of this utility model, it should be understood that the directional descriptions, such as up, down, front, back, left, right, etc., indicate the directional or positional relationship based on the directional or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0034] In the description of the utility model, if the meaning of several is more than one, the meaning of multiple is more than two, greater than, less than, more than and the like are understood as not including the number, above, below, within and the like are understood as including the number.If there is a description to the first, second is only used for distinguishing the purpose of technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the sequence of indicated technical features.

[0035] In the description of the utility model, unless otherwise explicitly limited, the words such as setting, installation, connection should be understood in a broad sense, and the person skilled in the art can reasonably determine the specific meaning of the above words in the utility model according to the specific content of the technical scheme.

[0036] In the description of the utility model, the description of reference terms "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model.In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0037] As described previously, the traditional packaging process for the high-integration QFN packaging structure at present includes the following steps: firstly, the upper surface of the copper substrate is etched for the first time, so as to form the base island area and the pin area for connecting the chip, and the etching depth is lower than the thickness of the copper plate, that is, the base island area and the pin area at this time are still connected with the lower area which has not been etched, and the lower area can be used as a support and a connecting carrier to keep the position of the base island area fixed in the transfer and further preparation process.Then, the chip is connected in the base island area, and the chip and the corresponding pin area are connected through the lead wire, and the first molding is performed after the lead wire connection is completed, and the molding body formed by the first molding covers the chip, the lead wire and part of the copper substrate, and exposes the lower surface of the copper substrate.After the first molding, the lower surface of the copper substrate is etched for the second time to remove the residual copper material between the pin areas, between the base island areas and between the pin areas and the base island areas, and finally the second molding is performed to fill the gap formed after etching.It can be known from the above that this way needs to be etched twice and molded twice, which is complicated and is not conducive to improving the preparation efficiency of the packaging structure.Based on the above problems, the utility model provides a QFN packaging structure which can simplify the preparation process.

[0038] Referring to Figure 1 , Figure 2The QFN package structure 10 in this embodiment includes a heat dissipation substrate 100, multiple chips 200, multiple pins 300, multiple leads 400, and a molded body (not shown). The multiple chips 200, multiple leads 400, heat dissipation substrate 100, and pins 300 are encapsulated in a molded body made of a material such as epoxy resin. Part of the surface of the heat dissipation substrate 100 is exposed outside the molded body for heat dissipation, and part of the surface of the pins 300 is exposed outside the molded body for electrical connection with external devices. Specifically, the lower surface of the heat dissipation substrate 100 is exposed from the lower surface of the molded body, the lower surface of the pins 300 is exposed from the lower surface of the molded body, and one side of the pins 300 is exposed from the side of the molded body.

[0039] Reference Figure 3 , Figure 4 The heat dissipation substrate 100 includes a first metal layer 110, a ceramic layer 130, and a second metal layer 120, which are sequentially stacked. For example, the first metal layer 110, ceramic layer 130, and second metal layer 120 are stacked from top to bottom. The first metal layer 110 includes a plurality of base islands 111. For example, see [reference needed]. Figure 1 The first metal layer 110 includes five base islands 111, with two larger base islands 111 generally located on the right and three smaller base islands 111 generally located on the left. Of course, the number and position of the base islands 111 are not limited to this. The base islands 111 are spaced apart from each other. For example, the first metal layer 110 can be formed by etching the upper metal layer of a conventional heat dissipation substrate 100, with the etched portion serving as the base islands 111. The lower surface of the second metal layer 120 is exposed from the lower surface of the molded body. Thus, the heat generated when the chip 200 is operating is transferred to the external environment through the first metal layer 110, the ceramic layer 130, and the second metal layer 120, thereby achieving heat dissipation for the chip 200.

[0040] The number of chips 200 corresponds to the number of base islands 111, and each chip 200 is connected to the side of the corresponding base island 111 facing away from the ceramic layer 130. For example, the chip 200 is connected to the upper side of the corresponding base island 111. The chip 200 and the base island 111 can be connected by a high-conductivity, high-heat-dissipation material such as solder paste or silver paste.

[0041] Multiple pins 300 are arranged around the heat sink 100, and the pins 300 and the heat sink 100 are spaced apart from each other, such as... Figure 1 As shown, the heat dissipation substrate 100 is a rectangular substrate, and pins 300 are provided at intervals on all four sides of the rectangular substrate. The lower surface of the pins 300 and the side facing away from the heat dissipation substrate 100 are exposed from the mold body.

[0042] The lead wire 400 is electrically connected to the corresponding chip 200 and the pin 300, and is connected to the chip 200 and the pin 300 by ultrasonic bonding in an exemplary manner. It should be noted that in some more specific embodiments, the QFN packaging structure 10 has a lead wire for electrical connection between the chips 200 in addition to the aforementioned lead wire 400 for electrical connection between the chip 200 and the pin 300.

[0043] In the embodiment, the heat dissipation substrate 100 is used instead of the traditional copper substrate, and the base island 111 can use the lower ceramic layer 130 as a connecting and supporting carrier to maintain its position, so that the upper metal layer of the heat dissipation substrate 100 can be etched to directly obtain the spaced base islands 111, without the need for secondary etching and corresponding secondary mold sealing, thereby simplifying the process steps and improving efficiency.

[0044] On the basis of the first embodiment, in some embodiments of the utility model, referring to Figure 4 The side of the pin 300 away from the chip 200 is flush with the side of the second metal layer 120 away from the chip 200, and the lower surface of the pin 300 is flush with the lower surface of the second metal layer 120 in an exemplary manner. In this way, each pin 300 in the embodiment can be used as a component independent of the heat dissipation substrate 100, and is connected by a connecting rib to form an integrated frame structure when delivered. During the preparation process, the frame structure and the heat dissipation substrate 100 are placed together in a jig to fix the relative position of the two, and after the mold sealing operation, the connecting rib and the mold sealing body corresponding to the connecting rib are cut by a tool, so that each pin 300 can be disconnected to obtain the final packaging structure.

[0045] On the basis of the first embodiment, in some embodiments of the utility model, referring to Figure 2The second metal layer 120 has a first side 121 and a second side 122, and the ceramic layer 130 has a third side 131 corresponding to the first side 121 and a fourth side 132 corresponding to the second side 122. The distance between the fourth side 132 and the second side 122 is greater than the distance between the first side 121 and the third side 131, that is, the distance between the second side 122 of the second metal layer 120 and the fourth side 132 is relatively farther, so as to reduce the spurious interference caused by the second metal layer 120 being too close to the corresponding side pin 300 when the working voltage of the QFN package structure 10 is high (for example, the output voltage is greater than 650 volts). For example, the upper side of the second metal layer 120 and the upper side of the ceramic layer 130 are the first side 121 and the third side 131 respectively, the left side of the second metal layer 120 and the left side of the ceramic layer 130 are the second side 122 and the fourth side 132 respectively, or the right side of the second metal layer 120 and the right side of the ceramic layer 130 are the second side 122 and the fourth side 132 respectively, or the lower side of the second metal layer 120 and the lower side of the ceramic layer 130 are the second side 122 and the fourth side 132 respectively.

[0046] It should be noted that the lower metal layer of the conventional heat dissipation substrate can be partially removed by etching to obtain the second metal layer 120 in the embodiment. For example, before etching, the distance between each side edge of the lower metal layer of the heat dissipation substrate to the corresponding edge of the ceramic layer 130 is equal. After removing part of the material on the left side, the lower side and the right side by etching, the second metal layer 120 shown in the figure can be obtained. At this time, the left side, the lower side and the right side of the second metal layer 120 are the second side 122 mentioned above. Figure 2

[0047] When the second metal layer 120 has the first side 121 and the second side 122, in some embodiments of the utility model, referring to Figure 2 The heat dissipation substrate 100 further comprises an insulating layer 140, which is arranged on the side of the ceramic layer 130 away from the chip 200, that is, the insulating layer 140 and the second metal layer 120 are arranged on the same side of the ceramic layer 130.

[0048] ​In the embodiment, the thickness of the insulating layer 140 is equal to the thickness of the second metal layer 120, and the insulating layer 140 is arranged between the fourth side 132 and the second side 122. As described above, when the second metal layer 120 is formed by etching, the corresponding area of the ceramic layer 130 is in a suspended state due to the removal of part of the material of the underlying metal layer, and when the lead is connected by ultrasonic bonding, the suspended area will cause the heat dissipation substrate to deform and oscillate, thereby affecting the connection quality of the lead. In the embodiment, the insulating layer 140 fills the space generated by the removal of the material, which can replace the metal layer to support the ceramic layer 130, thereby ensuring the connection quality of the lead. In some more specific embodiments, the insulating layer 140 is an insulating ink coated on the surface of the ceramic layer 130, which can be coated by a known process and is easy to implement.

[0049] When the heat dissipation substrate 100 further includes the insulating layer 140, in some embodiments of the utility model, the projection of each base island 111 on the ceramic layer 130 is located within the projection of the insulating layer 140 and the second metal layer 120 on the ceramic layer 130, in other words, when the insulating layer 140 and the second metal layer 120 are collectively regarded as a support layer, the projection of each base island 111 on the ceramic layer 130 is located within the projection of the support layer, in this way, the connection position of each lead 400 on the heat dissipation substrate can be supported. For example, the support layer formed by the insulating layer 140 and the second metal layer 120 has the same area as the underlying metal layer before etching.

[0050] When the second metal layer 120 has a first side 121 and a second side 122, in some embodiments of the utility model, with reference to Figure 5 , the plurality of chips 200 includes at least one power chip 210, the plurality of base islands 111 includes at least one power base island 111a, the power chip 210 is connected to the power base island 111a, and the projection of the power base island 111a on the ceramic layer 130 at least partially overlaps with the projection of the second metal layer 120 on the ceramic layer 130. The power chip 210 generates a large amount of heat when working, and the embodiment sets the power base island 111a and the second metal layer 120 to at least partially overlap, so that the heat generated by the power chip 210 is more easily transmitted to the outside, which is beneficial to the heat dissipation of the packaging structure.

[0051] In the embodiment of the utility model, base island 111 is supported through ceramic layer 130, and it is not necessary to set additional base island support structure (in some other conventional QFN package structure, base island 111 needs to be connected to pin 300 through intermediate connecting rib to ensure the stable connection of single package body of whole plate frame and its mechanical strength, and these intermediate connecting ribs need to occupy more space, resulting in the number of base island 111 being limited, and further limiting the integration of QFN package structure), therefore the embodiment can increase the number of base island 111 and chip 200, and improve the integration of package structure. Wherein, multiple chips 200 include at least one power chip 210 and at least one control chip 220, and multiple base islands 111 include at least one power base island 111a and at least one control base island 111b, power chip 210 is connected to power base island 111a, and control chip 220 is connected to control base island 111b. Exemplarily, QFN package structure 10 includes two power chips 210 and three control chips 220.

[0052] The utility model has been explained in detail above in combination with the drawings, but the utility model is not limited to the above-mentioned embodiment, and within the knowledge range of ordinary skilled in the art, various changes can be made without departing from the purpose of the utility model. In addition, the embodiments and the features in the embodiments of the utility model can be combined with each other without conflict.

Claims

1. A QFN package structure, characterized in that, The application relates to a heat dissipation substrate, comprising a first metal layer, a ceramic layer and a second metal layer, the first metal layer, the ceramic layer and the second metal layer are sequentially stacked, the first metal layer comprises a plurality of base islands spaced from each other; a plurality of chips are connected to the side of the base islands away from the ceramic layer; a plurality of pins are arranged around the heat dissipation substrate and spaced from the heat dissipation substrate; a plurality of leads are electrically connected to the chips and the pins; a mold sealing body covers the heat dissipation substrate, the chips, the pins and the leads, and part of the surface of the second metal layer and part of the surface of the pins are exposed to the mold sealing body. The side of the pins away from the chips is flush with the side of the second metal layer away from the chips in the stacking direction of the first metal layer, the ceramic layer and the second metal layer. The second metal layer has a first side and a second side, the ceramic layer has a third side corresponding to the first side and a fourth side corresponding to the second side, and the distance between the fourth side and the second side is greater than the distance between the first side and the third side. The heat dissipation substrate further comprises an insulating layer arranged on the side of the ceramic layer away from the chips, the thickness of the insulating layer is equal to the thickness of the second metal layer, and the insulating layer is arranged between the fourth side and the second side. The insulating layer is an insulating ink coated on the surface of the ceramic layer. The projection of each base island on the ceramic layer is located within the projection of the insulating layer and the second metal layer on the ceramic layer.

2. The QFN package structure of claim 1, wherein, The plurality of chips comprises at least one power chip, the plurality of base islands comprises at least one power base island, the power chip is connected to the power base island, and the projection of the power base island on the ceramic layer at least partially overlaps with the projection of the second metal layer on the ceramic layer.

3. The QFN package structure of claim 1, wherein, The plurality of chips comprises at least one power chip and at least one control chip, the plurality of base islands comprises at least one power base island and at least one control base island, the power chip is connected to the power base island, and the control chip is connected to the control base island.

4. The QFN package structure of claim 3, wherein, ​ 5. The QFN package structure of claim 4, wherein, ​ 6. The QFN package structure of claim 4, wherein, ​ 7. The QFN package structure of claim 3, wherein, ​ 8. The QFN package structure of claim 1, wherein, ​

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