Pixel

Abstract

A pixel includes: a first transistor having a gate electrode connected to a first node and connected between a second node and a third node; a second transistor connected between a second node and a first power line to which a first driving power source is supplied and having a gate electrode connected to the second node; a third transistor connected between the data line and the first node, and having a gate electrode electrically connected to the first scan line; a first capacitor connected between the first node and the third transistor; and a light emitting element connected between the third node and a second power line to which the second driving power is supplied.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0025826, filed on February 22, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally pertains to pixels. Background Technology

[0004] With the development of multimedia, the importance of display devices has increased. Therefore, various types of display devices, such as organic light-emitting diodes (“OLED”) and liquid crystal displays (“LCD”), are used.

[0005] Recently, head-mounted display devices (“HMDs”) have been developed. An HMD is a display device worn by a user in the form of glasses or a helmet to achieve virtual reality (“VR”) or augmented reality (“AR”), where the focus is formed at a distance close to the eyes. High-resolution panels are used in HMDs, and therefore, the number of pixels suitable for high-resolution panels is desired.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the background of this disclosure, and therefore may contain information that does not constitute prior art known to those skilled in the art in this country. Utility Model Content

[0007] The implementation provides a pixel with improved efficiency and a display device including the pixel.

[0008] According to an aspect of this disclosure, a pixel is provided, comprising: a first transistor having a gate electrode connected to a first node, the first transistor being connected between a second node and a third node; a second transistor being connected between the second node and a first power line, a first driving power supply being provided to the first power line, the second transistor having a gate electrode connected to the second node; a third transistor being connected between a data line and the first node, the third transistor having a gate electrode electrically connected to a first scan line; a first capacitor being connected between the first node and the third transistor; and a light-emitting element being connected between the third node and the second power line, a second driving power supply being provided to the second power line.

[0009] The pixel may further include: a fourth transistor connected between the fourth node and the first node, the fourth transistor having a gate electrode electrically connected to the second scan line; and a fifth transistor connected between the first power line and the fourth node, the fifth transistor having a gate electrode electrically connected to the emitt control line. A second transistor may be connected between the fourth node and the second node.

[0010] The pixel may also include a sixth transistor connected between the third node and the third power line, the sixth transistor having a gate electrode electrically connected to the third scan line.

[0011] Each of the first, third, and sixth transistors may have a first breakdown voltage, and at least one of the second, fourth, and fifth transistors may have a second breakdown voltage. The second breakdown voltage may be lower than the first breakdown voltage.

[0012] A horizontal cycle can include a first cycle, a second cycle, and a third cycle, defined sequentially. In the first cycle, transistors three through six can be turned on.

[0013] In the second cycle, the fourth and fifth transistors can be turned off, while the third and sixth transistors can remain on.

[0014] In the second cycle, the data voltage supplied to the data line can be transmitted to the first capacitor and the gate electrode of the first transistor through the conducting third transistor.

[0015] In the third cycle, the third, fourth, and sixth transistors can be turned off, and the fifth transistor can be turned on.

[0016] In the third cycle, the drive current can be supplied from the first power line to the light-emitting element through the fifth transistor, the second transistor, and the first transistor, based on the voltage of the gate electrode of the first transistor.

[0017] Each of the first to sixth transistors can be a P-type transistor.

[0018] The pixel may also include a second capacitor connected between the first node and the second node.

[0019] The second transistor can be used as a diode, allowing current to flow from the first electric field line to the second node.

[0020] The pixel may further include: a fourth transistor connected between the second node and the first node, the fourth transistor having a gate electrode connected to the second scan line; and a fifth transistor connected between the first power line and the second transistor, the fifth transistor having a gate electrode electrically connected to the emitt control line. The second transistor may be connected between the fifth transistor and the second node.

[0021] The pixel may also include a sixth transistor connected between the third node and the third power line, the sixth transistor having a gate electrode electrically connected to the third scan line. Each of the first, third, and sixth transistors may have a first breakdown voltage, and at least one of the second, fourth, and fifth transistors may have a second breakdown voltage. The second breakdown voltage may be lower than the first breakdown voltage.

[0022] According to another aspect of this disclosure, a display device is provided comprising pixels connected to a first scan line, a second scan line, a third scan line, a data line, and an emission control line, wherein each pixel comprises: a first transistor having a gate electrode connected to a first node, the first transistor being connected between a second node and a third node; a second transistor being connected between the second node and a first power line, a first driving power supply being provided to the first power line, the second transistor having a gate electrode connected to the second node; a third transistor being connected between one of the data lines and the first node, the third transistor having a gate electrode electrically connected to one of the first scan lines; a first capacitor being connected between the first node and the third transistor; and a light-emitting element being connected between the third node and the second power line, a second driving power supply being provided to the second power line.

[0023] The display device may further include: a fourth transistor connected between the fourth node and the first node, the fourth transistor having a gate electrode electrically connected to one of the second scan lines; and a fifth transistor connected between the first power line and the fourth node, the fifth transistor having a gate electrode electrically connected to one of the transmit control lines. A second transistor may be connected between the fourth node and the second node.

[0024] The display device may further include: a fourth transistor connected between the second node and the first node, the fourth transistor having a gate electrode connected to one of the second scan lines; and a fifth transistor connected between the first power line and the second transistor, the fifth transistor having a gate electrode electrically connected to one of the transmit control lines. The second transistor may be connected between the fifth transistor and the second node.

[0025] The display device may also include a sixth transistor connected between the third node and the third power line, the sixth transistor having a gate electrode electrically connected to one of the third scan lines.

[0026] Each of the first, third, and sixth transistors may have a first breakdown voltage, and at least one of the second, fourth, and fifth transistors may have a second breakdown voltage. The second breakdown voltage may be lower than the first breakdown voltage.

[0027] The display device may also include a second capacitor connected between the first node and the second node. Attached Figure Description

[0028] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0029] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as "between" two elements, it can be the only element between the two elements, or there may be one or more intervening elements. The same reference numerals always denote the same elements.

[0030] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0031] Figure 2 It is shown Figure 1 A block diagram illustrating an implementation of the scan driver and transmit driver.

[0032] Figure 3 It is shown Figure 1 Circuit diagram of an implementation of any of the pixels shown.

[0033] Figure 4 It is shown Figure 3 The timing diagram shows an implementation of the pixel driving method.

[0034] Figures 5 to 7 It shows the pixel in Figure 4 The diagram shows the operations in the cycle.

[0035] Figure 8 It is shown Figure 1 A circuit diagram of another embodiment of one of the pixels shown.

[0036] Figure 9 It is shown Figure 1 A circuit diagram of another embodiment of one of the pixels shown.

[0037] Figure 10 It shows including Figure 1 A block diagram illustrating an embodiment of the display system of the display device shown.

[0038] Figure 11 It is shown Figure 10 The image shows a perspective view of an application example of the display system. Detailed Implementation

[0039] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In this description, only the parts necessary for understanding operation according to the present disclosure are described, and descriptions of other parts are omitted so as not to unnecessarily obscure the subject matter of the disclosure. Furthermore, the present disclosure is not limited to the exemplary embodiments described herein, but can be implemented in various different forms. Rather, the exemplary embodiments described herein are provided to thoroughly and completely describe the disclosure and to fully convey the ideas of the present disclosure to those skilled in the art.

[0040] Throughout this specification, when an element is referred to as “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or indirectly connected or coupled to the other element with one or more intervening elements inserted between them. The technical terminology used herein is for illustrative purposes only and is not intended to limit the implementation. It will be understood that when a component “comprises” an element, unless there is another description to the contrary, it should be understood that the component does not exclude another element, but may also include another element. It will be understood that, for the purposes of this disclosure, “at least one of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more items of X, Y, and Z (e.g., XYZ, XY, YZ, XZ). Similarly, for the purposes of this disclosure, “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more items of X, Y, and Z (e.g., XYZ, XY, YZ, XZ).

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “an,” “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “an” or “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0042] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the “first” element discussed below may also be referred to as the “second” element.

[0043] For ease of description, spatial relative terms such as “below” and “above” may be used herein to describe the relationship between one element and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations described herein and depicted in the accompanying drawings, the spatial relative terms and the structures shown are intended to encompass different orientations of the device in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as “below” or “under” other elements or features will consequently be oriented “above” other elements or features. Thus, the exemplary term “above” can encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0044] Furthermore, embodiments of this disclosure are described herein with reference to schematic diagrams of preferred embodiments (and intermediate structures), thereby allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of the device, and do not limit the scope of this disclosure.

[0045] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0046] refer to Figure 1 The display device 100 according to embodiments of the present disclosure may include a display panel 110, a timing controller 120, a scan driver 130, a data driver 140, a transmit driver 150, and a power supply 160. These components may be implemented as separate integrated circuits, and two or more of these components may be integrated into a single integrated circuit. In embodiments, for example, the scan driver 130 and the transmit driver 150 may be formed and included in the display panel 110.

[0047] The display panel 110 may include pixels PX connected to first scan lines SL11 to SL1n, second scan lines SL21 to SL2n, third scan lines SL31 to SL3n, data lines DL1 to DLm, transmission control lines EL1 to ELn, and power lines PL1 to PL3 (n and m are integers of 2 or greater). In some embodiments, the first scan lines SL11, SL12... and SL1n may be collectively referred to as the first scan line SL1, the second scan lines SL21, SL22... and SL2n may be collectively referred to as the second scan line SL2, the third scan lines SL31, SL32... and SL3n may be collectively referred to as the third scan line SL3, and the transmission control lines EL1, EL2... and ELn may be collectively referred to as the transmission control lines EL. Data lines DL1 to DLm may, for example, include data lines DL1, DL2... and DLm.

[0048] In some implementations, the pixel PXij located on the i-th horizontal line (or pixel row) and the j-th vertical line (or pixel column) (see...) Figure 3 It can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th transmit control line ELi, and the j-th data line DLj (i is an integer of n or less, and j is an integer of m or less).

[0049] When a first scan signal is provided to the first scan lines SL11 to SL1n, pixels PX can be selected on a horizontal line basis. Each pixel PX selected by the first scan signal can provide a data signal from any one of the data lines (DL1 to DLm) connected to it. The pixel PX providing the data signal can generate light with a predetermined brightness corresponding to the voltage of the data signal.

[0050] The scan driver 130 can receive a scan drive signal SCS from the timing controller 120. At least one scan start signal and at least one clock signal for driving the scan driver 130 can be included in the scan drive signal SCS. The scan driver 130 can generate a first scan signal, a scan signal, and a third scan signal simultaneously with the shift scan start signal, corresponding to the clock signal.

[0051] Data driver 140 can receive output data Dout and data drive signal DCS from timing controller 120. Data drive signal DCS may include sampling signals and / or timing signals for driving data driver 140. Data driver 140 can generate a data signal based on data drive signal DCS and output data Dout. In the example, data driver 140 can generate an analog data signal based on the grayscale level of output data Dout. Data driver 140 can generate a horizontal period 1H (see...) Figure 4During this period, the reference power supply voltage and the data signal voltage are sequentially supplied to the data lines DL1 to DLm.

[0052] The transmit driver 150 can receive a transmit drive signal ECS from the timing controller 120. A transmit start signal and a clock signal for driving the transmit driver 150 can be included in the transmit drive signal ECS. The transmit driver 150 can generate a transmit control signal while shifting the transmit start signal in response to the clock signal.

[0053] Timing controller 120 can receive input data Din and control signal CS from the host system via an interface. In this example, timing controller 120 can receive input data Din and control signal CS from at least one of a graphics processing unit (“GPU”), a central processing unit (“CPU”), and an application processor (“AP”) included in the host system. Various signals, including clock signals, can be included in the control signal CS.

[0054] The timing controller 120 can generate a scan drive signal SCS, a data drive signal DCS, and a transmit drive signal ECS based on the control signal CS. The scan drive signal SCS, the data drive signal DCS, and the transmit drive signal ECS can be provided to the scan driver 130, the data driver 140, and the transmit driver 150, respectively.

[0055] The timing controller 120 can readjust the input data Din to a specification suitable for the display device 100. Furthermore, the timing controller 120 can generate output data Dout by correcting the input data Din and provide the output data Dout to the data driver 140.

[0056] Power supply 160 can generate various power supplies for driving display device 100. In this example, power supply 160 can generate a first driving power supply VDD, a second driving power supply VSS, and an initialization power supply VINT.

[0057] The first driving power supply VDD can be a power supply that provides driving current to pixel PX. The second driving power supply VSS can be a power supply that provides driving current from pixel PX. During the period when pixel PX is set to the emission state, the first driving power supply VDD can be set to a voltage higher than that of the second driving power supply VSS.

[0058] The initialization power supply VINT can be used to initialize the light-emitting elements LD included in each of the pixels PX (see [link to initialization power supply]). Figure 3The voltage of the first electrode (or anode electrode) of the light-emitting element (LD). The initialization power supply VINT may have the voltage value at which the LD is turned on when the initialization power supply VINT is supplied to the first electrode of the LD. In an embodiment, for example, the initialization power supply VINT may be set to ground potential.

[0059] The first driving power supply VDD, the second driving power supply VSS, and the initialization power supply VINT generated by the power supply 160 can be provided to the first power line PL1, the second power line PL2, and the third power line PL3, respectively. The first power line PL1, the second power line PL2, and the third power line PL3 can be commonly connected to the pixel PX, but the embodiments of this disclosure are not limited thereto.

[0060] In one embodiment, the first power line PL1 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels PX. In another embodiment, the second power line PL2 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels PX. In yet another embodiment, the third power line PL3 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels PX. That is, in the embodiments of this disclosure, each pixel PX can be connected to any one of the multiple power lines of the first power line PL1, any one of the multiple power lines of the second power line PL2, and any one of the multiple power lines of the third power line PL3.

[0061] Figure 2 It is shown Figure 1 A block diagram illustrating an implementation of the scan driver and transmit driver.

[0062] refer to Figure 2 The scan driver 130 may include a first scan driver 131, a second scan driver 132 and a third scan driver 133.

[0063] The first scan driver 131 can receive a first scan start signal FLM1 and generate a first scan signal while shifting the first scan start signal FLM1 in response to a clock signal. The first scan driver 131 can sequentially provide the first scan signal to the first scan lines SL11 to SL1n.

[0064] The second scan driver 132 can receive the second scan start signal FLM2 and generate a second scan signal while shifting the second scan start signal FLM2 in response to a clock signal. The second scan driver 132 can sequentially provide the second scan signals to the second scan lines SL21 to SL2n.

[0065] The third scan driver 133 can receive the third scan start signal FLM3 and generate the third scan signal while shifting the third scan start signal FLM3 in response to the clock signal. The third scan driver 133 can sequentially provide the third scan signal to the third scan lines SL31 to SL3n.

[0066] Each of the first scan signal, the second scan signal, and the third scan signal can be set as a gate turn-on voltage, such that the transistors included in the pixel PX can be turned on.

[0067] In the example, the first to third scan signals, which have a low level, can be provided as gate turn-on voltages to the P-type transistor. The first to third scan signals, which have a high level, can be provided as gate turn-on voltages to the N-type transistor. The transistor provided with the first, second, or third scan signal can be turned on in response to the first, second, or third scan signal.

[0068] Subsequently, providing a first scan signal, a second scan signal, or a third scan signal for the first scan lines SL11 to SL1n, the second scan lines SL21 to SL2n, or the third scan lines SL31 to SL3n can mean providing a gate on-voltage. Conversely, not providing a first scan signal, a second scan signal, or a third scan signal for the first scan lines SL11 to SL1n, the second scan lines SL21 to SL2n, or the third scan lines SL31 to SL3n can mean providing a gate off-voltage.

[0069] exist Figure 2 The diagram shows a first scan driver 131, a second scan driver 132, and a third scan driver 133 connected to first scan lines SL11 to SL1n, second scan lines SL21 to SL2n, and third scan lines SL31 to SL3n, respectively. However, this disclosure is not limited thereto. In another example, at least two of the first scan lines SL11 to SL1n, second scan lines SL21 to SL2n, and third scan lines SL31 to SL3n may be driven by a single scan driver.

[0070] The transmit driver 150 can receive a transmit start signal EFLM and generate a transmit control signal while shifting the transmit start signal EFLM in response to a clock signal. The transmit driver 150 can sequentially provide transmit control signals to transmit control lines EL1 to ELn. The transmit control signals can be set as gate on-voltages, enabling the transistors included in the pixel PX to conduct.

[0071] In the example, a low-level emit control signal can be provided as a gate on-state voltage to a P-type transistor, and a high-level emit control signal can be provided as a gate on-state voltage to an N-type transistor. The transistor with the emit control signal provided can turn on in response to the emit control signal. Subsequently, for emit control lines EL1 to ELn, providing an emit control signal can mean providing a gate on-state voltage. Furthermore, for emit control lines EL1 to ELn, not providing an emit control signal can mean providing a gate off-state voltage.

[0072] Figure 3 It is shown Figure 1 Circuit diagrams of implementations of any of the pixels shown. Figure 3 The example shown is a pixel PXij located on the i-th horizontal line and the j-th vertical line.

[0073] refer to Figure 3 According to embodiments of this disclosure, pixel PXij can be connected to corresponding signal lines SL1i, SL2i, SL3i, ELi, and DLj. In one embodiment, for example, pixel PXij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th transmit control line ELi, and the j-th data line DLj. In another embodiment, pixel PXij can also be connected to the first power line PL1, the second power line PL2, and the third power line PL3.

[0074] Pixel PXij may include a light-emitting element (LD) and a pixel circuit for controlling the amount of current supplied to the light-emitting element (LD).

[0075] The light-emitting element (LD) can be connected between a first electric field line PL1 and a second electric field line PL2. In the example, the first electrode (or anode electrode) of the LD can be electrically connected to the first electric field line PL1 via a third node N3, a first transistor M1, a second node N2, a second transistor M2, a fourth node N4, and a fifth transistor M5. The second electrode (or cathode electrode) of the LD can be electrically connected to the second electric field line PL2. The LD can generate light with a predetermined brightness corresponding to the amount of current supplied from the first electric field line PL1 to the second electric field line PL2 via the pixel circuit.

[0076] The light-emitting element (LD) can be selected as an organic light-emitting diode (OLED). Alternatively, the LD can be selected as an inorganic light-emitting diode such as a micro LED (light-emitting diode) or a quantum dot light-emitting diode. Furthermore, the LD can be a device configured with a combination of organic and inorganic materials. Figure 3The diagram shows a pixel PXij comprising a single light-emitting element LD. However, this disclosure is not limited thereto. In another example, a pixel PXij may comprise multiple light-emitting elements LD, and the multiple light-emitting elements LD may be connected in series, in parallel, or in a series / parallel connection.

[0077] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a first capacitor C1.

[0078] Each of the first transistors M1 to M6 can be a P-type transistor. Each of the first transistors M1 to M6 can be a metal-oxide-semiconductor field-effect transistor (“MOSFET”). In an embodiment, for example, when the first transistor M1 is a P-type MOSFET, the light-emitting element LD can be connected to the second electrode (or drain electrode) of the first transistor M1, such that the pixel circuit is almost unaffected by the degradation of the light-emitting element LD. However, this is merely illustrative, and the present disclosure is not limited thereto. For another example, at least one of the first transistors M1 to M6 can be replaced with an N-type transistor.

[0079] In the implementation, the first transistor M1 to the sixth transistor M6 may include amorphous silicon semiconductor, single-crystal silicon semiconductor, polycrystalline silicon semiconductor, oxide semiconductor, etc.

[0080] A first transistor M1 (or driving transistor) can be connected between a second node N2 and a third node N3 (i.e., the first electrode of the light-emitting element LD). The term "connection" can include the meaning of "electrical connection". The first electrode (or source electrode) of the first transistor M1 can be electrically connected to the second node N2, and the second electrode (or drain electrode) of the first transistor M1 can be connected to the third node N3. The gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can be turned on according to the voltage level of the first node N1.

[0081] The second transistor M2 can be connected between the fourth node N4 and the second node N2. The gate electrode of the second transistor M2 can be electrically connected to the second node N2. The second transistor M2 can function as a diode, allowing current to flow from the first power line PL1 to the second node N2 through the fifth transistor M5. In an embodiment, for example, the second transistor M2 can be diode-connected, allowing current to flow from the fourth node N4 to the second node N2.

[0082] Therefore, the second transistor M2 is connected to the first electrode of the first transistor M1, such that a portion of the voltage at the gate electrode of the first transistor M1 can be applied to the opposite ends of the load of the first transistor M1. Therefore, the equivalent transconductance G of the first transistor M1...m It can be less affected by intrinsic transconductance g m The impact of equivalent transconductance G. m It can be determined as shown in Equation 1.

[0083] Equation 1

[0084]

[0085] V in This can represent the input voltage of the gate electrode of the first transistor M1, and I D This can represent the drain-source current of the first transistor M1. R dio This can represent the resistance of the second transistor M2, which is used as a diode.

[0086] As shown in Equation 2, the intrinsic transconductance g m This can be determined through small-signal analysis, and therefore, with R... dio As the threshold voltage increases, the current change may become less sensitive to changes in voltage.

[0087] Equation 2

[0088]

[0089] μ P It can represent electric field mobility, C ox W / L can represent the capacity of the gate insulating layer per unit area, and W / L can represent the width / length ratio of the channel of the first transistor M1.

[0090] Therefore, by connecting the second transistor M2, which functions as a diode with high resistance at extremely low currents, to the first electrode of the first transistor M1, source degradation of the first transistor M1 can be achieved. Source degradation can refer to the phenomenon that the relationship between the input voltage (or the gate voltage of the first transistor M1) and the output current (or the current flowing through the first transistor M1 between the second node N2 and the third node N3) is linearized by a resistive element connected to the first electrode (or source electrode) of the first transistor M1, unaffected by other factors such as degradation. The voltage range to be applied to the gate electrode of the first transistor M1 can be relatively widened according to source degradation, and therefore, the voltage range of the data signal can also be widened.

[0091] In one implementation, for example, the second transistor M2 can be used to induce negative feedback on the threshold voltage variation of the first transistor M1. This negative feedback can compensate for the threshold voltage distribution of the first transistor M1. Therefore, compared to the case where the second transistor M2 is not present, the voltage range of the data signal can be set to be sufficiently wide.

[0092] The third transistor M3 can be connected between the j-th data line DLj and the first node N1. Furthermore, the gate electrode of the third transistor M3 can be electrically connected to the i-th first scan line SL1i. The third transistor M3 can be turned on when the first scan signal GW is provided to the i-th first scan line SL1i, so as to electrically connect the j-th data line DLj and the first node N1 to each other.

[0093] A fourth transistor M4 can be connected between the first node N1 and the fourth node N4. Furthermore, the gate electrode of the fourth transistor M4 can be electrically connected to the i-th second scan line SL2i. The fourth transistor M4 can be turned on when the second scan signal GI is provided to the i-th second scan line SL2i, thereby electrically connecting the first node N1 and the fourth node N4 to each other. The gate electrode of the first transistor M1 (i.e., the first node N1) and the first electrode of the first transistor M1 (i.e., the fourth node N4 connected to the second node N2 via the second transistor M2) can be electrically connected to each other. Therefore, the first transistor M1 can function as a diode depending on the operation of the fourth transistor M4.

[0094] The fifth transistor M5 can be connected between the first power line PL1 and the fourth node N4. Furthermore, the gate electrode of the fifth transistor M5 can be electrically connected to the i-th transmit control line ELi. The fifth transistor M5 can be turned on when the transmit control signal EM is provided to the i-th transmit control line ELi, and can be turned off when the transmit control signal EM is not provided. When the fifth transistor M5 is turned off, the first drive power supply VDD and the second transistor M2 can be electrically isolated from each other.

[0095] The sixth transistor M6 can be connected between the third node N3 and the third power line PL3. The first electrode of the sixth transistor M6 can be electrically connected to the third node N3 (i.e., the first electrode of the light-emitting element LD), and the second electrode of the sixth transistor M6 can be electrically connected to the third power line PL3. Furthermore, the gate electrode of the sixth transistor M6 can be electrically connected to the i-th third scan line SL3i. The sixth transistor M6 can be turned on when the third scan signal GB is provided to the i-th third scan line SL3i. When the sixth transistor M6 is turned on, the voltage of the initialization power supply VINT can be provided to the third node N3. In this embodiment, the voltage of the initialization power supply VINT can be supplied by the power supply 160 (see [link to embodiment]). Figure 1 In other embodiments, the voltage for initialization power supply VINT may be provided by an external device of display device 100.

[0096] In one embodiment, each of the first transistor M1, the third transistor M3, and the sixth transistor M6 may be a transistor having the same level of a first breakdown voltage. In another embodiment, for example, the first breakdown voltage may have a relatively high voltage level. On the other hand, at least one of the second transistor M2, the fourth transistor M4, and the fifth transistor M5 may be a transistor having the same level of a second breakdown voltage. The second breakdown voltage may have a lower level than the first breakdown voltage. "Breakdown voltage" may refer to the voltage at which current begins to flow through the transistor even in the off state due to excessively high off-state voltage caused by external environmental factors (such as a momentary short circuit or electrostatic discharge).

[0097] In the example, when a first breakdown voltage or higher is applied to each of the gate-source electrode, gate-drain electrode, and gate-body electrode, the operational reliability of each of the first transistor M1, the third transistor M3, and the sixth transistor M6 may deteriorate. In an implementation, for example, the first breakdown voltage may be 6V, 8V, or 10V. On the other hand, when a second breakdown voltage or higher is applied to each of the gate-source electrode, gate-drain electrode, and gate-body electrode, the operational reliability of at least one of the second transistor M2, the fourth transistor M4, and the fifth transistor M5 may deteriorate. In an implementation, for example, the second breakdown voltage may be 3.3V or 5V.

[0098] Therefore, by combining a transistor with a first breakdown voltage with a transistor with a second breakdown voltage lower than the first breakdown voltage to implement the pixel circuit, the first transistor M1 can be designed to have the largest size within the region of pixel PXij. This effectively improves brightness and / or short-distance uniformity between pixels PX. Furthermore, the second transistor M2 is implemented as a transistor with the second breakdown voltage, thereby ensuring a driving voltage margin corresponding to the reduced threshold voltage.

[0099] A first capacitor C1 (or a connecting capacitor) can be connected between the first node N1 and the third transistor M3. The first electrode of the first capacitor C1 can be electrically connected to the first electrode of the third transistor M3, and the second electrode of the first capacitor C1 can be electrically connected to the first node N1. The first capacitor C1 can change the voltage of the first node N1 corresponding to the voltage supplied from the j-th data line DLj through the third transistor M3. (See later...) Figure 6 Describe the first capacitor C1 in detail.

[0100] Figure 4 It is shown Figure 3 The timing diagram shows an implementation of the pixel driving method.

[0101] refer to Figure 3 and Figure 4Data signals can be provided to pixel PXij within a horizontal period 1H (or a specific horizontal period). The horizontal period 1H can be divided into a first period T1, a second period T2, and a third period T3, which are defined sequentially.

[0102] The first scan driver 131 can provide a first scan signal GW with a gate on-voltage to the i-th first scan line SL1i in the first period T1 and the second period T2.

[0103] The second scan driver 132 can provide a second scan signal GI with a gate on-voltage to the i-th second scan line SL2i during the first period T1. In an embodiment, the first period T1 may overlap with a predetermined horizontal period (e.g., the period for providing data signals to pixels located on the (i-1)-th horizontal line).

[0104] The third scan driver 133 can provide a third scan signal GB with a gate on-voltage to the i-th third scan line SL3i during the first period T1 and the second period T2. In an embodiment, the third period T3 can overlap with the next horizontal period (e.g., the period during which data signals are provided to pixels located on the (i+1)-th horizontal line).

[0105] Transmit driver 150 (see) Figure 1 The emitter driver 150 can apply the emitter control signal EM with a gate on voltage to the i-th emitter control line ELi during the first cycle T1 and the third cycle T3. In other words, the emitter driver 150 can disable the emitter control signal EM to a gate off voltage during the second cycle T2.

[0106] Data drive 140 (see Figure 1 The voltage Vdata(i) of the data signal can be provided to the j-th data line DLj in the second period T2. The voltage Vdata(i) of the data signal can be set to a predetermined voltage within the voltage range of the data signal, corresponding to the gray level.

[0107] The data driver 140 can provide a reference power supply VREF to the j-th data line DLj in the first cycle T1 and the third cycle T3. The reference power supply VREF is the voltage between the first drive power supply VDD and the second drive power supply VSS, and can be set to a specific voltage within the voltage range of the data signal.

[0108] In some implementations, the first period T1 may be an initialization period. In an example, during the first period T1, the voltage of the reference power supply VREF may be provided to the j-th data line DLj. During the first period T1, the voltage of the reference power supply VREF may be provided to the first node N1 included in pixel PXij, and the voltage of the initialization power supply VINT may be provided to the third node N3 included in pixel PXij. During the first period T1, the first node N1 may be initialized using the voltage of the reference power supply VREF, and the third node N3 may be initialized using the voltage of the initialization power supply VINT.

[0109] The second period T2 can be a data programming period. In the example, the second period T2 can be the period in which the voltage Vdata(i) of the data signal from the j-th data line DLj is provided to the pixel PXij. In the second period T2, the voltage corresponding to the data signal can be provided to the first node N1.

[0110] The third period T3 can be an emission period. In the example, during the third period T3, drive current can be supplied from the first drive power supply VDD to the light-emitting element LD via the fifth transistor M5, the second transistor M2, and the first transistor M1. During the third period T3, the first transistor M1 can control the amount of current flowing from the first drive power supply VDD through the fifth transistor M5, the second transistor M2, and the light-emitting element LD to the second drive power supply VSS based on the voltage of the first node N1. During the third period T3, the light-emitting element LD can emit light with a brightness corresponding to the amount of current.

[0111] Despite Figure 4 Not shown, but during the transition period between the first period T1 and the third period T3, the timing of the output (or transmission) of the first scan signal GW, the second scan signal GI, the third scan signal GB, the transmit control signal EM, and the data signal can be controlled to not overlap with each other.

[0112] Figures 5 to 7 It shows the pixel in Figure 4 The diagram shows the operations in the cycle.

[0113] refer to Figure 5 In the first cycle T1, transistors M3 through M6 can be turned on.

[0114] In the first cycle T1, the transmit control signal EM can be provided to the i-th transmit control line ELi. When the transmit control signal EM is provided to the i-th transmit control line ELi, the fifth transistor M5 can be turned on. When the fifth transistor M5 is turned on, the first power line PL1, which is supplied with the first drive power VDD, can be electrically connected to the fourth node N4.

[0115] In the first cycle T1, the third scan signal GB can be provided to the i-th third scan line SL3i. When the third scan signal GB is provided to the i-th third scan line SL3i, the sixth transistor M6 can be turned on. When the sixth transistor M6 is turned on, the voltage of the initialization power supply VINT can be provided to the third node N3. The anode electrode of the light-emitting element LD can be initialized by the voltage of the initialization power supply VINT. The initialization power supply VINT can be set to the voltage at which the light-emitting element LD does not emit light, and therefore, the light-emitting element LD can be set to a non-emitting state.

[0116] In the first cycle T1, the first scan signal GW can be provided to the i-th first scan line SL1i. When the first scan signal GW is provided to the i-th first scan line SL1i, the third transistor M3 can be turned on, and therefore, the voltage of the reference power supply VREF from the j-th data line DLj can be provided to the first node N1. The voltage of the first node N1 can be initialized to the voltage of the reference power supply VREF, regardless of the voltage provided in the previous cycle (or the previous frame cycle). Furthermore, when the third transistor M3 is turned on, the voltage of the reference power supply VREF from the j-th data line DLj can be provided to the first electrode of the first capacitor C1.

[0117] In the first cycle T1, when the second scan signal GI is provided to the i-th second scan line SL2i, the fourth transistor M4 can be turned on. As described above, since the fifth transistor M5 is turned on in the first cycle T1, the voltage of the first drive power supply VDD can be applied to the first node N1.

[0118] Therefore, in the first cycle T1, the voltage corresponding to the voltage difference between the reference power supply VREF and the first node N1 can be stored in the first capacitor C1. Furthermore, in the first cycle T1, the voltage of the initialization power supply VINT can be applied to the third node N3 through the sixth transistor M6.

[0119] refer to Figure 6 In the second cycle T2, the fourth transistor M4 and the fifth transistor M5 can be turned off, while the third transistor M3 and the sixth transistor M6 can remain on.

[0120] In the second cycle T2, as the transmission control signal EM is paused from being supplied to the i-th transmission control line ELi, the fifth transistor M5 can be turned off.

[0121] In the second cycle T2, the conduction state of the third transistor M3 can be maintained by the first scan signal GW provided to the i-th first scan line SL1i, and the conduction state of the sixth transistor M6 can be maintained by the third scan signal GB provided to the i-th third scan line SL3i.

[0122] In the second cycle T2, as the second scan signal GI is paused to be supplied to the i-th second scan line SL2i, the fourth transistor M4 can be turned off.

[0123] In the second cycle T2, the voltage Vdata(i) of the data signal can be provided to the j-th data line DLj. The voltage Vdata(i) of the data signal provided to the j-th data line DLj can be provided to the first electrode of the first capacitor C1 via the third transistor M3.

[0124] When the voltage Vdata(i) of the data signal is supplied to the first electrode of the first capacitor C1, the voltage of the first electrode of the first capacitor C1 can be changed from the voltage of the reference power supply VREF to the voltage Vdata(i) of the data signal. The voltage of the first node N1 can also be changed through the coupling of the first capacitor C1.

[0125] The voltage change at the first node N1 can be determined based on the capacitance of the first capacitor C1. The voltage Vdata(i) of the data signal can be supplied to the first node N1 through the first capacitor C1. Since the first capacitor C1 and the second capacitor C2 (see...) Figure 8 Due to the charge distribution effect, as the capacitance of the first capacitor C1 decreases, the voltage range of the data signal can be set to be wider. Optionally, the voltage range of the data signal can be set to be wider as the capacitance of the second capacitor C2 increases.

[0126] Therefore, the voltage Vdata(i) of the data signal is transmitted to the gate electrode of the first transistor M1 through the first capacitor C1, so that the voltage range of the data signal can be set to be sufficiently wide. Therefore, according to the embodiments of this disclosure, various gray levels can be easily implemented using a wider data signal voltage range.

[0127] refer to Figure 7 In the third cycle T3, the third transistor M3, the fourth transistor M4 and the sixth transistor M6 can be turned off, and the fifth transistor M5 can be turned on.

[0128] In the third cycle T3, as the transmit control signal EM is provided to the i-th transmit control line ELi, the fifth transistor M5 can be turned on. On the other hand, as the supply of the third scan signal GB to the i-th third scan line SL3i is paused, the sixth transistor M6 can be turned off.

[0129] The first transistor M1 can control the amount of drive current supplied from the first drive power supply VDD to the second drive power supply VSS via the fifth transistor M5, the second transistor M2, and the light-emitting element LD, corresponding to the voltage of the first node N1. In the third cycle T3, the light-emitting element LD can generate light with a brightness corresponding to the amount of drive current supplied from the first transistor M1.

[0130] Specifically, the amount of current supplied from the first transistor M1 to the light-emitting element LD in the third cycle T3 can be determined as shown in Equation 3.

[0131] Equation 3

[0132]

[0133] μ p It can represent electric field mobility, C ox W / L can represent the capacitance of the gate insulating layer per unit area, and W / L can represent the width / length ratio of the channel of the first transistor M1. d VDD can represent the current supplied to the light-emitting element LD, and VDD can represent the voltage of the first driving power supply VDD. th1 V can represent the threshold voltage of the first transistor M1. th2 This can represent the threshold voltage of the second transistor M2, and V dsta2 This can represent the saturation voltage of the second transistor M2. V data It can represent the voltage of the data signal input to the gate electrode of the first transistor M1, and VREF can represent the voltage of the reference power supply VREF. m1 This can represent the intrinsic transconductance of the first transistor M1.

[0134] C1 can represent the capacitance of the first capacitor C1, and C2 can represent the capacitance of the second capacitor C2 (see [link to relevant documentation]). Figure 8 The capacitance of the parasitic capacitor between the first node N1 and the second node N2 of the first transistor M1. Optionally, as... Figure 8 As shown in the diagram, C2 can represent the capacitance of the auxiliary capacitor.

[0135] Therefore, the current supplied from the first transistor M1 to the light-emitting element LD can be a value obtained by compensating for the threshold voltage of the first transistor M1 and the threshold voltage of the light-emitting element LD.

[0136] Figure 8 It is shown Figure 1 A circuit diagram of another embodiment of one of the pixels shown.

[0137] refer to Figure 3 and Figure 8In addition to the second capacitor C2, pixel PXij' can be connected with... Figure 3 The pixels PXij shown are essentially the same. Figure 8 In the middle, omission and Figure 3 Related overlapping descriptions, and will mainly describe the parts that differ from the embodiments described above.

[0138] The second capacitor C2 can be connected between the first node N1 and the second node N2. The first electrode of the second capacitor C2 can be electrically connected to the gate electrode of the first transistor M1, and the second electrode of the second capacitor C2 can be electrically connected to the first electrode (or source electrode) of the first transistor M1. The second capacitor C2 can store the voltage provided between the first node N1 and the second node N2.

[0139] Furthermore, when the voltage Vdata(i) of the data signal is supplied to the first electrode of the first capacitor C1 during the second cycle T2, the voltage of the first electrode of the first capacitor C1 can be changed from the voltage of the reference power supply VREF to the voltage Vdata(i) of the data signal. Additionally, the voltage change value of the first node N1 can be determined based on the capacitance ratio between the first capacitor C1 and the second capacitor C2.

[0140] In the example, the voltage change value of the first node N1 can be determined by multiplying the voltage change value of the first electrode of the first capacitor C1 by C1 / (C1+C2). The capacitance of the second capacitor C2 can be smaller than the capacitance of the first capacitor C1. Therefore, the second capacitor C2 is connected between the first node N1 and the second node N2, thereby allowing the voltage range of the data signal to be set more precisely or adaptively in some embodiments.

[0141] Figure 9 It is shown Figure 1 A circuit diagram of another embodiment of one of the pixels shown.

[0142] refer to Figure 9 The pixel PXij may include a first transistor M1, a third transistor M3, a fifth transistor M5, a sixth transistor M6, and a light-emitting element LD.

[0143] The first transistor M1, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the light-emitting element LD can be essentially connected with... Figure 3 The pixels PXij shown are the same. Figure 9 In the middle, omission and Figure 3 Related overlapping descriptions, and will mainly describe the parts that differ from the embodiments described above.

[0144] refer to Figure 9Pixel PXij” can be connected to the corresponding signal lines SL1i, SL2i, SL3i, ELi, and DLj. In an embodiment, for example, pixel PXij” can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th transmit control line ELi, and the j-th data line DLj. In an embodiment, pixel PXij” can also be connected to the first power line PL1, the second power line PL2, and the third power line PL3.

[0145] "Pixel PXij" may include a light-emitting element (LD) and a pixel circuit for controlling the amount of current supplied to the light-emitting element (LD).

[0146] The fourth transistor M4' can be connected between the first node N1 and the second node N2'. Furthermore, the gate electrode of the fourth transistor M4' can be electrically connected to the i-th second scan line SL2i. The fourth transistor M4' can be turned on when the second scan signal GI is provided to the i-th second scan line SL2i, thereby electrically connecting the first node N1 and the second node N2' to each other. In this case, the gate electrode of the first transistor M1 can be electrically connected to the second node N2'. Therefore, the first transistor M1 can function as a diode depending on the operation of the fourth transistor M4'.

[0147] The second transistor M2' can be connected between the fifth transistor M5 and the second node N2'. Furthermore, the gate electrode of the second transistor M2' can be electrically connected to the second node N2'. The second transistor M2' can function as a diode, allowing current flowing from the first power line PL1 through the fifth transistor M5 to flow through the second node N2'. In some embodiments, for example, the gate electrode of the second transistor M2' can be electrically connected to its drain electrode to function as a diode.

[0148] Apart from the fourth transistor M4' being connected to the second node N2', the operation of the fourth transistor M4' in the horizontal period (1H) can be essentially the same as... Figure 3 The fourth transistor M4 shown operates in the same manner during the horizontal cycle.

[0149] Figure 10 It shows including Figure 1 A block diagram illustrating an embodiment of the display system of the display device shown.

[0150] refer to Figure 10 The display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220.

[0151] The processor 1100 can perform various tasks and calculations. In implementations, the processor 1100 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 via a bus system to control the components of the display system 1000.

[0152] exist Figure 10 The diagram shows a display system 1000 including a first display device 1210 and a second display device 1220. A processor 1100 can be connected to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0153] Through the first channel CH1, the processor 1100 can send the first input data Din1 and the first control signal CS1 to the first display device 1210. The first display device 1210 can display an image based on the first input data Din1 and the first control signal CS1. The first display device 1210 can be connected to a reference... Figure 1 The display device 100 described is configured identically. The first input data Din1 and the first control signal CS1 can respectively serve as... Figure 1 The input data Din and control signal CS shown are provided.

[0154] Through the second channel CH2, the processor 1100 can send the second input data Din2 and the second control signal CS2 to the second display device 1220. The second display device 1220 can display an image based on the second input data Din2 and the second control signal CS2. The second display device 1220 can be connected to a reference... Figure 1 The display device 100 described is configured identically. The second input data Din2 and the second control signal CS2 can respectively serve as... Figure 1 The input data Din and control signal CS shown are provided.

[0155] Display system 1000 may include a computing system for providing image display functionality, such as a portable computer, mobile phone, smartphone, tablet PC (“PC”), smartwatch, watch phone, portable multimedia player (“PMP”), navigation system, or ultra-mobile computer (“UMPC”). Furthermore, display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (“MR”) device, and an augmented reality (AR) device.

[0156] Figure 11 It is shown Figure 10 The image shows a perspective view of an application example of the display system.

[0157] refer to Figure 11 , Figure 10 The display system 1000 shown can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0158] The head-mounted display device 2000 may include a headband 2100 and a display device housing 2200. The headband 2100 may be connected to the display device housing 2200. The headband 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to a user's head. The horizontal strap may be configured to surround the sides of the user's head, and the vertical strap may be configured to surround the top of the user's head. However, the implementation is not limited to this. As another example, the headband 2100 may be implemented in the form of an eyeglass frame, a helmet, etc.

[0159] The display device housing 2200 can accommodate Figure 10 The first display device 1210 and the second display device 1220 are shown. The display device housing 2200 can also accommodate... Figure 10 The processor 1100 shown is shown.

[0160] In the pixels and display devices including pixels according to embodiments of the present disclosure, a second transistor M2 or M2', which functions as a diode, is connected to the first electrode of the first transistor M1, thereby compensating for the threshold voltage distribution of the first transistor M1 through source degradation. Therefore, compared to the characteristics of the first transistor M1, the first transistor M1 can have a wider voltage range for the data signal. Furthermore, the voltage Vdata(i) of the data signal is transmitted to the gate electrode of the first transistor M1 through the first capacitor C1, thereby further widening the voltage range of the data signal. Therefore, according to embodiments of the present disclosure, various grayscale levels can be easily implemented using a wider data signal voltage range.

[0161] According to this disclosure, a pixel with improved efficiency and a display device including the pixel can be provided.

[0162] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art at the time of filing this application, unless specifically stated otherwise, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A pixel, characterized in that, include: A first transistor has a gate electrode connected to a first node, and the first transistor is connected between a second node and a third node; A second transistor is connected between the second node and the first power line, a first drive power supply is provided to the first power line, and the second transistor has a gate electrode connected to the second node. A third transistor is connected between the data line and the first node, and the third transistor has a gate electrode electrically connected to the first scan line; A first capacitor is connected between the first node and the third transistor; as well as A light-emitting element is connected between the third node and the second power line, and a second driving power supply is provided to the second power line.

2. The pixel according to claim 1, characterized in that, Also includes: A fourth transistor is connected between the fourth node and the first node, the fourth transistor having a gate electrode electrically connected to the second scan line; A fifth transistor is connected between the first power line and the fourth node, and the fifth transistor has a gate electrode electrically connected to the emitter control line; as well as A sixth transistor, connected between the third node and the third power line, has a gate electrode electrically connected to the third scan line. The second transistor is connected between the fourth node and the second node.

3. The pixel according to claim 2, characterized in that, Each of the first transistor, the third transistor, and the sixth transistor has a first breakdown voltage, and at least one of the second transistor, the fourth transistor, and the fifth transistor has a second breakdown voltage. Wherein, the second breakdown voltage is lower than the first breakdown voltage.

4. The pixel according to claim 2, characterized in that, A horizontal cycle comprises a first cycle, a second cycle, and a third cycle, defined sequentially. During the first cycle, the third transistor to the sixth transistor are turned on.

5. The pixel according to claim 4, characterized in that, During the second cycle, the fourth and fifth transistors are off, while the third and sixth transistors remain on. The data voltage supplied to the data line is transmitted to the first capacitor and the gate electrode of the first transistor through the turned-on third transistor.

6. The pixel according to claim 4, characterized in that, In the third cycle, the third transistor, the fourth transistor, and the sixth transistor are off, and the fifth transistor is on. The driving current is supplied from the first power line to the light-emitting element through the fifth transistor, the second transistor, and the first transistor, according to the voltage of the gate electrode of the first transistor.

7. The pixel according to claim 2, characterized in that, It also includes a second capacitor connected between the first node and the second node.

8. The pixel according to claim 1, characterized in that, The second transistor functions as a diode, allowing current to flow from the first power line to the second node.

9. The pixel according to claim 1, characterized in that, Also includes: A fourth transistor is connected between the second node and the first node, the fourth transistor having a gate electrode connected to the second scan line; as well as A fifth transistor, connected between the first power line and the second transistor, has a gate electrode electrically connected to the emitter control line. The second transistor is connected between the fifth transistor and the second node.

10. The pixel according to claim 9, characterized in that, It also includes a sixth transistor connected between the third node and the third power line, the sixth transistor having a gate electrode electrically connected to the third scan line. Wherein, each of the first transistor, the third transistor, and the sixth transistor has a first breakdown voltage, and at least one of the second transistor, the fourth transistor, and the fifth transistor has a second breakdown voltage, and Wherein, the second breakdown voltage is lower than the first breakdown voltage.

Images