Semiconductor device

Abstract

A semiconductor device (1C) is provided with a transistor (10A) that is formed in a first region (A1A) of a semiconductor layer (40) and a transistor (20A) that is formed in a second region (A2A) that is adjacent to the first region (A1A) of the semiconductor layer (40) in plan view, the first region (A1A) and the second region (A2A) being one or the other that bisects the semiconductor layer (40) in area in plan view, and the first region (A1A) and the second region (A2A) being one of the first region (A1A) and the second region (A2A) being one of the second region (A2A) and the second region (A2A) being one of the first region (A1A) and the second region (A2A). In a plan view, the first drain pad (151A) and the second drain pad (161A) are arranged in a direction orthogonal to a boundary line (90C) between the first region and the second region, and the midpoint of a line segment connecting the center of the first drain pad (151A) and the center of the second drain pad (161A) is positioned on the boundary line (90C). The first gate pad (119A) and the second gate pad (129A) are arranged in a direction orthogonal to the boundary line (90C), and the midpoint of a line segment connecting the center of the first gate pad (119A) and the center of the second gate pad (129A) is located on the boundary line (90C).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to chip-scale packaged semiconductor devices. Background Technology

[0002] Vertical MOS transistors with a dual structure are used to prevent conduction before lithium-ion batteries become overcharged or over-discharged. In such dual-structure vertical MOS transistors, since the current conducting during charging and discharging is relatively large, reducing the on-resistance in the conducting state is of particular importance.

[0003] However, during the charging process, which begins when the lithium-ion battery becomes over-discharged due to the natural passage of time, it is desirable to initiate charging slowly with a relatively small current flow for safe battery use. Therefore, it is convenient in battery protection circuits to include a path for a relatively small current flow in a vertically oriented MOS transistor with a dual structure.

[0004] (Existing technical literature)

[0005] (Patent Documents)

[0006] Patent Document 1: Japanese Patent Application Publication No. 2021-005732A Utility Model Content

[0007] The problem to be solved by utility models

[0008] However, in a dual-structure vertical MOS transistor, adding an additional path within a limited device area will hinder the conduction of the original charging and discharging current.

[0009] Methods for solving problems

[0010] To address the aforementioned issues, one aspect of this disclosure relates to a semiconductor device that is a chip-scale packaged semiconductor device capable of being mounted face-down. This semiconductor device includes: a semiconductor substrate; a low-concentration impurity layer formed on the semiconductor substrate; a first vertical MOS transistor formed in a first region of the semiconductor layer when the semiconductor substrate and the low-concentration impurity layer are used together as a semiconductor layer; a second vertical MOS transistor formed in a second region, the second region being a region adjacent to the first region in a plan view of the semiconductor layer; and a first source pad group consisting of a plurality of first source pads formed in the first region in the plan view, and adjacent to the first... A first source electrode of a vertical MOS transistor is connected; a first gate pad is formed in the first region in the plan view and connected to the first gate electrode of the first vertical MOS transistor; a first drain pad is formed in the first region in the plan view and connected to the first drain electrode of the first vertical MOS transistor; a second source pad group consisting of a plurality of second source pads is formed in the second region in the plan view and connected to the second source electrode of the second vertical MOS transistor; a second gate pad is formed in the second region in the plan view and connected to the second gate electrode of the second vertical MOS transistor; a second drain pad... A pad, formed in the second region in the plan view, and connected to the second drain electrode of the second vertical MOS transistor; and a metal layer formed in contact with the back side of the semiconductor substrate, the semiconductor substrate being the common drain region of the first vertical MOS transistor and the second vertical MOS transistor; in the plan view, the semiconductor layer is a rectangle having a long side and a short side; in the plan view, the first region and the second region are one and the other dividing the semiconductor layer into two equal parts in area; in the plan view, the first drain pad and the second drain pad are arranged in a direction orthogonal to the boundary lines of the first region and the second region, connecting the... The midpoint of the line segment connecting the center of the first drain pad and the center of the second drain pad is located on the boundary line. In the plan view, the first gate pad and the second gate pad are arranged in a direction orthogonal to the boundary line. The midpoint of the line segment connecting the center of the first gate pad and the center of the second gate pad is located on the boundary line. In the plan view, no other pads are sandwiched between the first drain pad and the second drain pad and one of the short sides of the outer periphery of the rectangular semiconductor layer. In the plan view, no other pads are sandwiched between the first gate pad and the second gate pad and the other short side of the outer periphery of the rectangular semiconductor layer.

[0011] Alternatively, in the plan view, the first gate pad and the first drain pad are not adjacent to each other, and the second gate pad and the second drain pad are not adjacent to each other.

[0012] Alternatively, in the plan view, no other pads are sandwiched between the plurality of first source pads, no other pads are sandwiched between the plurality of second source pads, and no other pads are sandwiched between the first source pad group and the second source pad group in the plan view.

[0013] Alternatively, in the plan view, in the first region, a plurality of first source pads are arranged between the first gate pad and the first drain pad along the arrangement direction of the first gate pad and the first drain pad; and in the second region, in the plan view, a plurality of second source pads are arranged between the second gate pad and the second drain pad along the arrangement direction of the second gate pad and the second drain pad.

[0014] Alternatively, in the plan view, in the first region, a plurality of first source pads are also arranged in a direction orthogonal to the boundary line, and in the second region, a plurality of second source pads are also arranged in a direction orthogonal to the boundary line.

[0015] Alternatively, in the plan view, the first gate pad, the second gate pad, the first drain pad, and the second drain pad are circles with the same diameter, and are the smallest pads in the semiconductor layer.

[0016] Utility Model Effect

[0017] With the above configuration, in a vertical MOS transistor with a dual structure that can control bidirectional conduction, a secondary path with a relatively small current flow can be added to the same device while minimizing the obstruction of the conduction of the main path through which a relatively large current flows.

[0018] Thus, this disclosure allows for the conduction of the main path through which a relatively large current flows with minimal obstruction, and enables the secondary path through which a relatively small current flows to be attached to the same device. Attached Figure Description

[0019] Figure 1 This is a cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 1.

[0020] Figure 2AThis is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0021] Figure 2B This is a cross-sectional view showing the main current flowing through the semiconductor device according to Embodiment 1.

[0022] Figure 2C This is a plan view showing an example of the shape of the body region and the active region of the semiconductor device according to Embodiment 1.

[0023] Figure 2D This is a plan view showing an example of an enlarged view of the gate electrode portion of the semiconductor device according to Embodiment 1.

[0024] Figure 3A This is a cross-sectional view showing an example of the structure of the semiconductor device according to Embodiment 1.

[0025] Figure 3B This is a cross-sectional view showing the secondary current flowing through the semiconductor device according to Embodiment 1.

[0026] Figure 4A This is a plan view of the approximate unit structure of the first transistor involved in Embodiment 1.

[0027] Figure 4B This is a perspective view of the approximate unit structure of the first transistor involved in Embodiment 1.

[0028] Figure 5A This is a circuit diagram illustrating an application example of the semiconductor device according to Embodiment 1 in a charging and discharging circuit.

[0029] Figure 5B This is a circuit diagram illustrating an application example of the semiconductor device according to Embodiment 1 in a charging and discharging circuit.

[0030] Figure 6A This is a plan view showing an example of the pad configuration of a comparative example of the semiconductor device according to Embodiment 1.

[0031] Figure 6B This is a circuit diagram illustrating an application example of a comparative example of the semiconductor device according to Embodiment 1 in a charging and discharging circuit.

[0032] Figure 7A This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0033] Figure 7B This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0034] Figure 7C This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0035] Figure 7D This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0036] Figure 8A This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0037] Figure 8B This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0038] Figure 8C This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0039] Figure 8D This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0040] Figure 9A This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0041] Figure 9B This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0042] Figure 10A This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0043] Figure 10B This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0044] Figure 10C This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 1.

[0045] Figure 11 This is a cross-sectional view showing the warped appearance of the semiconductor device according to Embodiment 1.

[0046] Figure 12A This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0047] Figure 12B This is a cross-sectional view showing the secondary current flowing in the semiconductor device according to Embodiment 2.

[0048] Figure 12C This is a plan view showing an enlarged example of the drain electrode portion and gate electrode portion of the semiconductor device according to Embodiment 2.

[0049] Figure 13A This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0050] Figure 13B This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0051] Figure 13C This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0052] Figure 14A This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0053] Figure 14B This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0054] Figure 14C This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0055] Figure 14D This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0056] Figure 15A This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0057] Figure 15B This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0058] Figure 16A This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0059] Figure 16B This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0060] Figure 16C This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0061] Figure 16D This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 2.

[0062] Figure 17A This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 3.

[0063] Figure 17B This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 3.

[0064] Figure 17C This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 3.

[0065] Figure 17D This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 3.

[0066] Figure 18A This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 3.

[0067] Figure 18B This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 3.

[0068] Figure 19A This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 4.

[0069] Figure 19B This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to Embodiment 4.

[0070] Explanation of reference numerals in the attached figures

[0071] 1. Semiconductor devices, 1A, 1B, 1C, 2

[0072] 4 control ICs

[0073] 5 Lithium-ion batteries

[0074] 6 load

[0075] 10. 10A Transistor (First Vertical Type MOS Transistor)

[0076] 11 First source electrode

[0077] Parts 12 and 13

[0078] 14 First Source Region

[0079] 15 First gate conductor

[0080] 16 First gate insulating film

[0081] 17 First gate trench

[0082] 18 First Physical Area

[0083] 18a First Connecting Part

[0084] 19 First gate electrode

[0085] 20, 20A transistor (second vertical MOS transistor)

[0086] 21 Second source electrode

[0087] Parts 22 and 23

[0088] 24 Second source region

[0089] 25 Second gate conductor

[0090] 26 Second gate insulating film

[0091] 27 Second gate trench

[0092] 28 Second Body Area

[0093] 28a Second connecting part

[0094] 29 Second gate electrode

[0095] 30 transistors (third vertical MOS transistor)

[0096] 31 Third source electrode

[0097] 32 Semiconductor Substrate

[0098] 33 Low-concentration impurity layer

[0099] 34 interlayer insulation layers

[0100] 35 passivation layer

[0101] 39 Third gate electrode

[0102] 40 semiconductor layers

[0103] 41 metal layers

[0104] 51 Drain Electrode

[0105] Parts 52 and 53

[0106] 58 Drain Lead-out Region

[0107] 51A First Drain Electrode

[0108] Parts 52A and 53A

[0109] 58A First Drain Lead-out Region

[0110] 61A Second Drain Electrode

[0111] Parts 62A and 63A

[0112] 68A Second Drain Lead-out Region

[0113] 90 Central Line

[0114] 90C boundary line

[0115] 111, 111A, 111a~111f First source pads

[0116] 112 First Active Zone

[0117] 119, 119A First Gate Pad

[0118] 121, 121A, 121a~121f Second source pads

[0119] 122 Second Active Region

[0120] 129, 129A Second Gate Pad

[0121] 131 Third Source Pad

[0122] 139 Third Gate Pad

[0123] 151 drain pad

[0124] 151A First Drain Pad

[0125] 161A Second Drain Pad

[0126] A1, A1A First Area

[0127] A2, A2A Second Area

[0128] A3 Third Area

[0129] C1 charging current

[0130] C2 discharge current

[0131] C3 has a relatively small charging current.

[0132] S1 external switching element Detailed Implementation

[0133] The embodiments described below are all specific examples illustrating this disclosure. The values, shapes, materials, constituent elements, arrangement positions of constituent elements, and connection methods shown in the following embodiments are merely examples and are not intended to limit this disclosure.

[0134] In this disclosure, the cases of "A and B being electrically connected" include: A and B being directly connected via wiring, A and B being directly connected without wiring, and A and B being indirectly connected via resistive components (resistive elements, resistive wiring).

[0135] (Implementation Method 1)

[0136] [1. Structure of a Semiconductor Device]

[0137] The structure of the semiconductor device according to Embodiment 1 will be described below. The semiconductor device according to Embodiment 1 is a chip-size package (CSP) type semiconductor device that can be mounted face-down and has two vertical MOS (Metal Oxide Semiconductor) transistors formed on a semiconductor substrate. The two vertical MOS transistors are power transistors, specifically trench MOSFETs (Field Effect Transistors).

[0138] Figure 1 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to Embodiment 1. Figure 2A This is a plan view illustrating an example of the arrangement of the pads of semiconductor device 1. The size and / or shape of semiconductor device 1, except that it is rectangular, is an example. Furthermore, the size, shape, and arrangement of the pads are also an example.

[0139] Figure 1 It is shown Figure 2A A sectional view at point I-I.

[0140] like Figure 1 as well as Figure 2A As shown, the semiconductor device 1 has a semiconductor layer 40, a metal layer 41, a first vertical MOS transistor 10 (hereinafter also referred to as transistor 10) formed in a first region A1 within the semiconductor layer 40, a second vertical MOS transistor 20 (hereinafter also referred to as transistor 20) formed in a second region A2 within the semiconductor layer 40, and a third region A3 that does not overlap with the first region A1 and the second region A2.

[0141] In this disclosure, the semiconductor layer formed on the semiconductor substrate 32, together with the semiconductor substrate 32, is referred to as semiconductor layer 40. Semiconductor layer 40 is formed by stacking the semiconductor substrate 32 and a low-concentration impurity layer 33. The semiconductor substrate 32 is disposed on the back side of semiconductor layer 40 and is made of silicon containing impurities of a first conductivity type. The low-concentration impurity layer 33 is a first conductivity type impurity layer formed on the surface side of semiconductor layer 40 in contact with the semiconductor substrate 32, and contains a lower concentration of first conductivity type impurities than the first conductivity type impurities in semiconductor substrate 32. The low-concentration impurity layer 33 may also be formed on semiconductor substrate 32, for example, by epitaxial growth.

[0142] The metal layer 41 is formed by contacting the back side of the semiconductor layer 40 and is made of silver (Ag) or copper (Cu). Additionally, the metal layer 41 may contain trace amounts of elements other than metals that are introduced as impurities during the manufacturing process of the metal material. Furthermore, the metal layer 41 may be formed on the entire back side of the semiconductor layer 40 or not on the entire back side; either method is acceptable.

[0143] like Figure 1 as well as Figure 2A As shown, a first body region 18 of a second conductivity type is formed in the first region A1 of the low-concentration impurity layer 33. The first body region 18 of the second conductivity type contains impurities of a second conductivity type different from the first conductivity type. A first source region 14 of the first conductivity type containing impurities of the first conductivity type is formed in the first body region 18. A plurality of first gate trenches 17 are formed in the first region A1. The plurality of first gate trenches 17 extend from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a depth of a portion of the low-concentration impurity layer 33, and a first gate conductor 15 is formed on a first gate insulating film 16 inside the first gate trench 17.

[0144] The first source electrode 11 is composed of a portion 12 and a portion 13, with portion 12 connected to the first source region 14 and the first body region 18 via portion 13. The first gate conductor 15 is a buried gate electrode embedded inside the semiconductor layer 40 and electrically connected to the first gate pad 119.

[0145] Part 12 of the first source electrode 11 is a layer that bonds with solder during reflow when mounted face down. As a non-limiting example, it may be made of a metallic material containing one or more of nickel, titanium, tungsten, and palladium. A plating layer such as gold may be applied to the surface of part 12.

[0146] The portion 13 of the first source electrode 11 is a layer that connects the portion 12 to the semiconductor layer 40. As a non-limiting example, it may be made of a metallic material containing one or more of aluminum, copper, gold, and silver.

[0147] In the second region A2 of the low-concentration impurity layer 33, a second body region 28 containing impurities of a second conductivity type is formed. In the second body region 28, a second source region 24 containing impurities of a first conductivity type is formed. A plurality of second gate trenches 27 are formed in the second region A2, extending from the upper surface of the semiconductor layer 40 through the second source region 24 and the second body region 28 to a depth equal to a portion of the low-concentration impurity layer 33. A second gate conductor 25 is formed inside the second gate trenches 27 on a second gate insulating film 26.

[0148] The second source electrode 21 is composed of portions 22 and 23, with portion 22 connected to the second source region 24 and the second body region 28 via portion 23. The second gate conductor 25 is a buried gate electrode embedded inside the semiconductor layer 40 and electrically connected to the second gate pad 129.

[0149] The portion 22 of the second source electrode 21 is a layer that bonds with the solder during reflow when mounted face down. As a non-limiting example, it may be made of a metallic material containing one or more of nickel, titanium, tungsten, and palladium. A plating layer such as gold may be applied to the surface of the portion 22.

[0150] The portion 23 of the second source electrode 21 is a layer that connects the portion 22 to the semiconductor layer 40. As a non-limiting example, it may be made of a metal material containing one or more of aluminum, copper, gold, and silver.

[0151] With the aforementioned structures of transistors 10 and 20, the region directly above the semiconductor substrate 32 in the semiconductor substrate 32 and the low-concentration impurity layer 33 functions as a common drain region that combines the first drain region of transistor 10 and the second drain region of transistor 20. Furthermore, the metal layer 41 functions as a common drain electrode (hereinafter also referred to as the back-side drain electrode) on the back side of the semiconductor layer 40, which combines the drain electrodes of transistors 10 and 20.

[0152] like Figure 1 As shown, the first body region 18 is covered by an interlayer insulating layer 34 with an opening, and has a portion 13 of a first source electrode 11 connected to the first source region 14 through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 13 of the first source electrode 11 are covered by a passivation layer 35 with an opening, and have a portion 12 connected to the portion 13 of the first source electrode 11 through the opening of the passivation layer 35.

[0153] The second body region 28 is covered by an interlayer insulating layer 34 with an opening, and has a portion 23 of a second source electrode 21 connected to the second source region 24 through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 23 of the second source electrode 21 are covered by a passivation layer 35 with an opening, and have a portion 22 connected to the portion 23 of the second source electrode 21 through the opening of the passivation layer 35.

[0154] Therefore, the plurality of first source pads 111 and the plurality of second source pads 121 respectively refer to the areas where the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1, i.e., the so-called terminal portions. Similarly, the first gate pad 119 and the second gate pad 129 respectively refer to the areas where the first gate electrode 19 (on the surface of the semiconductor device 1) is partially exposed on the surface of the semiconductor device 1. Figure 1 , Figure 2A (not shown in the diagram) and the second gate electrode 29 (in Figure 1 , Figure 2A (Not shown in the figure) The area partially exposed on the surface of semiconductor device 1, namely the so-called terminal portion.

[0155] Figure 3A It is shown Figure 2A A sectional view at point II-II. (See figure.) Figure 3A As shown, in the third region A3 of the low-concentration impurity layer 33, a drain lead-out region 58 of a first conductivity type is formed within the low-concentration impurity layer 33. This drain lead-out region 58 contains first conductivity type impurities at a higher concentration than the concentration of first conductivity type impurities in the low-concentration impurity layer 33. Furthermore, the drain lead-out region 58 can also be formed within the low-concentration impurity layer 33 to a depth reaching the semiconductor substrate 32.

[0156] The drain electrode (hereinafter also referred to as the surface-side drain electrode) 51 is composed of part 52 and part 53, with part 52 connected to the drain lead-out region 58 via part 53.

[0157] The portion 52 of the drain electrode 51 is a layer that bonds with the solder during reflow when mounted face down. As a non-limiting example, it is made of a metallic material containing one or more of nickel, titanium, tungsten, and palladium. A plating layer such as gold may be applied to the surface of the portion 52.

[0158] A portion 53 of the drain electrode 51 is a layer that connects portion 52 to the drain lead-out region 58. Therefore, the drain electrode 51 has a drain potential common to transistors 10 and 20. Furthermore, as a non-limiting example, portion 53 of the drain electrode 51 may be made of one or more metallic materials containing aluminum, copper, gold, or silver.

[0159] like Figure 3AAs shown, the low-concentration impurity layer 33 is covered by an interlayer insulating layer 34 with an opening, and a portion 53 of the drain electrode 51 is provided that is connected to the drain lead-out region 58 through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 53 of the drain electrode 51 are covered by a passivation layer 35 with an opening, and a portion 52 is provided that is connected to the portion 53 of the drain electrode 51 through the opening of the passivation layer 35.

[0160] Therefore, the drain pad 151 refers to the area where the drain electrode 51 is partially exposed on the surface of the semiconductor device 1, i.e., the portion of the terminal.

[0161] As a standard design example of the various structures in semiconductor device 1, the thickness of semiconductor layer 40 is 10-90 μm, the thickness of metal layer 41 is 10-90 μm, and the sum of the thicknesses of interlayer insulating layer 34 and passivation layer 35 is 3-13 μm.

[0162] like Figure 1 as well as Figure 2A As shown, transistor 10 has a plurality of first source pads 111 and first gate pads 119 on the surface of semiconductor layer 40, which are bonded to the mounting substrate via bonding material when mounted face down. Similarly, transistor 20 has a plurality of second source pads 121 and second gate pads 129 on the surface of semiconductor layer 40, which are bonded to the mounting substrate via bonding material when mounted face down. Furthermore, the third region A3 has a drain pad 151 on the surface of semiconductor layer 40, which is bonded to the mounting substrate via bonding material when mounted face down.

[0163] like Figure 1 as well as Figure 2A As shown, in the plan view, the semiconductor device 1 and the semiconductor layer 40 are rectangular in shape. Additionally, in... Figure 2A In the process, although the semiconductor device 1 and the semiconductor layer 40 are rectangular, they can also be square.

[0164] In a plan view, the direction in which the first region A1 and the second region A2 are arranged in a direction parallel to the outer periphery of the semiconductor device 1 is defined as the first direction. In a plan view, the arrangement of the first region A1 and the second region A2 in the first direction means that the first region A1 and the second region A2 are arranged most facing each other in the first direction.

[0165] The term "most oriented in the first direction" refers to the longest portion of the boundary line 90C between the first region A1 and the second region A2 (described later) in a plan view, which is orthogonal to the first direction. For example, if the boundary line 90C is curved in the plan view, the first direction is the direction orthogonal to the direction in which the sum of the line segments forming the boundary line 90C is longest.

[0166] like Figure 2A As shown, in a plan view of semiconductor layer 40, the first region A1 and the second region A2 are adjacent to each other, and the area of ​​semiconductor layer 40, excluding the third region A3, is divided into two equal parts.

[0167] like Figure 2A As shown, in the plan view of semiconductor layer 40, the central line 90 is a line that bisects semiconductor layer 40 in the first direction. In the plan view of semiconductor layer 40, the central line 90 is a straight line in a direction orthogonal to the first direction.

[0168] Furthermore, the center of the third region A3 of the semiconductor layer 40 is located on the central line 90 of the semiconductor layer 40 in a plan view of the semiconductor layer 40. Regarding the center... Figure 2A As shown, if the drain pad 151 is circular, the center refers to the center of the circle; if the third region A3 is rectangular, the center refers to the intersection of the diagonals of the rectangle; and if the region is elliptical, the center refers to the intersection of the major and minor axes of the ellipse.

[0169] And in Figure 2A In the diagram, the virtual boundary lines 90C used to distinguish the first region A1, the second region A2, and the third region A3 of the semiconductor layer 40 are represented by dashed lines. The boundary line 90C on the region adjacent to the first region A1 and the second region A2 can also be viewed as a virtual line at the center of the gap between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Furthermore, if it has a finite width, it can also be viewed as the gap itself (even with this gap, it can be seen as a line when observed with the naked eye or at low magnification).

[0170] The boundary line 90C on the region adjacent to the first region A1 and the third region A3 can also be regarded as a virtual line along the central position of the interval between the portion 13 of the first source electrode 11 and the portion 53 of the drain electrode 51. And if it is of finite width, it can also be regarded as the interval itself.

[0171] The boundary line 90C on the region adjacent to the second region A2 and the third region A3 can also be regarded as a virtual line along the central position of the interval between the portion 23 of the second source electrode 21 and the portion 53 of the drain electrode 51. And if it is of finite width, it can also be regarded as the interval itself.

[0172] Furthermore, although the boundary line 90C bisects the area of ​​semiconductor layer 40 except for the third region A3 in the plan view of semiconductor layer 40, it does not necessarily have to be a straight line. Also, in the plan view of semiconductor layer 40, the central line 90 and the boundary line 90C may at least partially coincide.

[0173] Drain pad 151 is configured in a plan view of semiconductor layer 40, located inside and surrounded by the third region A3 of semiconductor layer 40. Figure 2A In the example, the center of the drain pad 151 coincides with the center of the third region A3. The drain pad 151 only needs to be located within the third region A3, but it is also possible for the center of the drain pad 151 to not coincide with the center of the third region A3.

[0174] In the plan view of semiconductor layer 40, it is desirable that the area of ​​the third region A3 of semiconductor layer 40 be smaller than the areas of both the first region A1 and the second region A2. This is because the areas of the first region A1 and the second region A2 need to be as large as possible in order to reduce the on-resistance of the main path, as will be explained later. For the main path, the secondary path of semiconductor device 1 only needs to carry a relatively small current, so there is no need to increase the area of ​​the third region A3. Regarding the shape of the third region A3 in the plan view, as a representative example, it is desirable that it be a rectangle circumscribed around the drain pad 151, independent of the shape of the surrounding drain pad 151, except for any empty spaces.

[0175] Furthermore, drain pad 151 does not need to be affected. Figure 2A Due to shape limitations in the examples, it could also be Figure 2A The example shown is roughly elliptical, but it can also be roughly rectangular.

[0176] The number of each of the plurality of first source pads 111 of transistor 10 and the plurality of second source pads 121 of transistor 20 need not be limited. Figure 2A The example shown is limited to five, but there can be more than five. Furthermore, the shapes of the plurality of first source pads 111 of transistor 10 and the plurality of second source pads 121 of transistor 20 are not necessarily limited to five. Figure 2A The example shown is roughly rectangular, which can be either... Figure 2A The example shown is roughly rectangular, but it could also be roughly circular. Furthermore, the respective configurations of the plurality of first source pads 111 of transistor 10 and the plurality of second source pads 121 of transistor 20 do not need to be constrained by... Figure 2A The configuration shown in the example is limited.

[0177] Furthermore, the number of the first gate pad 119 of transistor 10 and the second gate pad 129 of transistor 20 need not be limited by... Figure 2A The example shown may be limited to one, but there may be two or more. Furthermore, the shapes of the first gate pad 119 and the second gate pad 129 can each be... Figure 2A The example shown is approximately circular, but it may not be approximately circular. Furthermore, the configuration of the first gate pad 119 and the second gate pad 129 need not be constrained by... Figure 2A The configuration shown in the example is limited.

[0178] In addition, Figure 1 , Figure 2A Although not shown, in a plan view of semiconductor layer 40, a first EQR (equipotential ring) electrically connected to the drain region of transistor 10 may be provided on the outer periphery of the first region A1. Similarly, in a plan view of semiconductor layer 40, a second EQR electrically connected to the drain region of transistor 20 may be provided on the outer periphery of the second region A2. In the adjacent and facing portions of transistors 10 and 20, the first EQR and the second EQR may be common.

[0179] The first EQR is intended to prevent leakage current from flowing between the transistor 10 and the first body region 18. The second EQR is intended to prevent leakage current from flowing between the transistor 20 and the second body region 28.

[0180] As a non-limiting example, the first EQR and the second EQR can be made of one or more metallic materials including aluminum, copper, gold, and silver. Furthermore, the first EQR and the second EQR can be electrically connected to the surface-side drain electrode 51, or they can be electrically connected to the back-side drain electrode 41 via the semiconductor substrate 32, which serves as a common drain region.

[0181] [2. The operation of semiconductor devices]

[0182] Figure 4A as well as Figure 4B These are, respectively, a plan view and a perspective view of the approximate unit structure of transistors 10 or 20 repeatedly formed in the X and Y directions of semiconductor device 1. Figure 4A as well as Figure 4B For ease of understanding, the semiconductor substrate 32, metal layer 41, passivation layer 35, first source electrode 11 or second source electrode 21, and interlayer insulating layer 34 are not illustrated.

[0183] Furthermore, the Y direction is parallel to the upper surface of the semiconductor layer 40 and is the direction in which the first gate trench 17 extends. The X direction is parallel to the upper surface of the semiconductor layer 40 and orthogonal to the Y direction. The Z direction is orthogonal to both the X and Y directions and is the direction indicating the height of the semiconductor device 1.

[0184] Although the directions have been defined above, the Y direction can be opposite to the X direction in the following explanation. That is, the X direction can be parallel to the upper surface of the semiconductor layer 40 and be the direction in which the first gate trench 17 extends. In this case, the Y direction is parallel to the upper surface of the semiconductor layer 40 and orthogonal to the X direction.

[0185] like Figure 4A as well as Figure 4B As shown, transistor 10 includes a first connection portion 18a that electrically connects a first body region 18 to a first source electrode 11. The first connection portion 18a is a region in the first body region 18 where the first source region 14 is not formed, and contains impurities of the same second conductivity type as the first body region 18. The first source region 14 and the first connection portion 18a are alternately and periodically arranged along the Y direction. Transistor 20 is similar.

[0186] In the semiconductor device 1, for example, the first conductivity type can be set as N-type and the second conductivity type can be set as P-type. The first source region 14, the second source region 24, the drain lead-out region 58, the semiconductor substrate 32, and the low concentration impurity layer 33 can be N-type semiconductors, and the first body region 18, the first connection portion 18a, the second body region 28, and the second connection portion 28a can be P-type semiconductors.

[0187] Furthermore, in the semiconductor device 1, for example, the first conductivity type can be set as P-type and the second conductivity type can be set as N-type. The first source region 14, the second source region 24, the drain lead-out region 58, the semiconductor substrate 32, and the low concentration impurity layer 33 can be P-type semiconductors, and the first body region 18, the first connection portion 18a, the second body region 28, and the second connection portion 28a can be N-type semiconductors.

[0188] In the following description, transistors 10 and 20 are used as examples of so-called N-channel transistors, where the first conductivity type is N-type and the second conductivity type is P-type. Figure 2B The bidirectional conduction path through which the main current flows in the semiconductor device 1 shown is explained.

[0189] In semiconductor device 1, if a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage above a threshold is applied to the second gate electrode 29 (second gate conductor 25) with reference to the second source electrode 21, a conductive channel is formed near the second gate insulating film 26 in the second body region 28. Thus, a main current flows through the path of first source electrode 11 - first connection portion 18a - first body region 18 - low-concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - low-concentration impurity layer 33 - conductive channel formed in the second body region 28 - second source region 24 - second source electrode 21, and semiconductor device 1 becomes conductive. In this disclosure, this conductive path is referred to as the main path. A PN junction exists at the contact surface between the first body region 18 and the low-concentration impurity layer 33 in this main path, functioning as a body diode.

[0190] Similarly, in semiconductor device 1, if a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage above a threshold is applied to the first gate electrode 19 (first gate conductor 15) with reference to the first source electrode 11, a conductive channel is formed near the first gate insulating film 16 in the first body region 18. Thus, a main current flows through the path of second source electrode 21 - second connection portion 28a - second body region 28 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - low concentration impurity layer 33 - conductive channel formed in the first body region 18 - first source region 14 - first source electrode 11, and semiconductor device 1 becomes conductive. In this disclosure, this conductive path is also referred to as the main path. A PN junction exists at the contact surface between the second body region 28 and the low concentration impurity layer 33 in this main path, functioning as a body diode.

[0191] Furthermore, in the semiconductor device 1, a voltage exceeding a threshold value can be applied to the first gate electrode 19 to form a conduction channel near the first gate insulating film 16 in the first body region 18, while a voltage exceeding a threshold value can be applied to the second gate electrode 29 to form a conduction channel near the second gate insulating film 26 in the second body region 28. In this way, a main current can flow through a path such as first source electrode 11 - first source region 14 - conduction channel formed in the first body region 18 - low-concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - low-concentration impurity layer 33 - conduction channel formed in the second body region 28 - second source region 24 - second source electrode 21, or a path opposite to this path, to turn on the semiconductor device 1. In this disclosure, this bidirectional conduction path is also referred to as the main path.

[0192] In addition, the terms "main current" and "main path" used in this disclosure are used to distinguish them from the "secondary current" and "secondary path" which will be described later.

[0193] Figure 3B This is a cross-sectional view showing the secondary current flowing through semiconductor device 1. The secondary current in... Figure 3B Not illustrated, the secondary current is a current controlled by an external switching element (e.g., a single-structure vertical MOS transistor) connected in series with the drain electrode 51 of the semiconductor device 1, and is relatively small compared to the main current. Furthermore, in this disclosure, the conduction path through which the secondary current flows in the semiconductor device 1 is referred to as the secondary path.

[0194] In semiconductor device 1, if a high voltage is applied to the first source electrode 11 and a low voltage is applied to the drain electrode 51, and an external switching element connected in series with the drain electrode 51 is turned on, a secondary current flows through the path of the first source electrode 11 - first connection portion 18a - first body region 18 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - low concentration impurity layer 33 - drain lead-out region 58 - drain electrode 51, and semiconductor device 1 becomes turned on. Furthermore, if a high voltage is applied to the first source electrode 11 and a low voltage is applied to the drain electrode 51, causing the external switching element to be in a conducting state, and a voltage above a threshold is applied to the first gate electrode 19 with the first source electrode 11 as a reference, a conducting channel is formed near the first gate insulating film 16 in the first body region 18, and a secondary current flows through the path of first source electrode 11 - first source region 14 - conducting channel formed in the first body region 18 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - low concentration impurity layer 33 - drain lead-out region 58 - drain electrode 51, and the semiconductor device 1 becomes in a conducting state.

[0195] Similarly, if a high voltage is applied to the second source electrode 21 and a low voltage is applied to the drain electrode 51, and the external switching element connected in series with the drain electrode 51 is turned on, the secondary current flows through the path of the second source electrode 21 - second connection portion 28a - second body region 28 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - low concentration impurity layer 33 - drain lead-out region 58 - drain electrode 51, and the semiconductor device 1 is turned on. Furthermore, if a high voltage is applied to the second source electrode 21 and a low voltage is applied to the drain electrode 51, causing the external switching element to be turned on, and a voltage above a threshold is applied to the second gate electrode 29 with the second source electrode 21 as a reference, a conduction channel is formed near the second gate insulating film 26 in the second body region 28. A secondary current flows through the path of second source electrode 21 - second source region 24 - conduction channel formed in the second body region 28 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - low concentration impurity layer 33 - drain lead-out region 58 - drain electrode 51, and the semiconductor device 1 becomes turned on.

[0196] These conduction paths through which the secondary current flows are called secondary paths. The secondary path of semiconductor device 1 is controlled by making an external switching element connected in series with the drain electrode 51 either in a conducting or non-conducting state. When the switching element is in a conducting state, the secondary path of semiconductor device 1 becomes a conducting state. In addition, PN junctions exist at the contact surfaces of the first body region 18 and the low-concentration impurity layer 33 and the second body region 28 and the low-concentration impurity layer 33 in this secondary path, functioning as body diodes.

[0197] When the main path is turned on, the external switching element connected in series with the drain electrode 51 must be controlled to be turned off, so the secondary path is turned off and only the main path is turned on.

[0198] Figure 2C This is a plan view showing an example of the shape of the first body region 18 and the second body region 28, the first active region 112 and the second active region 122, among the constituent elements of the semiconductor device 1, in a plan view of the semiconductor layer 40. Figure 2C In order to clearly illustrate the structure of the upper surface of the semiconductor layer 40, which is not actually visible, the passivation layer 35, the first source electrode 11, the first gate electrode 19, the second source electrode 21, the second gate electrode 29, the drain electrode 51, and the interlayer insulating layer 34 are considered transparent and omitted from the illustration. The illustrations of the first source region 14, the second source region 24, and the drain lead-out region 58 are also omitted.

[0199] To reduce the on-resistance of the main path of semiconductor device 1, it is necessary to ensure that the first active region 112 and the second active region 122 are as large as possible. The first active region 112 is the smallest area encompassing the portion where a conduction channel is formed when a voltage above a threshold is applied to the first gate electrode 19 (first gate conductor 15) of transistor 10. The portion where a conduction channel is formed refers to the portion of each of the plurality of first gate trenches 17 adjacent to the first source region 14. For example... Figure 2C As shown, in a plan view of semiconductor layer 40, the first active region 112 is surrounded by the first body region 18. The second active region 122 is the smallest area surrounding the portion that forms a conduction channel when a voltage above a threshold is applied to the second gate electrode 29 (second gate conductor 25) of transistor 20. The portion forming the conduction channel refers to the portion of each of the plurality of second gate trenches 27 adjacent to the second source region 24. Figure 2C As shown, in a plan view of semiconductor layer 40, the second active region 122 is surrounded by the second body region 28.

[0200] The larger the area of ​​the first active region 112 and the area of ​​the second active region 122, the larger the main path becomes, thereby reducing the on-resistance of the main path of the semiconductor device 1.

[0201] Figure 2D It is shown Figure 2A The first gate pad 119 is configured as an enlarged plan view. Figure 2D This is an example of the shape of portion 13 of the first source electrode 11, the first gate electrode 19, and the first gate pad 119 in a plan view of the semiconductor layer 40, which are components of the semiconductor device 1. Figure 2D To make the structure of the upper surface of the semiconductor layer 40, which is not actually visible, easily understandable, the passivation layer 35 and the interlayer insulating layer 34 are omitted from the illustration as they are considered transparent. The illustration of the first source region 14 is also omitted.

[0202] Although the illustration is omitted, portion 23 of the second source electrode 21, the second gate electrode 29, and the second gate pad 129 are... Figure 2D The portion 13 of the first source electrode 11, the first gate electrode 19, and the first gate pad 119 shown are linearly symmetrical about the central line 90 as the axis of symmetry.

[0203] The regions directly below and near the first gate electrode 19, and the regions directly below and near the second gate electrode 29, are areas that do not contribute to the conduction of the main path. Here, "nearby region" refers to the area along the outer periphery of the first gate electrode 19 and the second gate electrode 29. Figure 2DThe region can be understood as the area between the first gate electrode 19 and the portion 13 of the first source electrode 11, and the region between the second gate electrode 29 and the second source electrode 21 (omitted from the figure).

[0204] Furthermore, the third region A3 surrounding the drain pad 151 is also a region that does not contribute to the conduction of the main path.

[0205] In other words, the area directly below and near the first gate electrode 19, the area directly below and near the second gate electrode 29, and the third region A3 in the semiconductor device 1 are areas required for the semiconductor device 1 to function, but are areas that are desirable to be minimized as much as possible in a limited device area in order to reduce the on-resistance of the main path of the semiconductor device 1.

[0206] [3. Application Examples of Semiconductor Devices]

[0207] Figure 5A This is a circuit diagram illustrating an application example of the semiconductor device 1 of this disclosure in a protection circuit for a lithium-ion battery 5. In this application example, the semiconductor device 1 controls the bidirectional conduction of the main path according to control signals provided from the control IC 4 to the first gate electrode 19 and the second gate electrode 29, thereby controlling the discharge operation from the lithium-ion battery 5 to the load 6 or the charging operation from the load 6 to the lithium-ion battery 5. At this time, since the charging current C1 or the discharging current C2 flowing through the semiconductor device 1 is a relatively large current, the secondary path is not used. When the semiconductor device 1 of this disclosure is applied to a battery protection circuit, the control of bidirectional conduction for charging and discharging using the main path can also be considered the main function of the semiconductor device 1. Since the main path carries a relatively large current, it is desirable to minimize the on-resistance as much as possible.

[0208] Then use Figure 5A The application of the secondary path will be explained. In addition to the main path, the semiconductor device 1 has a secondary path utilizing the drain electrode 51. During pre-charging, a charging current C3 flows through the secondary path. If the lithium-ion battery 5 is in an over-discharged state, it would be dangerous to charge it with a relatively large charging current C1, as in normal charging. Pre-charging refers to charging with a relatively small charging current C3.

[0209] exist Figure 5ASince the semiconductor device 1 cannot independently control the conduction of the secondary path, an external switching element (e.g., a single-structure vertical MOS transistor) S1, capable of controlling the conduction and non-conduction states, is connected in series to the drain electrode 51 of the semiconductor device 1. The external switching element S1 is controlled to be in a conduction or non-conduction state by a control signal provided from the control IC 4. By making the secondary path of the semiconductor device 1 conduct when the switching element S1 is in a conduction state, and making the secondary path of the semiconductor device 1 non-conduction when the switching element S1 is in a non-conduction state, the charging operation from the load 6 to the lithium-ion battery 5 is controlled with a relatively small charging current C3. Furthermore, when the main path of the semiconductor device 1 is turned on, the external switching element S1 must be controlled to be in a non-conducting state.

[0210] During pre-charging, a relatively small charging current C3 is initially used. Once the lithium-ion battery 5 is charged to a certain level, the charging current C1 is switched to a relatively large charging current. In the secondary path, since a relatively small charging current C3 needs to flow, there is no need to focus on reducing the on-resistance.

[0211] Figure 5B This is a circuit diagram illustrating an application example of semiconductor device 1, and... Figure 5A This is also an example of an application of the protection circuit for lithium-ion batteries 5 used in lithium-ion battery packs. Figure 5B Zhongyu Figure 5A The main function of semiconductor device 1 is the same as described above, which is to control the charging current C1 and the discharging current C2. However, the method of utilizing the secondary path is different. The drain electrode 51 of semiconductor device 1 is connected to control IC 4 and is used as a monitor terminal for the drain voltage common to transistors 10 and 20. Figure 5B In this circuit, since the secondary path of semiconductor device 1 is connected to control IC4, it is controlled by control IC4 to be in a non-conducting state, and therefore no secondary current flows. When controlling the charging current C1 and discharging current C2 of lithium-ion battery 5, control IC4 uses the secondary path to monitor the voltage of drain electrode 51. When the voltage of drain electrode 51 deviates from the normal voltage range of lithium-ion battery 5, it is determined to be an abnormal state, and the charging and discharging operation is stopped. Accordingly, over-discharging and over-charging of lithium-ion battery 5 can be prevented.

[0212] [4. Effects of the semiconductor device 1 according to Embodiment 1]

[0213] The features of the semiconductor device 1 in this disclosure described above are as follows.

[0214] The semiconductor device 1 disclosed herein is a chip-size packaged semiconductor device capable of being mounted face-down. The semiconductor device 1 includes: a semiconductor substrate 32; a low-concentration impurity layer 33 formed on the semiconductor substrate 32; a first vertical MOS transistor 10 formed in a first region A1 of the semiconductor layer 40 when the semiconductor substrate 32 and the low-concentration impurity layer 33 are together used as a semiconductor layer 40; and a second vertical MOS transistor 20 formed in a second region A2, which is adjacent to the first region A1 in a plan view of the semiconductor layer 40. The regions to be connected include: a plurality of first source pads 111, which are formed in a first region A1 in a plan view and connected to the first source electrode 11 of the first vertical MOS transistor 10; a first gate pad 119, which is formed in a first region A1 in a plan view and connected to the first gate electrode 19 of the first vertical MOS transistor 10; a plurality of second source pads 121, which are formed in a second region A2 in a plan view and connected to the second source electrode 21 of the second vertical MOS transistor 20; and a second gate pad 129, which is formed in a second region A2 in a plan view. Region A2 is connected to the second gate electrode 29 of the second vertical MOS transistor 20; and a metal layer 41 is formed in contact with the back side of the semiconductor substrate 32, which is the common drain region of the first vertical MOS transistor 10 and the second vertical MOS transistor 20. In a plan view, the semiconductor layer 40 is rectangular. In a plan view, the first vertical MOS transistor 10 and the second vertical MOS transistor 20 are arranged in a first direction. In a plan view, the semiconductor layer 40 has a third region that does not overlap with the first region A1 and the second region A2. In plan view, region A3, first region A1 and second region A2 are one and the other that divide the area of ​​semiconductor layer 40, excluding third region A3, into two equal parts in area. In plan view, the center of third region A3 is located on central line 90, which is a straight line that divides semiconductor layer 40 into two equal parts in a first direction and is orthogonal to the first direction. In plan view, semiconductor layer 40 has a drain pad 151 connected to a common drain region. In plan view, drain pad 151 is configured to be surrounded in third region A3.

[0215] With the above configuration, the number of drain pads 151 required to form the secondary path can be reduced to the minimum necessary number. That is, by having only one drain pad 151, the area of ​​the third region A3 can be reduced compared to the case with multiple drain pads, thereby suppressing the increase in on-resistance on the main path caused by having a secondary path as much as possible.

[0216] Furthermore, in the plan view of semiconductor layer 40, since the third region A3 of semiconductor layer 40 can be disposed on the central line 90 of semiconductor layer 40, by flexibly applying this region, which originally does not contribute to the conduction of the main path, as a region for disposing of drain pad 151, the increase in the on-resistance of the main path can be suppressed compared to disposing the third region A3 at a position other than on the central line 90 in the plan view of semiconductor layer 40.

[0217] Furthermore, in the plan view of semiconductor layer 40, since the center of the third region A3 is positioned on the central line 90 of semiconductor layer 40, even with the third region A3 (drain pad 151) provided, it is not difficult to prevent the first active region 112 and the second active region 122 from having the same area and shape. Therefore, there are fewer instances of bias in the bidirectional electrical characteristics and heat dissipation between transistor 10 and transistor 20.

[0218] Since the main current of semiconductor device 1 is bidirectional, it is desirable that transistors 10 and 20 be configured with pads that are linearly symmetrical about the boundary line 90C as the axis of symmetry, or point-symmetrical about the center of semiconductor layer 40, as shown in the above configuration. This minimizes the likelihood of biases in electrical characteristics and heat dissipation due to different main current directions. For example, in lithium-ion battery packs for smartphones, tablets, etc., if a protection circuit using semiconductor device 1 is incorporated, no special design is needed regarding the conduction direction of semiconductor device 1, whether charging or discharging.

[0219] use Figure 6A as well as Figure 6B The semiconductor device 2 according to the comparative example of Embodiment 1 will be described. Since the same components as those in the semiconductor device 1 in the semiconductor device 2 according to the comparative example have already been described, they will be given the same reference numerals and detailed descriptions will be omitted.

[0220] In semiconductor device 2, the third region A3 under the plan view of semiconductor layer 40 has a third vertical MOS transistor 30 (hereinafter also referred to as transistor 30). Therefore, semiconductor device 2 is a triple-structure semiconductor device 2 that equips three vertical MOS transistors (transistor 10, transistor 20, transistor 30) with separate control functions in one device.

[0221] The transistor 30 is configured the same as the transistor 10 or the transistor 20. The semiconductor device 2 does not have the drain pad 151 and drain lead-out region 58 that are present in the semiconductor device 1 according to Embodiment 1.

[0222] Transistor 30 has a third source pad 131 and a third gate pad 139 located on the surface (third region A3) of semiconductor layer 40. The drain region of transistor 30 is common to the drain regions of transistor 10 and transistor 20.

[0223] Figure 6B This illustrates the comparison between semiconductor device 2 and... Figure 5A The circuit diagram shown is an application example of a protection circuit that is also applicable to lithium-ion battery 5. Figure 6B In the middle, the main function and implementation method of semiconductor device 2 (1) Figure 5A The main function of the semiconductor device 1 involved is the same. Furthermore, the secondary path of the semiconductor device 2 involved in the comparative example is the path where current flows from the first source electrode 11 of transistor 10 through the interior of semiconductor device 2 to the third source electrode 31 of transistor 30. Alternatively, it is the path where current flows from the second source electrode 21 of transistor 20 through the interior of semiconductor device 2 to the third source electrode 31 of transistor 30.

[0224] exist Figure 6B In this embodiment, the conduction control of the secondary path of semiconductor device 2 is controlled by a control signal provided from control IC4 to the third gate electrode 39 of transistor 30. That is, the semiconductor device 2 according to the comparative example has the function of controlling the conduction of the secondary path. Therefore, in embodiment 1 ( Figure 5A The external switching element S1 required in the previous step is not needed here.

[0225] Compared to the secondary path in the semiconductor device 2 of the comparative example, the secondary path in the semiconductor device 1 according to Embodiment 1 does not have control functions in the secondary path, thus reducing the area occupied by this part of the semiconductor device 1. Alternatively, this part can be used as the main path, thereby increasing the area of ​​the main path and reducing the on-resistance of the main path.

[0226] Figures 7A to 7D , Figures 8A to 8D , Figure 9A , Figure 9B , Figures 10A to 10C This is a plan view showing an example of the pad configuration that satisfies the conditions of the semiconductor device 1 according to Embodiment 1.

[0227] like Figures 7A to 7DAs shown, the center of the third region A3 is located on the central line 90 of the semiconductor layer 40 in the plan view of the semiconductor layer 40. The third region A3 is configured such that the first region A1 and the second region A2 are not sandwiched between the edge of the third region A3 and the outer periphery of the semiconductor layer 40 that is parallel to the first direction and closest to the third region A3. The drain pad 151 can be configured to be surrounded in the third region A3.

[0228] With the above configuration, in a plan view of the semiconductor layer 40, the drain pad 151 can be positioned as close as possible to the outer periphery of the semiconductor layer 40. This reduces the likelihood of poor solder bonding caused by warping of the semiconductor device 1 compared to when the drain pad 151 is positioned at the center of the semiconductor layer 40.

[0229] The warping of semiconductor layer 1 will be explained below. As a means of reducing the on-resistance of semiconductor device 1, the warping of semiconductor layer 1 is... Figure 2B Thinning the semiconductor layer 40 (mainly the semiconductor substrate 32), which is the resistive component of the main current flowing vertically through the semiconductor, is effective. Furthermore, thickening the metal layer 41 also helps to reduce on-resistance. In other words, by thinning the semiconductor layer 40 or thickening the metal layer 41 in the semiconductor device 1, the on-resistance is reduced. However, if the thicknesses of the semiconductor layer 40 and the metal layer 41 are similar, the warping that occurs in the semiconductor device 1 at high temperatures will increase due to the differences in the coefficients of thermal expansion and Young's modulus between the semiconductor and the metal.

[0230] The warping of semiconductor device 1 mainly occurs during reflow soldering when it is mounted face-down, under high-temperature conditions of approximately 250°C. In face-down mounting, because the metal layer 41 expands more than the semiconductor layer 40 at high temperatures, it bulges and warps away from the mounting substrate.

[0231] like Figure 11 As shown, when semiconductor device 1 warps, it is not conducive to the mounting of semiconductor device 1. There may be insufficient solder near the center of semiconductor device 1, which corresponds to the protrusion, and poor bonding (insufficient solder distribution) may occur. However, in the outer peripheral area of ​​semiconductor device 1, the force pressing towards the mounting substrate due to warping increases, and sometimes solder overflows from the area where it should be (solder overflow).

[0232] When the semiconductor layer 40 is rectangular, due to the warping effect that occurs in the semiconductor device 1, the bending of the semiconductor layer 40 is greatest in the direction parallel to the long side, and there is also some bending in the direction parallel to the short side.

[0233] The warping of semiconductor device 1 caused by the high temperature during reflow mounting is due to the central portion of semiconductor layer 40 bulging away from the mounting substrate. While there is a possibility of poor bonding near the center of semiconductor device 1, which corresponds to the bulge, due to insufficient solder, this can be mitigated by… Figures 7A to 7D The configuration shown reduces the likelihood of poor solder joints due to warping of the semiconductor device 1, since the drain pad 151 is disposed on the outer periphery of the semiconductor layer 40, compared to the case where the drain pad 151 is disposed on the central portion of the semiconductor layer 40.

[0234] Especially Figure 7B , Figure 7C , Figure 7D As shown, when the semiconductor layer 40 is a rectangular shape with the direction orthogonal to the first direction as the long side, poor solder bonding can be effectively prevented.

[0235] like Figures 8A to 8D As shown, the third region A3 can be configured such that its center is located on the central line of the semiconductor layer 40 in a plan view of the semiconductor layer 40 and coincides with the intersection of the two diagonals of the semiconductor layer 40, and the drain pad 151 is surrounded in the third region A3.

[0236] Through the above composition, and Figures 7A to 7D Compared to the pad configuration shown, this mounting defect can suppress solder overflow caused by warping of the semiconductor device 1 during high-temperature reflow mounting.

[0237] The warping of the semiconductor device 1 that occurs at high temperatures during reflow mounting is a warping that bends in a direction parallel to the long side of the semiconductor layer 40. Therefore, in the regions near the short side on one side of the semiconductor layer 40 and near the short side on the other side, the solder is not pressed towards the central part of the semiconductor device 1 but towards the mounting substrate, resulting in solder overflow and other mounting defects.

[0238] However, by making semiconductor device 1 become Figures 8A to 8D The configuration shown, since the drain pad 151 is disposed in the central portion of the semiconductor layer 40, can suppress poor installation caused by solder overflow due to warping of the semiconductor device 1, compared to the case where the drain pad 151 is disposed in the outer peripheral portion of the semiconductor layer 40.

[0239] Especially Figure 8D When the semiconductor layer 40 shown is a rectangular shape with the direction orthogonal to the first direction as the long side, it can effectively prevent poor installation such as solder overflow compared to the case where the drain pad 151 is configured to be closest to the outer periphery of the semiconductor layer 40.

[0240] In addition to the above configuration, in the plan view of semiconductor layer 40, the first gate pad 119, the second gate pad 129 and the drain pad 151 can be circles with the same diameter, and can be the pad with the smallest area among the pads provided by semiconductor layer 40.

[0241] With the above configuration, in a plan view of semiconductor layer 40, the area of ​​the region that does not contribute to the conduction of the main path of semiconductor device 1 can be minimized. Therefore, the increase in the on-resistance of the main path due to the presence of a secondary path can be suppressed.

[0242] Additionally, drain pad 151 is not affected. Figures 7A to 7D as well as Figures 8A to 8D Limited by the circle shown. It could also be... Figure 9A as well as Figure 9B The shape shown is roughly rectangular. "Roughly rectangular" is a general term that includes not only rectangles with rectangular ends, but also rectangles with semi-circular ends or polygonal shapes.

[0243] exist Figure 9A , Figure 9B In the plan view of semiconductor layer 40, the first gate pad 119 and the second gate pad 129 are circles with the same diameter, and the first gate pad 119, the second gate pad 129 and the drain pad 151 are arranged in the same strip area.

[0244] pass Figure 9A The configuration shown, by placing the first gate pad 119, the second gate pad 129, and the drain pad 151, which obstruct the bidirectional flow of main current along the first direction in the plan view, within the same width along the first direction, prevents them from becoming factors that obstruct the flow of main current. Furthermore, through... Figure 9B The configuration shown prevents the first gate pad 119, the second gate pad 129, and the drain pad 151 from becoming factors that increase the on-resistance of the main current because the first gate pad 119, the second gate pad 129, and the drain pad 151 can be configured in regions that do not contribute to the conduction of the main path.

[0245] And, as Figures 10A to 10C As shown, in Figures 7A to 7D Based on the embodiment, in the plan view of the semiconductor layer 40, the semiconductor layer 40 is rectangular in shape, the drain pad 151 is approximately rectangular in shape, and the length direction of the drain pad 151 can be parallel to the central line 90 of the semiconductor device 1 and the long side direction of the semiconductor layer 40.

[0246] In the plan view of semiconductor layer 40, since there are many parts where the central line 90 and the boundary line 90C coincide, the above configuration allows the third region A3 of semiconductor layer 40, which is not conducive to the conduction of the main path, to be flexibly used as a region for configuring the drain pad 151, thereby suppressing the increase of the conduction resistance of the main path.

[0247] Furthermore, it can suppress solder overflow caused by warping of the semiconductor device 1 during the high temperature of reflow mounting, resulting in mounting defects. When the semiconductor layer 40 is rectangular with its long side perpendicular to the first direction, if the drain pad 151 is approximately rectangular in its length direction parallel to the long side direction of the semiconductor layer 40, then the length direction of the drain pad 151 is parallel to the direction in which the solder is squeezed due to warping of the semiconductor device 1 during the high temperature of reflow mounting. Therefore, solder overflow can be suppressed, thereby mitigating the impact of warping of the semiconductor device 1 during the high temperature of reflow mounting on mounting defects.

[0248] (Implementation Method 2)

[0249] The semiconductor device 1A according to Embodiment 2 will be described below. The semiconductor device 1A according to Embodiment 2 is obtained by modifying a part of the configuration of the semiconductor device 1 according to Embodiment 1. Regarding the semiconductor device 1A according to Embodiment 2, the same components as those of the semiconductor device 1 are given the same reference numerals as those already described and detailed descriptions are omitted. Here, the description will focus on the differences from the semiconductor device 1.

[0250] Figure 12A This is a plan view showing an example of the pad configuration of the semiconductor device 1A according to Embodiment 2. The size and shape of the semiconductor device 1A are illustrative, except that its shape is rectangular. Furthermore, the size, shape, and configuration of the pads are also illustrative. Figure 12A The cross-section at point II shows an example of the pad configuration of the semiconductor device 1 according to Embodiment 1. Figure 2A Section II Figure 1 Equivalent.

[0251] Figure 1 The transistor 10 of the semiconductor device 1 according to Embodiment 1 corresponds to Figure 12B The first vertical MOS transistor 10A (hereinafter also referred to as transistor 10A) in the semiconductor device 1A according to Embodiment 2 shown.

[0252] same, Figure 1 The transistor 20 of the semiconductor device 1 according to Embodiment 1 corresponds to Figure 12B The second vertical MOS transistor 20A (hereinafter also referred to as transistor 20A) in the semiconductor device 1A according to Embodiment 2 shown.

[0253] Figure 2A In Embodiment 1, the first region A1 and the second region A2 of the semiconductor device 1 correspond to respectively Figure 12A The first region A1A and the second region A2A in the semiconductor device 1A according to Embodiment 2 shown.

[0254] and, Figure 2A In Embodiment 1, the plurality of first source pads 111 and first gate pads 119 of the semiconductor device 1 correspond to respectively Figure 12A The semiconductor device 1A shown in Embodiment 2 contains a plurality of first source pads 111A and first gate pads 119A.

[0255] same, Figure 2A In Embodiment 1, the plurality of second source pads 121 and second gate pads 129 of the semiconductor device 1 correspond to respectively Figure 12A The semiconductor device 1A according to Embodiment 2 shown has a plurality of second source pads 121A and a second gate pad 129A.

[0256] like Figure 12A as well as Figure 1 As shown, semiconductor device 1A includes a semiconductor layer 40, a metal layer 41, a transistor 10A formed in a first region A1A within the semiconductor layer 40, and a transistor 20A formed in a second region A2A within the semiconductor layer 40. Compared to semiconductor device 1 according to Embodiment 1, the semiconductor device 1A according to Embodiment 2 does not have a third region A3.

[0257] like Figure 12A and Figure 12B as well as Figure 1 As shown, in addition to the constituent elements of the first region A1 of the semiconductor device 1 according to Embodiment 1, the first region A1A of the semiconductor device 1 according to Embodiment 2 also includes a first drain electrode 51A.

[0258] Similarly, in addition to having the constituent elements of the second region A2 of the semiconductor device 1 according to Embodiment 1, the second region A2A of the semiconductor device 1 also has a second drain electrode 61A.

[0259] exist Figure 12A In the middle, the cross-section at II-II, that is, the cross-section of the first drain electrode 51A, is... Figure 3A Equivalent. Furthermore, the cross-section of the second drain electrode 61A is also the same.

[0260] Figure 3A The portion 52 of the semiconductor device 1 in Embodiment 1 corresponds to portion 52A and portion 62A in the semiconductor device 1A in Embodiment 2.

[0261] and, Figure 3A The portion 53 of the semiconductor device 1 in Embodiment 1 corresponds to portion 53A and portion 63A in the semiconductor device 1A in Embodiment 2.

[0262] same, Figure 3A The drain electrode 51 of the semiconductor device 1 according to Embodiment 1, which is composed of portions 52 and 53, corresponds to the first drain electrode 51A composed of portions 52A and 53A and the second drain electrode 61A composed of portions 62A and 63A in the semiconductor device 1A according to Embodiment 2.

[0263] and, Figure 3A The drain lead-out region 58 of the semiconductor device 1 according to Embodiment 1 corresponds to the first drain lead-out region 58A and the second drain lead-out region 68A in the semiconductor device 1A according to Embodiment 2.

[0264] A first drain lead-out region 58A of a first conductivity type is formed within the low-concentration impurity layer 33 of the first region A1A, comprising impurities of a first conductivity type with a higher concentration than those of impurities of the first conductivity type in the low-concentration impurity layer 33. Alternatively, the first drain lead-out region 58A may be formed within the low-concentration impurity layer 33 to a depth reaching the semiconductor substrate 32.

[0265] The first drain electrode 51A is composed of a portion 52A and a portion 53A, with portion 52A connected to the first drain lead-out region 58A via portion 53A.

[0266] A portion 52A of the first drain electrode 51A is a layer that bonds with the solder during reflow when mounted face down. As a non-limiting example, it may be made of one or more metallic materials including nickel, titanium, tungsten, and palladium. A plating layer such as gold may be applied to the surface of portion 52A.

[0267] A portion 53A of the first drain electrode 51A is a layer that contacts portion 52A and the first drain lead-out region 58A. Therefore, the first drain electrode 51A has the same potential as the common drain region of transistors 10A and 20A. Furthermore, as a non-limiting example, it can be made of one or more metallic materials including aluminum, copper, gold, and silver.

[0268] like Figure 3A as well as Figure 12BAs shown, the low-concentration impurity layer 33 is covered by an interlayer insulating layer 34 with an opening, and a portion 53A of the first drain electrode 51A is provided, which is connected to the first drain lead-out region 58A through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 53A of the first drain electrode 51A are covered by a passivation layer 35 with an opening, and a portion 52A is provided, which is connected to the portion 53A of the first drain electrode 51A through the opening of the passivation layer 35.

[0269] Therefore, the first drain pad 151A refers to the area where the first drain electrode 51A is partially exposed on the surface of the semiconductor device 1A, which is the so-called terminal portion.

[0270] Similarly, a second drain lead-out region 68A of a first conductivity type is formed within the low-concentration impurity layer 33 of the second region A2A, containing impurities of the first conductivity type with a higher concentration than those of the first conductivity type impurities in the low-concentration impurity layer 33. Furthermore, the second drain lead-out region 68A may also be formed within the low-concentration impurity layer 33 to a depth reaching the semiconductor substrate 32.

[0271] The second drain electrode 61A is composed of a portion 62A and a portion 63A, with portion 62A connected to the second drain lead-out region 68A via portion 63A.

[0272] A portion 62A of the second drain electrode 61A is a layer that bonds with the solder during reflow in a face-down mounting configuration. As a non-limiting example, it may be made of one or more metallic materials, including nickel, titanium, tungsten, and palladium. A plating layer such as gold may be applied to the surface of portion 62A.

[0273] A portion 63A of the second drain electrode 61A is a layer connected to portion 62A and the second drain lead-out region 68A. Therefore, the second drain electrode 61A has the same potential as the common drain region of transistors 10A and 20A. Furthermore, as a non-limiting example, it can be made of one or more metallic materials including aluminum, copper, gold, and silver.

[0274] like Figure 3A as well as Figure 12B As shown, the low-concentration impurity layer 33 is covered by an interlayer insulating layer 34 with an opening, and a portion 63A of the second drain electrode 61A is provided, which is connected to the second drain lead-out region 68A through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 63A of the second drain electrode 61A are covered by a passivation layer 35 with an opening, and a portion 62A is provided, which is connected to the portion 63A of the second drain electrode 61A through the opening of the passivation layer 35.

[0275] Therefore, the second drain pad 161A refers to the area where the second drain electrode 61A is partially exposed on the surface of the semiconductor device 1A, which is the so-called terminal portion.

[0276] like Figure 1 , Figure 3A , Figure 12A As shown, transistor 10A has a plurality of first source pads 111A, first gate pads 119A, and first drain pads 151A on the surface of semiconductor layer 40, which are bonded to the mounting substrate via bonding material when mounted face down. Furthermore, transistor 20A has a plurality of second source pads 121A, second gate pads 129A, and second drain pads 161A on the surface of semiconductor layer 40, which are bonded to the mounting substrate via bonding material when mounted face down.

[0277] like Figure 1 as well as Figure 12A As shown, in the plan view, the semiconductor device 1A and the semiconductor layer 40 are rectangular in shape. Additionally, in... Figure 12A Although the semiconductor device 1A and the semiconductor layer 40 are rectangular, they can also be square.

[0278] In a plan view, the direction in which the first region A1A and the second region A2A are arranged in a direction parallel to the outer periphery of the semiconductor device 1A is defined as the first direction. In a plan view, the arrangement of the first region A1A and the second region A2A in the first direction means that the first region A1A and the second region A2A are in the most opposite state in the first direction.

[0279] "Most relative in the first direction" means that, in a plan view, the portion of the boundary line 90C between the first region A1A and the second region A2A that is orthogonal to the first direction is the longest. For example, in a plan view, if the boundary line 90C is curved, the direction orthogonal to the direction in which the sum of the line segments forming the boundary line 90C is the longest is called the first direction.

[0280] like Figure 12A As shown, in the plan view of semiconductor layer 40, the first region A1A and the second region A2A are adjacent to each other, which are one side and the other side that divide semiconductor layer 40 into two equal parts in area.

[0281] like Figure 12A As shown, the central line 90 is a line that bisects the semiconductor layer 40 in the first direction in a plan view of the semiconductor layer 40. Therefore, the central line 90 is a straight line in a direction orthogonal to the first direction in the plan view of the semiconductor layer 40.

[0282] Furthermore, in the plan view of semiconductor layer 40, the midpoint of the line segment connecting the center of the first gate pad 119A of transistor 10A and the center of the second gate pad 129A of transistor 20A is located on the boundary line 90C of semiconductor device 1A.

[0283] Furthermore, in the plan view of semiconductor layer 40, the midpoint of the line segment connecting the center of the first drain pad 151A of transistor 10A and the center of the second drain pad 161A of transistor 20A is located on the boundary line 90C of semiconductor device 1A.

[0284] And as Figure 12A As shown, the first source pad 111A is configured such that no portion is sandwiched between the first gate pad 119A and the first drain pad 151A. Therefore, the first gate pad 119A and the first drain pad 151A are arranged adjacent to each other.

[0285] Similarly, the second source pad 121A is configured such that no portion is sandwiched between the second gate pad 129A and the second drain pad 161A. Therefore, the second gate pad 129A and the second drain pad 161A are arranged adjacent to each other.

[0286] like Figure 12A As shown, in a plan view of semiconductor layer 40, the first gate pad 119A and the second gate pad 129A of semiconductor device 1A have the same shape and the same area. Furthermore, the first drain pad 151A and the second drain pad 161A have the same shape and the same area.

[0287] Other examples Figure 12A As shown, the first gate pad 119A, the second gate pad 129A, the first drain pad 151A, and the second drain pad 161A can also have the same shape and the same area.

[0288] The main current and main path of the semiconductor device 1A involved in Embodiment 2 are the same as those of the semiconductor device 1 involved in Embodiment 1.

[0289] Figure 12B This is a cross-sectional view showing the secondary current flowing through semiconductor device 1A. The secondary current of semiconductor device 1A is the same as the secondary current of semiconductor device 1 according to Embodiment 1. It is controlled by an external switching element connected in series with the first drain electrode 51A and the second drain electrode 61A of semiconductor device 1A, and is therefore a relatively small current compared to the main current. The conduction path of the secondary current of semiconductor device 1A will be described below.

[0290] In semiconductor device 1A, when a high voltage is applied to the first source electrode 11 and a low voltage is applied to the first drain electrode 51A and the second drain electrode 61A, and an external switching element connected in series with the first drain electrode 51A and the second drain electrode 61A is turned on, a secondary current flows through the path of first source electrode 11 - first connection portion 18a - first body region 18 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - low concentration impurity layer 33 - first drain lead-out region 58A - first drain electrode 51A, and semiconductor device 1A is turned on. Alternatively, at this time, a secondary current can also flow through the path of first source electrode 11 - first connection portion 18a - first body region 18 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - low concentration impurity layer 33 - second drain lead-out region 68A - second drain electrode 61A.

[0291] Furthermore, when a high voltage is applied to the first source electrode 11 and a low voltage is applied to the first drain electrode 51A and the second drain electrode 61A, making the external switching element conduct, and when a voltage above a threshold is applied to the first gate electrode 19 with the first source electrode 11 as a reference, a conduction channel is formed near the first gate insulating film 16 in the first body region 18, so that a secondary current flows from the first source electrode 11 - the first source region 14 - the conduction channel formed in the first body region 18 - the low concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low concentration impurity layer 33, to the first drain lead-out region 58A - the first drain electrode 51A, or to the second drain lead-out region 68A - the second drain electrode 61A, and the semiconductor device 1A becomes conduction-enabled.

[0292] Similarly, when a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first drain electrode 51A and the second drain electrode 61A, making the external switching element connected in series with the first drain electrode 51A and the second drain electrode 61A in a conducting state, a secondary current flows through the path of the second source electrode 21 - second connection portion 28a - second body region 28 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - low concentration impurity layer 33 - second drain lead-out region 68A - second drain electrode 61A, and the semiconductor device 1A becomes conducting. Alternatively, at this time, a secondary current can also flow through the path of the second source electrode 21 - second connection portion 28a - second body region 28 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - low concentration impurity layer 33 - first drain lead-out region 58A - first drain electrode 51A.

[0293] Furthermore, when a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first drain electrode 51A and the second drain electrode 61A, making the external switching element conduct, and when a voltage above a threshold is applied to the second gate electrode 29 with the second source electrode 21 as a reference, a conduction channel is formed near the second gate insulating film 26 in the second body region 28, so that a secondary current flows from the second source electrode 21 - second source region 24 - conduction channel formed in the second body region 28 - low concentration impurity layer 33 - semiconductor substrate 32 - metal layer 41 - semiconductor substrate 32 - low concentration impurity layer 33, to the second drain lead-out region 68A - second drain electrode 61A, or to the first drain lead-out region 58A - first drain electrode 51A, and the semiconductor device 1A becomes conduction-enabled.

[0294] The conduction paths through which the secondary current flows are the secondary paths of semiconductor device 1A. The secondary paths of semiconductor device 1A are controlled by making an external switching element, connected in series with the first drain electrode 51A and the second drain electrode 61A, either in a conducting or non-conducting state. When the switching element is in a conducting state, the secondary paths of semiconductor device 1A are in a conducting state.

[0295] When the main path is turned on, the external switching element connected in series with the first drain electrode 51A and the second drain electrode 61A must be controlled to be turned off. Therefore, the secondary path is turned off, and only the main path is turned on.

[0296] in addition, Figure 12C It shows that the configuration is... Figure 12A A magnified plan view showing the positions of the first drain pad 151A and the first gate pad 119A. Figure 12C An example of the shape of portion 13 of the first source electrode 11, portion 53A of the first drain electrode 51A, the first drain pad 151A, the first gate electrode 19, the first gate pad 119A, the first EQR, and the first gate resistor element in a plan view of the semiconductor layer 40 is shown.

[0297] The gate resistor element is electrically connected to the gate electrode and is designed to prevent transistor damage and provide protection when excessive voltage is applied to the gate electrode. In other words, it is a component designed to improve ESD (Electrostatic Discharge) withstand capability.

[0298] Furthermore, it is not necessary to provide a gate resistor element and an EQR in the semiconductor device disclosed herein, and it is also possible to omit the gate resistor element and the EQR. Either way is acceptable.

[0299] exist Figure 12C In order to clearly show the structure of the upper surface of the semiconductor layer 40, which is not actually visible, the passivation layer 35 and the interlayer insulating layer 34 are omitted from the illustration as they are considered transparent. The illustrations of the first source region 14 and the first drain lead-out region 58A are also omitted.

[0300] Although the illustration is omitted, the portion 23 of the second source electrode 21, the portion 63A of the second drain electrode 61A, the second drain pad 161A, the second gate electrode 29, the second gate pad 129A, the second EQR, and the second gate resistor element are similar to... Figure 12C The portion 13 of the first source electrode 11, the portion 53A of the first drain electrode 51A, the first drain pad 151A, the first gate electrode 19, the first gate pad 119A, the first EQR, and the first gate resistor element shown are linearly symmetrical about the central line 90 as the axis of symmetry.

[0301] The area directly below and near the first drain electrode 51A, and the area directly below and near the second drain electrode 61A, are regions that do not contribute to the conduction of the main path. Here, "nearby area" refers to the region along the outer periphery of the first drain electrode 51A and the second drain electrode 61A, or more specifically... Figure 12C The region between portion 53A of the first drain electrode 51A and portion 13 of the first source electrode 11, and the region between portion 63A of the second drain electrode 61A and portion 23 of the second source electrode 21 (omitted in the figure).

[0302] In other words, the regions directly below and near the first gate electrode 19, the regions directly below and near the first drain electrode 51A, the regions directly below and near the second gate electrode 29, and the regions directly below and near the second drain electrode 61A are areas in the semiconductor device 1A that are necessary for the semiconductor device 1A to function. However, within a limited device area, these areas are desirable to be as small as possible in order to reduce the on-resistance of the main path of the semiconductor device 1A.

[0303] Other examples Figure 12C As shown, in the plan view of semiconductor layer 40, a first gate resistor element can also be disposed between the first gate pad 119A and the first drain pad 151A. Furthermore, a portion 53A of the first drain electrode 51A can also be directly connected to the first EQR.

[0304] Although the illustration is omitted, similarly, in the plan view of semiconductor layer 40, a second gate resistor element can be disposed between the second gate pad 129A and the second drain pad 161A. Furthermore, a portion 63A of the second drain electrode 61A can also be directly connected to the second EQR.

[0305] The features of the semiconductor device 1A in this disclosure described above are as follows.

[0306] The semiconductor device 1A disclosed herein is a chip-sized packaged semiconductor device capable of being mounted face-down. The semiconductor device 1A includes: a semiconductor substrate 32; a low-concentration impurity layer 33 formed on the semiconductor substrate 32; a first vertical MOS transistor 10A formed in a first region A1A of the semiconductor layer 40 when the semiconductor substrate 32 and the low-concentration impurity layer 33 are together used as a semiconductor layer 40; a second vertical MOS transistor 20A formed in a second region A2A, the second region A2A being adjacent to the first region A1A in a plan view of the semiconductor layer 40; and a plurality of first source pads 111A in a plan view. A first gate pad 119A is formed in the first region A1A and connected to the first source electrode 11 of the first vertical MOS transistor 10A; a first drain pad 151A is formed in the first region A1A and connected to the first drain electrode 51A of the first vertical MOS transistor 10A; a plurality of second source pads 121A are formed in the second region A2A and connected to the second source electrode 21 of the second vertical MOS transistor 20A; a second gate pad 129A... In plan view, a second drain pad 161A is formed in the second region A2A and connected to the second gate electrode 29 of the second vertical MOS transistor 20A; a second drain pad 161A is formed in the second region A2A and connected to the second drain electrode 61A of the second vertical MOS transistor 20A; and a metal layer 41 is formed in contact with the back side of a semiconductor substrate 32, which is the common drain region of the first vertical MOS transistor 10A and the second vertical MOS transistor 20A. In plan view, the semiconductor layer 40 is rectangular. In plan view, the first region A1A and the second region A2A are equal in area to the semiconductor layer 40. In a plan view, the midpoint of the line segment connecting the center of the first gate pad 119A and the center of the second gate pad 129A is located on the boundary line 90C between the first region A1A and the second region A2A. In a plan view, the midpoint of the line segment connecting the center of the first drain pad 151A and the center of the second drain pad 161A is located on the boundary line 90C. The first source pad 111A is configured such that no part of it is sandwiched between the first gate pad 119A and the first drain pad 151A, and the second source pad 121A is configured such that no part of it is sandwiched between the second gate pad 129A and the second drain pad 161A.

[0307] Figures 13A-13C , Figures 14A to 14D , Figure 15A , Figure 15B , Figures 16A to 16D This is a plan view showing an example of the pad configuration that satisfies the conditions of the semiconductor device 1A according to Embodiment 2.

[0308] With the above configuration, in a plan view of semiconductor layer 40, the first gate pad 119A and the first drain pad 151A are arranged adjacent to each other, and the second gate pad 129A and the second drain pad 161A are arranged adjacent to each other. Although the area around the first gate pad 119A and the area around the first drain pad 151A is the first active region 112, it is originally a region where the current density of the main current is relatively difficult to increase. Therefore, by arranging the first gate pad 119A and the first drain pad 151A adjacent to each other, the usable area of ​​the first active region 112 can be expanded compared to arranging them far apart. Similarly, by arranging the second gate pad 129A and the second drain pad 161A adjacent to each other, the usable area of ​​the second active region 122 can be expanded compared to arranging them far apart. Therefore, the increase in the on-resistance of the main path due to the presence of a secondary path can be suppressed as much as possible.

[0309] Furthermore, in the plan view of semiconductor layer 40, the first gate pad 119A and the second gate pad 129A, as well as the first drain pad 151A and the second drain pad 161A, can be configured to be linearly symmetrical about the boundary line 90C as the axis of symmetry, or they can be configured to be point-symmetrical about the center of semiconductor layer 40 as the center of symmetry. Because the first gate pad 119A, the first drain pad 151A, the second gate pad 129A, and the second drain pad 161A can be configured in this way, even with a secondary path, it is not difficult to prevent the first active region 112 and the second active region 122 from having the same area and shape. Therefore, the bias in the bidirectional electrical characteristics and heat dissipation between transistor 10A and transistor 20A will be less.

[0310] like Figures 14A to 14D As shown, the first drain pad 151A and the first gate pad 119A can be arranged in a direction parallel to the boundary line 90C. The first drain pad 151A can be configured such that no part of any other pad is sandwiched between the first drain pad 151A and the edge closest to the first drain pad 151A in the outer periphery of the semiconductor layer 40.

[0311] Similarly, the second drain pad 161A and the second gate pad 129A can be arranged in a direction parallel to the boundary line 90C. The second drain pad 161A can be configured such that no part of any other pad is sandwiched between the second drain pad 161A and the edge closest to the second drain pad 161A in the outer periphery of the semiconductor layer 40.

[0312] With the above configuration, in a plan view of the semiconductor layer 40, the first drain pad 151A, the first gate pad 119A, the second drain pad 161A, and the second gate pad 129A can be arranged close to the outer periphery of the semiconductor layer 40. Therefore, compared with the case where the first drain pad 151A, the first gate pad 119A, the second drain pad 161A, and the second gate pad 129A are arranged at the center of the semiconductor layer 40, the possibility of poor bonding with the solder due to warping of the semiconductor device 1A can be reduced.

[0313] like Figure 14A As shown, for example, the arrangement of the first drain pad 151A and the first gate pad 119A, and the arrangement of the second drain pad 161A and the second gate pad 129A, can also be reversed. In this case, although the first gate pad 119A and the second gate pad 129A, and the first drain pad 151A and the second drain pad 161A are not configured to be linearly symmetrical about the boundary line 90C as the axis of symmetry, they can be configured to be point-symmetrical about the center of the semiconductor layer 40.

[0314] In addition, the first drain pad 151A and the second drain pad 161A are not affected by Figures 14A to 14D Limited by the circle shown. It could also be... Figure 15A The shape shown is roughly rectangular.

[0315] like Figure 15A as well as Figure 15B As shown, the first drain pad 151A and the first gate pad 119A can be configured to be arranged in a direction orthogonal to the boundary line 90C, and the second drain pad 161A and the second gate pad 129A can be configured to be arranged in a direction orthogonal to the boundary line 90C. The midpoint of the line segment connecting the center of the first drain pad 151A and the center of the second drain pad 161A can coincide with the center of the semiconductor layer 40.

[0316] With the above configuration, the first drain pad 151A and the second drain pad 161A can be configured to be linearly symmetrical about the boundary line 90C, thus reducing the bias in the bidirectional electrical characteristics and heat dissipation between transistors 10A and 20A. Furthermore, compared to the case where the first drain pad 151A and the first gate pad 119A are arranged in a direction parallel to the boundary line 90C, since they can overlap at least a portion of the first direction through which the main current flows, factors that hinder the main current can be mitigated.

[0317] And can be as Figures 16A to 16D As shown, the first drain pad 151A can be configured as a first stripe equally spaced from the plurality of first source pads 111A. In the direction forming the first stripe, the first drain pad 151A and the plurality of first source pads 111A can have the same width. The second drain pad 161A can be configured as a second stripe equally spaced from the plurality of second source pads 121A. In the direction forming the second stripe, the second drain pad 161A and the plurality of second source pads 121A can have the same width. Furthermore, the first stripe and the second stripe can be the same stripe shape.

[0318] In this configuration, one of the plurality of first source pads 111A can be replaced with a first drain pad 151A, and one of the plurality of second source pads 121A can be replaced with a second drain pad 161A. Therefore, when changing from a usage method that does not require a secondary path to a usage method that requires a secondary path, the semiconductor device 1A can be used without making significant changes to the wiring configuration of the mounting substrate.

[0319] (Implementation Method 3)

[0320] The semiconductor device 1B according to Embodiment 3 will be described below. The semiconductor device 1B according to Embodiment 3 is obtained by modifying a part of the semiconductor device 1A according to Embodiment 2. Regarding the constituent elements of the semiconductor device 1B according to Embodiment 3 that are the same as those of the semiconductor device 1A, they are given the same reference numerals as the constituent elements that have been described, and detailed descriptions are omitted. The following description focuses on the differences from the semiconductor device 1A.

[0321] Figure 17A This is a plan view showing an example of the pad configuration of the semiconductor device 1B according to Embodiment 3. Except that the semiconductor device 1B is rectangular, the size and shape of the rest are just examples. Furthermore, the size, shape, and configuration of the pads are also examples. Figure 17A Section II and Figure 1 They are equivalent. Furthermore, Figure 17A Section II-II and Figure 3A Similarly, the constituent elements of the semiconductor device 1B according to Embodiment 3 are the same as those of the semiconductor device 1A according to Embodiment 2.

[0322] like Figure 17A as well as Figure 1 As shown, the semiconductor device 1B includes: a semiconductor layer 40, a metal layer 41, a transistor 10A formed in a first region A1A within the semiconductor layer 40, and a transistor 20A formed in a second region A2A within the semiconductor layer 40.

[0323] The constituent elements of transistors 10A and 20A in the semiconductor device 1B according to Embodiment 3 are the same as those of transistors 10A and 20A described in the semiconductor device 1A according to Embodiment 2.

[0324] like Figure 17A As shown, in the plan view of semiconductor layer 40, the first region A1A and the second region A2A are adjacent to each other, which are one side and the other side that divide semiconductor layer 40 into two equal parts in area.

[0325] And in Figure 17A In order to distinguish the first region A1A and the second region A2A of the semiconductor layer 40, a dashed line is used to represent the virtual boundary line 90C.

[0326] like Figure 17A As shown, in the plan view of semiconductor layer 40, the midpoint of the line segment connecting the center of the first drain pad 151A and the center of the second drain pad 161A is located on the boundary line 90C of semiconductor device 1B.

[0327] Other examples Figure 17A As shown in one example of the semiconductor device 1B, the midpoint of the line segment connecting the center of the first gate pad 119A and the center of the second gate pad 129A can be located on the boundary line 90C of the semiconductor device 1B.

[0328] Furthermore, in a plan view of the semiconductor layer 40, a portion of a plurality of first source pads 111A may be configured between the first drain pad 151A and the boundary line 90C.

[0329] Similarly, in a plan view of semiconductor layer 40, a portion of a plurality of second source pads 121A may be configured between the second drain pad 161A and the boundary line 90C.

[0330] The main current and main path of the semiconductor device 1B involved in Embodiment 3 are the same as those of the semiconductor device 1 involved in Embodiment 1.

[0331] Furthermore, the secondary current and secondary path of the semiconductor device 1B involved in Embodiment 3 are the same as the secondary current and secondary path of the semiconductor device 1A involved in Embodiment 2.

[0332] The features of the semiconductor device 1B in this disclosure described above are as follows.

[0333] The semiconductor device 1B disclosed herein is a chip-size packaged semiconductor device capable of being mounted face-down. The semiconductor device 1B includes: a semiconductor substrate 32; a low-concentration impurity layer 33 formed on the semiconductor substrate 32; a first vertical MOS transistor 10A formed in a first region A1A of the semiconductor layer 40 when the semiconductor substrate 32 and the low-concentration impurity layer 33 are together used as a semiconductor layer 40; a second vertical MOS transistor 20A formed in a second region A2A, the second region A2A being adjacent to the first region A1A in a plan view of the semiconductor layer 40; and a plurality of first sources. A first source pad 111A is formed in the first region A1A in a plan view and is connected to the first source electrode 11 of the first vertical MOS transistor 10A; a first gate pad 119A is formed in the first region A1A in a plan view and is connected to the first gate electrode 19 of the first vertical MOS transistor 10A; a first drain pad 151A is formed in the first region A1A in a plan view and is connected to the first drain electrode 51A of the first vertical MOS transistor 10A; a plurality of second source pads 121A are formed in the second region A2A in a plan view and are connected to the second vertical MOS transistor. The second source electrode 21 of transistor 20A is connected; the second gate pad 129A, in plan view, is formed in the second region A2A and connected to the second gate electrode 29 of the second vertical MOS transistor 20A; the second drain pad 161A, in plan view, is formed in the second region A2A and connected to the second drain electrode 61A of the second vertical MOS transistor 20A; and a metal layer 41 is formed in contact with the back side of a semiconductor substrate 32, which is the common drain region of the first vertical MOS transistor 10A and the second vertical MOS transistor 20A. In plan view, the semiconductor layer 40... The structure is rectangular. In the plan view, the first region A1A and the second region A2A are one and the other that divide the semiconductor layer 40 into two equal parts in area. In the plan view, the midpoint of the line segment connecting the center of the first drain pad 151A and the center of the second drain pad 161A is located on the boundary line 90C between the first region A1A and the second region A2A. In the plan view, a plurality of first source pads 111A are configured such that at least a portion is sandwiched between the first drain pad 151A and the boundary line 90C, and a plurality of second source pads 121A are configured such that at least a portion is sandwiched between the second drain pad 161A and the boundary line 90C.

[0334] Figures 17B-17D , Figure 18A as well as Figure 18B This is a plan view showing an example of the pad configuration that satisfies the conditions of the semiconductor device 1B according to Embodiment 3.

[0335] With the above configuration, in a plan view of semiconductor layer 40, at least a portion of the plurality of first source pads 111A and at least a portion of the plurality of second source pads 121A are configured such that the first drain pad 151A and the second drain pad 161A are not sandwiched between the plurality of first source pads 111A and the plurality of second source pads 121A and the boundary line 90C. Accordingly, compared to the first drain pad 151A and the second drain pad 161A being configured near the boundary line 90C where the main current density is highest, the flow of the main current is not obstructed, and thus the increase in on-resistance on the main path due to the presence of a secondary path can be suppressed as much as possible.

[0336] Especially Figure 17A , Figure 17C In the middle, along the entire length of the boundary line 90C, the first source pad 111A and the second source pad 121A are arranged opposite each other without any other pads sandwiched between them, thus effectively reducing the on-resistance of the main path.

[0337] like Figure 18A as well as Figure 18B As shown, in a plan view of the semiconductor layer 40, the first drain pad 151A can be positioned closest to the corner formed by two intersecting sides among the four sides constituting the outer periphery of the semiconductor layer 40, and the second drain pad 161A can be positioned closest to another corner diagonally opposite to the corner of the semiconductor layer 40 where the first drain pad 151A is positioned.

[0338] With the above configuration, since the first drain pad 151A and the second drain pad 161A can be positioned closest to the outer periphery of the semiconductor layer 40, the possibility of poor bonding with the solder due to warping of the semiconductor device 1B can be reduced compared to the case where the first drain pad 151A and the second drain pad 161A are positioned in the center of the semiconductor layer 40.

[0339] (Implementation Method 4)

[0340] The semiconductor device 1C according to Embodiment 4 will be described below. The semiconductor device 1C according to Embodiment 4 is obtained by modifying a portion of the semiconductor devices 1A and 1B according to Embodiments 2 and 3. Elements in the semiconductor device 1C according to Embodiment 4 that are the same as those in semiconductor devices 1A and 1B are given the same reference numerals as previously described elements, and detailed descriptions are omitted. The following description focuses on the differences from semiconductor devices 1A and 1B.

[0341] Figure 19A This is a plan view showing an example of the pad configuration of the semiconductor device 1C according to Embodiment 4. Except that the semiconductor device 1C is rectangular, for example, a rectangle with a long side and a short side, the size and shape are just examples. Furthermore, the size, shape, and configuration of the pads are also examples. Figure 19A Section II and Figure 1 They are equivalent. Figure 19A Section II-II and Figure 3A They are equivalent. The constituent elements of the semiconductor device 1C according to Embodiment 4 are the same as those of the semiconductor device 1A according to Embodiment 2 and the semiconductor device 1B according to Embodiment 3.

[0342] like Figure 19A as well as Figure 1 As shown, the semiconductor device 1C includes: a semiconductor layer 40, a metal layer 41, a transistor 10A formed in a first region A1A within the semiconductor layer 40, and a transistor 20A formed in a second region A2A within the semiconductor layer 40.

[0343] The constituent elements of transistors 10A and 20A in the semiconductor device 1C according to Embodiment 4 are the same as those of transistors 10A and 20A described in the semiconductor device 1A according to Embodiment 2 and the semiconductor device 1B according to Embodiment 3.

[0344] like Figure 19A As shown, in the plan view of semiconductor layer 40, the first region A1A and the second region A2A are adjacent to each other, which are one side and the other side that divide semiconductor layer 40 into two equal parts in area.

[0345] Furthermore, in Figure 19A In order to distinguish the first region A1A and the second region A2A of the semiconductor layer 40, the virtual boundary line 90C is represented by a dashed line.

[0346] like Figure 19AAs shown, in a plan view of semiconductor layer 40, the first drain pad 151A and the second drain pad 161A are arranged in a direction orthogonal to the boundary line 90C, and the midpoint of the line segment connecting the center of the first drain pad 151A and the center of the second drain pad 161A is located on the boundary line 90C of semiconductor device 1C.

[0347] Furthermore, in the plan view of the semiconductor layer 40, the first gate pad 119A and the second gate pad 129A are arranged in a direction orthogonal to the boundary line 90C, and the midpoint of the line segment connecting the center of the first gate pad 119A and the center of the second gate pad 129A is located on the boundary line 90C of the semiconductor device 1C.

[0348] Furthermore, in the plan view of the semiconductor layer 40, no other pads are sandwiched between the first drain pad 151A and the second drain pad 161A and one of the short sides of the outer periphery of the rectangular semiconductor layer 40.

[0349] Furthermore, in a plan view of the semiconductor layer 40, no other pads are sandwiched between the first gate pad 119A and the second gate pad 129A and another short side of the outer periphery of the rectangular semiconductor layer 40.

[0350] The main current and main path of the semiconductor device 1C involved in Embodiment 4 are the same as those of the semiconductor device 1 involved in Embodiment 1.

[0351] Furthermore, the secondary current and secondary path of the semiconductor device 1C involved in Embodiment 4 are the same as the secondary current and secondary path of the semiconductor device 1A involved in Embodiment 2 and the semiconductor device 1B involved in Embodiment 3.

[0352] The features of the semiconductor device 1C described above in this disclosure are as follows.

[0353] The semiconductor device 1C disclosed herein is a chip-size packaged semiconductor device capable of being mounted face-down. The semiconductor device 1C includes: a semiconductor substrate 32; a low-concentration impurity layer 33 formed on the semiconductor substrate 32; a first vertical MOS transistor 10A formed in a first region A1A of the semiconductor layer 40 when the semiconductor substrate 32 and the low-concentration impurity layer 33 are together used as a semiconductor layer 40; a second vertical MOS transistor 20A formed in a second region A2A, which is adjacent to the first region A1A in a plan view of the semiconductor layer 40; a first source pad group consisting of a plurality of first source pads 111A formed in the first region A1A in a plan view and connected to the first source electrode 11 of the first vertical MOS transistor 10A; and a first gate pad 119A. A first drain pad 151A is formed in the first region A1A in the plan view and is connected to the first gate electrode 19 of the first vertical MOS transistor 10A; a second source pad group consisting of a plurality of second source pads 121A is formed in the second region A2A in the plan view and is connected to the second source electrode 21 of the second vertical MOS transistor 20A; a second gate pad 129A is formed in the second region A2A in the plan view and is connected to the second gate electrode 29 of the second vertical MOS transistor 20A; a second drain pad 161A is formed in the second region A2A in the plan view and is connected to the second drain electrode 61A of the second vertical MOS transistor 20A.A metal layer 41 is formed in contact with the back side of a semiconductor substrate 32, which is the common drain region of the first vertical MOS transistor 10A and the second vertical MOS transistor 20A. In a plan view, the semiconductor layer 40 is a rectangle with a long side and a short side. In a plan view, the first region A1A and the second region A2A are one and the other that divide the semiconductor layer 40 into two equal parts in area. In a plan view of the semiconductor layer 40, the first drain pad 151A and the second drain pad 161A are arranged in a direction orthogonal to the boundary line 90C, and the line segment connecting the center of the first drain pad 151A and the center of the second drain pad 161A is... The midpoint of the first gate pad 119A and the second gate pad 129A are located on the boundary line 90C. The midpoint of the line segment connecting the center of the first gate pad 119A and the center of the second gate pad 129A is located on the boundary line 90C. In the plan view, no other pads are sandwiched between the first drain pad 151A and the second drain pad 161A and one of the short sides of the outer periphery of the rectangular semiconductor layer 40. In the plan view, no other pads are sandwiched between the first gate pad 119A and the second gate pad 129A and the other short side of the outer periphery of the rectangular semiconductor layer 40.

[0354] Figure 19B This is a plan view showing another configuration example of the pads that meet the conditions of the semiconductor device 1C according to Embodiment 4.

[0355] With the above configuration, in the plan view of semiconductor layer 40, the first gate pad 119A and the second gate pad 129A, as well as the first drain pad 151A and the second drain pad 161A, can be configured in a linearly symmetrical manner about the boundary line 90C. Because the first gate pad 119A, the first drain pad 151A, the second gate pad 129A, and the second drain pad 161A can be configured in this way, even with secondary paths, it is less likely to prevent the first active region 112 and the second active region 122 from having the same area and shape. Therefore, the bias in the bidirectional electrical characteristics and heat dissipation between transistor 10A and transistor 20A will be less pronounced.

[0356] Furthermore, with the above configuration, the first drain pad 151A, the second drain pad 161A, the first gate pad 119A, and the second gate pad 129A can be arranged as close as possible to the outer periphery of the semiconductor layer 40. Compared with the case where they are arranged in the center of the semiconductor layer 40, the possibility of poor bonding with the solder due to warping caused by the semiconductor device 1C can be reduced.

[0357] In addition, such as Figures 19A-19BAs shown, in a plan view of semiconductor layer 40, the first gate pad 119A and the first drain pad 151A are configured not adjacent to each other, and the second gate pad 129A and the second drain pad 161A are configured not adjacent to each other.

[0358] Furthermore, in a plan view of the semiconductor layer 40, no other pads are sandwiched between the plurality of first source pads 111A, no other pads are sandwiched between the plurality of second source pads 121A, and no other pads are sandwiched between the first source pad group and the second source pad group.

[0359] The above configuration expands the effective utilization range of the first and second active regions. Therefore, it minimizes the increase in the on-resistance of the main path caused by the presence of a secondary path.

[0360] In addition, such as Figures 19A-19B As shown, in a plan view of semiconductor layer 40, in the first region A1A, a plurality of first source pads 111A are arranged between the first gate pad 119A and the first drain pad 151A along the arrangement direction of the first gate pad 119A and the first drain pad 151A, and in the second region A2A, a plurality of second source pads 121A are arranged between the second gate pad 129A and the second drain pad 161A along the arrangement direction of the second gate pad 129A and the second drain pad 161A.

[0361] And, as Figure 19B As shown, in a plan view of semiconductor layer 40, a plurality of first source pads 111A are also arranged in the first region A1A in a direction orthogonal to the boundary line 90C, and a plurality of second source pads 121A are also arranged in the second region A2A in a direction orthogonal to the boundary line 90C.

[0362] The above configuration expands the usable area of ​​both the first and second active regions. Therefore, it minimizes the increase in on-resistance of the main path due to the presence of a secondary path and ensures high heat dissipation. Furthermore, by preventing an excessively large pad area, mounting defects during face-down mounting are reduced. In particular, it prevents solder overflow and insufficiency caused by warpage and suppresses the formation of voids.

[0363] In addition to the above configuration, in the plan view of semiconductor layer 40, the first gate pad 119A, the second gate pad 129A, the first drain pad 151A, and the second drain pad 161A can be circles with the same diameter, and can be the pads with the smallest area among the pads provided by semiconductor layer 40.

[0364] With the above configuration, in a plan view of semiconductor layer 40, the area of ​​the region that does not contribute to the conduction of the main path of semiconductor device 1C can be minimized. Therefore, the increase in the on-resistance of the main path due to the presence of a secondary path can be suppressed.

[0365] The embodiments have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. Various modifications conceived by those skilled in the art to these embodiments, and combinations of constituent elements from different embodiments and modifications, are also included within the scope of one or more embodiments of this disclosure, provided they do not depart from the spirit of this disclosure. Furthermore, not only combinations of structures explicitly shown in the descriptions of each embodiment, but also structures from multiple embodiments can be combined with each other even without explicit description, provided that no particular obstacle arises in the combination.

[0366] Industrial availability

[0367] Semiconductor devices incorporating the vertical MOS transistors of this invention can be widely used as devices for controlling the conduction state of current paths.

Claims

1. A semiconductor device, a chip-scale packaged semiconductor device capable of being mounted face-down, said semiconductor device comprising: Semiconductor substrate; A low-concentration impurity layer formed on the semiconductor substrate; When the semiconductor substrate and the low-concentration impurity layer are used together as the semiconductor layer... A first vertical MOS transistor is formed in the first region of the semiconductor layer; A second vertical MOS transistor is formed in a second region, which is the region adjacent to the first region in a plan view of the semiconductor layer; A first source pad group, consisting of multiple first source pads, is formed in the first region in the plan view and is connected to the first source electrode of the first vertical MOS transistor. A first gate pad is formed in the first region in the plan view and is connected to the first gate electrode of the first vertical MOS transistor. A first drain pad is formed in the first region in the plan view and is connected to the first drain electrode of the first vertical MOS transistor; A group of second source pads, consisting of multiple second source pads, is formed in the second region in the plan view and is connected to the second source electrode of the second vertical MOS transistor. A second gate pad is formed in the second region in the plan view and is connected to the second gate electrode of the second vertical MOS transistor; A second drain pad is formed in the second region in the plan view and is connected to the second drain electrode of the second vertical MOS transistor; as well as A metal layer is formed in contact with the back side of the semiconductor substrate. The semiconductor substrate is the common drain region of the first vertical MOS transistor and the second vertical MOS transistor. In the plan view, the semiconductor layer is a rectangle with a long side and a short side. In the plan view, the first region and the second region are one and the other sides that divide the semiconductor layer into two equal parts in area. In the plan view, the first drain pad and the second drain pad are arranged in a direction orthogonal to the boundary lines of the first region and the second region, and the midpoint of the line segment connecting the center of the first drain pad and the center of the second drain pad is located on the boundary line. In the plan view, the first gate pad and the second gate pad are arranged in a direction orthogonal to the boundary line, and the midpoint of the line segment connecting the center of the first gate pad and the center of the second gate pad is located on the boundary line. In the plan view, no other pads are sandwiched between the first drain pad and the second drain pad and one of the short sides of the outer periphery of the rectangular semiconductor layer. In the plan view, no other pads are sandwiched between the first gate pad and the second gate pad and another short side of the outer periphery of the rectangular semiconductor layer.

2. The semiconductor device as claimed in claim 1, In the plan view, the first gate pad and the first drain pad are arranged not adjacent to each other. In the plan view, the second gate pad and the second drain pad are arranged not adjacent to each other.

3. The semiconductor device as claimed in claim 2, In the plan view, no other pads are sandwiched between the plurality of first source pads, and no other pads are sandwiched between the plurality of second source pads. In the plan view, no other pads are sandwiched between the first source pad group and the second source pad group.

4. The semiconductor device as claimed in claim 3, In the plan view, in the first region, a plurality of first source pads are arranged between the first gate pad and the first drain pad along the arrangement direction of the first gate pad and the first drain pad. In the plan view, in the second region, a plurality of second source pads are arranged between the second gate pad and the second drain pad along the arrangement direction of the second gate pad and the second drain pad.

5. The semiconductor device as claimed in claim 4, In the plan view, in the first region, a plurality of first source pads are also arranged in a direction orthogonal to the boundary line. In the plan view, in the second region, a plurality of second source pads are also arranged in a direction orthogonal to the boundary line.

6. The semiconductor device as claimed in any one of claims 1 to 5, In the plan view, the first gate pad, the second gate pad, the first drain pad, and the second drain pad are circles with the same diameter, and are the smallest pads in area among the pads provided in the semiconductor layer.

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