Universal FPGA (Field Programmable Gate Array) data acquisition and processing platform

Abstract

The utility model discloses a universal FPGA data acquisition and processing platform, which is characterized by comprising an FPGA module, an optical fiber transmission module, a gigabit network module, a DDR3 dynamic data storage module, a Flash memory module, an LPC connector interface module, an HPC connector interface module, a universal SMA connector module and a high-precision system programmable clock module, wherein the HPC connector interface module provides a digital signal channel between the FPGA module and external equipment through an HPC connector; the HPC connector is connected with the FPGA module to generate 80 pairs of differential signals based on the LVDS level standard, the HPC connector is connected with the high-precision system programmable clock module to generate 4 pairs of programmable differential clock signals based on the LVDS level standard, and the HPC connector is connected with the two special GTX high-speed data transceivers in the FPGA module to form 16 pairs of GTX high-speed data transceiving links.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the field of nuclear electronics, and relates to a hardware design of FPGA data acquisition and processing, in particular to a universal FPGA data acquisition and processing platform. BACKGROUND

[0002] With the development of nuclear science and technology, whether the research on the internal characteristics and laws of atomic nucleus or the application of nuclear science and technology, the information carried by nuclear radiation and atomic nucleus needs to be measured and analyzed. Generally, various nuclear radiation detectors are used to detect and output nuclear information, and the information is converted into an electric signal, and then the signal is processed and researched by using electronic methods, and the information carried by the output signal of the detector is preserved as much as possible. The corresponding energy, charge, mass, time and position information are measured and analyzed from the amplitude, time and trajectory information of the output signal, and the measurement accuracy is continuously improved and the measurement speed is faster and faster, so that nuclear electronics is gradually developed and formed in the field of nuclear science and technology.

[0003] At present, the method used in nuclear electronics is that the output signal of the detector is first amplified, shaped or triggered, and timed, then the analog signal is converted into a digital quantity by analog-digital conversion, and the useful analog information is converted into a digital quantity, and then the digital trigger and timing signal are sent to the FPGA data acquisition and processing system for further processing, and the data after processing is sent to a computer for further analysis, display and the like. The above four parts constitute the measurement system of nuclear electronics, as shown in the figure. Figure 1

[0004] The analog amplification and shaping module, the trigger and timing module and the analog-digital conversion module in the nuclear electronics measurement system will change greatly with the design and demand of the specific detector, but the FPGA data acquisition and processing module changes little. In view of this, and considering the various functions of the commonly used FPGA data acquisition and processing module in the industry, the utility model provides a hardware design scheme of universal nuclear electronics data acquisition and processing, which can be compatible with the data acquisition and processing modules in various nuclear electronics measurement systems. Utility model content

[0005] In view of the problems in the prior art, the purpose of the utility model is to provide a universal FPGA data acquisition and processing platform, which is a universal FPGA hardware platform. Users only need to design special amplification and shaping, analog-digital conversion and trigger timing required by different detectors according to different project requirements, and then couple them to the universal FPGA hardware platform of the utility model, so that a complete nuclear electronics test system can be conveniently and quickly built, and the research and development progress of the field of scientific research projects can be accelerated.

[0006] ​The platform takes a Kintex7 series FPGA (Field-Programmable Gate Array, FPGA) chip (specific model: XC7K325T-2FFG900) of Xilinx Company as a core module of the hardware design, and through loading a DDR3 module, a high-precision programmable clock module, a gigabit network transmission module, a fiber transmission module, a USB-serial module, a general HPC (High Pin Connector, HPC) and LPC (Low Pin Connector, LPC) connector module and the like, a new hardware design scheme of general nuclear electronics data acquisition and processing is realized.

[0007] The hardware scheme uses one high-performance FPGA chip XC7K325T-2FFG900, two LPC connectors and one HPC connector to enhance the logic processing function and peripheral extensible function of the hardware.

[0008] 1, the LPC connector 1 can provide 68 groups of signals and 4 power supplies (1.5V, 1.8V, 2.5V, 3.3V) based on the LVCMOS-1.8V level standard for peripherals;

[0009] 2, the LPC connector 2 can provide 68 groups of signals and 4 power supplies (1V, 1.2V, 3.6V, 5.4V) based on the LVCMOS-3.3V level standard for peripherals;

[0010] 3, the HPC connector can provide 80 pairs of FPGA data / clock signals based on the LVDS level standard, 4 pairs of programmable differential clock signals based on the LVDS / LVPECL / CML level standard, 16 pairs of GTX high-speed transceiver signals in the FPGA and 1 digital power supply of 12V for peripherals.

[0011] The technical scheme of the utility model discloses:

[0012] A general FPGA data acquisition and processing platform, characterized in that it comprises an FPGA module 17, a fiber transmission module, a gigabit network module 5, a DDR3 dynamic data storage module 7, a Flash memory module 10, an LPC connector interface module, an HPC connector interface module 13, a general SMA connector module 14, a high-precision system programmable clock module 16, wherein,

[0013] The Flash memory module 10 is used for storing the logic code of the FPGA module 17 and loading the logic code into the FPGA module 17 at each power-on;

[0014] The FPGA module 17 is used for executing control instructions sent by the computer through the gigabit network module 5.

[0015] The DDR3 dynamic data storage module 7 is used for dynamically storing data in the FPGA module 17.

[0016] The optical fiber transmission module is used for realizing data communication between the FPGA module 17 and external devices.

[0017] The gigabit network module 5 is used for transmitting data processed by the FPGA module 17 to the computer.

[0018] The LPC connector interface module is used for providing a digital signal channel between the FPGA module 17 and external devices through the LPC connector.

[0019] The HPC connector interface module 13 is used for providing a digital signal channel between the FPGA module 17 and external devices through the HPC connector; wherein the HPC connector is connected with a general IO port of the FPGA module 17, and is used for generating 80 pairs of differential signals based on the LVDS level standard; the HPC connector is connected with the high-precision system programmable clock module 16, and is used for generating 4 pairs of programmable differential clock signals based on the LVDS level standard; the HPC connector is connected with 2 special GTX high-speed data transceivers in the FPGA, and constitutes 16 pairs of GTX high-speed data transceiver links.

[0020] The general SMA connector module 14 includes a plurality of SMA connectors, which are used for inputting external trigger signals into the FPGA module 17.

[0021] The high-precision system programmable clock module 16 is used for generating a plurality of frequency-adjustable FPGA working clocks and external device working clocks according to online programming configuration of the FPGA module 17.

[0022] Further, it also includes a digital switching power module 1, a DDR3 power module 8, a GTX power module 9; the LPC connector interface module includes a second LPC connector interface module 11 and a first LPC connector interface module 15, which respectively provide a digital signal channel between the FPGA module 17 and external devices through the internal LPC connector; the digital switching power module 1 is used to generate 1V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 3.6V and 5.4V digital power according to the external 12V DC power supply and respectively supply power for the gigabit network module 5, the DDR3 power module 8, the GTX power module 9, the Flash memory module 10, the HPC connector interface module 13, the second LPC connector interface module 11, the first LPC connector interface module 15 and the FPGA module 17; the DDR3 power module 8 is used to provide power for the DDR3 dynamic data storage module 7; the GTX power module 9 is used to provide voltage for the special GTX high-speed data transceiver power module inside the FPGA module 17; the second LPC connector interface module 11 is used to provide 1V, 1.2V, 3.6V and 5.4V digital power for the connected external devices, and provide a digital signal channel based on the LVCMOS-3.3V level standard between the FPGA module 17 and external devices; the first LPC connector interface module 15 is used to provide 1.5V, 1.8V, 2.5V and 3.3V digital power for the connected external devices, and provide a digital signal channel based on the LVCMOS-1.8V level standard between the FPGA module 17 and external devices; the HPC connector interface module 13 is used to provide 12V digital power for the connected external devices.

[0023] Further, the optical fiber transmission module includes a first optical fiber data transmission module 4 and a second optical fiber data transmission module 3, which are respectively used as high-speed optical communication interfaces to provide data communication with a data transmission rate of 12.5Gbps between the FPGA module 17 and external devices.

[0024] Further, the LPC connector interface module includes a second LPC connector interface module 11 and a first LPC connector interface module 15, which respectively provide a digital signal channel between the FPGA module 17 and external devices through the internal LPC connector.

[0025] Further, it also includes an LED module 6 for monitoring the power-on working state of the FPGA module 17.

[0026] Further, it also includes an LED panel light module 12 for monitoring the working state of the connected external devices.

[0027] Furthermore, it also includes a USB serial port module 2, which is used to provide USB serial communication between the FPGA module 17 and the computer.

[0028] Furthermore, the high-precision system programmable clock module 16 adopts the high-precision programmable clock chip LMK04832; the FPGA module 17 adopts the XC7K325T-2FFG900 chip.

[0029] Furthermore, the DDR3 dynamic data storage module 7 uses two DDR3 chips with a storage capacity of 4Gb to provide dynamic storage of 8Gb of data for the FPGA module 17.

[0030] The advantages of this utility model are as follows:

[0031] The hardware itself is powerful, including 1Gbps network communication, 12.5Gbps fiber optic communication, USB serial communication, 8GbDDR3 dynamic data storage, and multiple programmable high-precision clocks. In addition, the onboard LPC and HPC connectors provide multiple single-ended / differential data with different level standards, programmable clocks, power output interfaces, etc. The peripherals are highly expandable, thus realizing a wide variety of nuclear electronics data acquisition and processing functions. Attached Figure Description

[0032] Figure 1 This is a diagram of a nuclear electronics measurement system.

[0033] Figure 2 This is a hardware structure diagram of this platform.

[0034] Reference numerals: 01-Detector, 02-Analog amplification and shaping unit, 03-Triggering and timing unit, 04-Analog-to-digital converter, 05-FPGA data acquisition and processing unit, 06-Computer, 07-Nuclear electronics measurement system; 1-Digital switching power supply module, 2-USB serial port module, 3-Second fiber optic data transmission module, 4-First fiber optic data transmission module, 5-Gigabit network module, 6-LED module, 7-DDR3 dynamic data storage module, 8-DDR3 power supply module, 9-GTX power supply module, 10-Flash memory module, 11-Second LPC connector interface module, 12-LED panel light module, 13-HPC connector interface module, 14-Universal SMA connector module, 15-First LPC connector interface module, 16-High-precision system programmable clock module, 17-FPGA module. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0036] The hardware structure block diagram of this utility model is as follows: Figure 2 As shown, where:

[0037] Digital switching power supply module 1: An external 12V DC power supply generates 1V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 3.6V and 5.4V digital power supplies after passing through digital switching power supply module 1, providing digital power supply for the entire hardware system. Specifically, 1V digital power is supplied to FPGA module 17 and second LPC connector interface module 11; 1.2V digital power is supplied to second LPC connector interface module 11; 1.5V digital power is supplied to DDR3 power module 8 and first LPC connector interface module 15; 1.8V digital power is supplied to Gigabit network module 5 and first LPC connector interface module 15; 2.5V digital power is supplied to Flash memory module 10, GTX power supply module 9 and first LPC connector interface module 15; 3.3V digital power is supplied to high-precision system programmable clock module 16, USB serial port module 2, second fiber optic data transmission module 3, first fiber optic data transmission module 4, LED module 6, first LPC connector interface module 15 and LED panel light module 12; 3.6V digital power is supplied to second LPC connector interface module 11; and 5.4V digital power is supplied to second LPC connector interface module 11.

[0038] USB serial port module 2: Uses the CP2102 chip to achieve USB serial communication with the computer.

[0039] The second fiber optic data transmission module 3 serves as a high-speed optical communication interface, with a data transmission rate of up to 12.5Gbps, enabling high-speed fiber optic data communication between the hardware system and external devices.

[0040] The first fiber optic data transmission module 4 serves as a high-speed optical communication interface, with a data transmission rate of up to 12.5Gbps, used to realize high-speed fiber optic data communication between the hardware system and external devices.

[0041] The gigabit network module 5 serves as a bridge for data communication between the FPGA module 17 and the computer. Its bidirectional transmission rate is 1Gbps, transmitting the data processed by the FPGA module 17 to the computer. At the same time, the computer can also send commands to the FPGA module 17 through the gigabit network module 5 to control its working status.

[0042] LED module 6 contains 8 LEDs used to monitor the power-on status of the entire FPGA hardware system.

[0043] DDR3 dynamic data storage module 7 takes 2 DDR3 chips with storage capacity of 4 Gb as the core to realize dynamic storage of 8 Gb data in FPGA module 17.

[0044] DDR3 power supply module 8 provides power supply for DDR3 chips.

[0045] GTX power supply module 9 is a power supply module for special GTX high-speed data transceiver in FPGA module 17, which provides 3 analog voltages of MGTAVCC_1V0, MGTAVTT_1V2 and MGTVCCAUX_1V8; wherein MGTAVCC_1V0 is 1V analog voltage, MGTAVTT_1V2 is 1.2V analog voltage, and MGTVCCAUX_1V8 is 1.8V analog voltage.

[0046] Flash memory module 10 is used to store the logic code for the operation of FPGA module 17, and automatically loads the logic code into FPGA module 17 each time the hardware system is powered on.

[0047] Second LPC connector interface module 11, the LPC connector in the interior provides the digital signal channel between the hardware and the peripheral and the power supply for the peripheral, wherein the digital signals are based on LVCMOS-3.3V level standard. Specifically, the 68 pins of the LPC are connected to the general IO port of FPGA module 17, and in addition, 8 pins are connected to digital switching power supply module 1 to provide 4 digital power supplies of 1V, 1.2V, 3.6V and 5.4V for the peripheral.

[0048] LED panel light module 12 includes 8 LED panel lights, which are used to monitor the working state of the peripheral connected to the hardware.

[0049] HPC connector interface module 13 also provides digital signal channels between the hardware and the peripheral and power supply for the peripheral. Specifically, the 160 pins of the HPC connector are connected to the general IO port of the FPGA, which are used to generate 80 pairs of differential signals based on LVDS level standard, in addition, 8 pins are connected to high-precision system programmable clock module 16, which are used to generate 4 pairs of programmable differential clock signals based on LVDS level standard, and 32 pins are connected to 2 special GTX high-speed data transceivers in the FPGA, which constitute 16 pairs of GTX high-speed data transceiver links, and finally 2 pins are connected to digital switching power supply module 1 to provide 1 digital power supply of 12V for the peripheral.

[0050] General SMA connector module 14 includes 4 general SMA connectors as the input interface of 4 external trigger signals based on LVCMOS-3.3V level standard.

[0051] The LPC connector in the first LPC connector interface module 15 also provides a digital signal channel between the hardware and the peripherals and power supply for the peripherals, wherein the digital signals are based on the LVCMOS-1.8V level standard. Specifically, 68 pins of the LPC are connected to the general IO ports of the FPGA module 17, and 8 pins are connected to the digital switching power supply module 1 to provide 4 paths of digital power 1.5V, 1.8V, 2.5V and 3.3V for the peripherals.

[0052] The high-precision system programmable clock module 16 takes the high-precision programmable clock chip LMK04832 as the core, which can be programmed and configured online by the FPGA in the FPGA module 17, to generate at most 14 paths of frequency-adjustable FPGA working clock and peripheral working clock.

[0053] The FPGA module 17 is the core of the platform, which adopts the high-performance Kintex7 series XC7K325T-2FFG900 chip of Xilinx Company.

[0054] The platform has simple structure, convenient use and strong expandability, and fully meets the design requirements of the general nuclear electronics hardware platform.

[0055] Although the specific embodiments of the utility model are disclosed for the purpose of illustration, the purpose is to help understand the content of the utility model and to implement it, those skilled in the art can understand that: without departing from the spirit and scope of the utility model and the attached claims, various substitutions, changes and modifications are possible. Therefore, the utility model should not be limited to the disclosed content of the best embodiment, and the scope of the utility model claimed is the scope defined by the claims.

Claims

1. A universal FPGA data acquisition and processing platform, characterized in that, The FPGA module (17), the optical fiber transmission module, the gigabit network module (5), the DDR3 dynamic data storage module (7), the Flash memory module (10), the LPC connector interface module, the HPC connector interface module (13), the general SMA connector module (14), and the high-precision system programmable clock module (16) are included. The Flash memory module (10) is configured to store logic codes for the operation of the FPGA module (17) and load the logic codes into the FPGA module (17) at each power-on. The FPGA module (17) is configured to execute control instructions sent by a computer through the gigabit network module (5). The DDR3 dynamic data storage module (7) is configured to dynamically store data in the FPGA module (17). The optical fiber transmission module is configured to realize data communication between the FPGA module (17) and external devices. The gigabit network module (5) is configured to transmit data processed by the FPGA module (17) to a computer. The LPC connector interface module is configured to provide a digital signal channel between the FPGA module (17) and external devices through an LPC connector. The HPC connector interface module (13) is configured to provide a digital signal channel between the FPGA module (17) and external devices through an HPC connector, wherein the HPC connector is connected to a general IO port of the FPGA module (17) to generate 80 pairs of differential signals based on an LVDS level standard, the HPC connector is connected to the high-precision system programmable clock module (16) to generate 4 pairs of programmable differential clock signals based on an LVDS level standard, and the HPC connector is connected to 2 special GTX high-speed data transceivers inside the FPGA to form 16 pairs of GTX high-speed data transceiver links. The general SMA connector module (14) includes a plurality of SMA connectors, which are used to input external trigger signals into the FPGA module (17). The high-precision system programmable clock module (16) is configured to generate multiple frequency-adjustable FPGA working clocks and external device working clocks according to online programming configuration of the FPGA module (17).

2. The universal FPGA data acquisition and processing platform of claim 1, wherein, The system further includes a digital switching power supply module (1), a DDR3 power supply module (8), and a GTX power supply module (9). The LPC connector interface module includes a second LPC connector interface module (11) and a first LPC connector interface module (15), which respectively provide digital signal channels between the FPGA module (17) and external devices through internal LPC connectors. The digital switching power supply module (1) is configured to generate 1V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 3.6V and 5.4V digital power supply for the Gigabit network module (5), the DDR3 power module (8), the GTX power module (9), the Flash memory module (10), the HPC connector interface module (13), the second LPC connector interface module (11), the first LPC connector interface module (15), and the FPGA module (17).

3. The universal FPGA data acquisition and processing platform of claim 1, wherein, The optical fiber transmission module includes a first optical fiber data transmission module (4) and a second optical fiber data transmission module (3) as high-speed optical communication interfaces for providing data communication with a data transmission rate of 12.5 Gbps between the FPGA module (17) and external devices.

4. The universal FPGA data acquisition and processing platform of claim 1, wherein, The LPC connector interface module includes a second LPC connector interface module (11) and a first LPC connector interface module (15) for providing digital signal channels between the FPGA module (17) and external devices through the internal LPC connectors.

5. The universal FPGA data acquisition and processing platform according to claim 1 or 2 or 3, characterized in that, An LED module (6) is further included for monitoring the power-on working state of the FPGA module (17).

6. The universal FPGA data acquisition and processing platform according to claim 1 or 2 or 3, characterized in that, An LED panel light module (12) is further included for monitoring the working state of each external device connected thereto.

7. The universal FPGA data acquisition and processing platform of claim 1, wherein, A USB serial port module (2) is further included for providing USB serial communication between the FPGA module (17) and a computer.

8. The universal FPGA data acquisition and processing platform of claim 1, wherein, The high-precision system programmable clock module (16) uses a high-precision programmable clock chip LMK04832, and the FPGA module (17) uses an XC7K325T-2FFG900 chip.

9. The universal FPGA data acquisition and processing platform of claim 1, wherein, The DDR3 dynamic data storage module (7) uses two DDR3 chips with a storage capacity of 4 Gb to provide 8 Gb of dynamic storage for the FPGA module (17).

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