Voltage generator and semiconductor device

Abstract

The utility model provides a voltage generator and a semiconductor device. The voltage generator includes a temperature dependent voltage generator and a reference voltage node. The temperature dependent voltage generator generates a voltage that increases as the temperature increases, and includes a first transistor stack and a second transistor stack. The first transistor stack and the second transistor stack each have a predetermined number of transistors. The number of transistors of the second transistor stack is greater than the number of transistors of the first transistor stack. The reference voltage node is connected to the temperature-dependent voltage generator and provides a reference voltage that is substantially temperature-independent. A method for generating a temperature-independent reference voltage is also disclosed.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of voltage generator and a kind of semiconductor device. BACKGROUND

[0002] In many devices, it is desirable to maintain a constant reference voltage regardless of temperature variations, where a stable voltage enables the most accurate operation. If the reference voltage varies with temperature, errors or instabilities can be introduced in the performance of the device. Having a reference voltage that is temperature-independent can enable more consistent and reliable operation of the device under different environmental conditions. Such a reference voltage helps to maintain accuracy and stability in various applications, such as analog-to-digital converters, voltage regulators, sensor interfaces, and other circuits where an accurate voltage reference is beneficial. SUMMARY

[0003] The utility model provides a kind of voltage generator and a kind of semiconductor device.

[0004] A voltage generator of the utility model includes: a temperature-dependent voltage generator configured to generate a voltage that increases with rising temperature, the temperature-dependent voltage generator includes a first transistor stack and a second transistor stack, the first transistor stack and the second transistor stack each have a predetermined number of transistors, wherein the number of transistors of the second transistor stack is greater than the number of transistors of the first transistor stack; and a reference voltage node connected to the temperature-dependent voltage generator and configured to provide a reference voltage that is substantially temperature-independent.

[0005] A semiconductor device of the utility model includes: a first temperature-dependent voltage generator configured to generate a voltage that increases with rising temperature; a second temperature-dependent voltage generator configured to generate a voltage that decreases with rising temperature; and a reference voltage node connected to the first temperature-dependent voltage generator and the second temperature-dependent voltage generator and configured to provide a reference voltage that is substantially temperature-independent, wherein the second temperature-dependent voltage generator includes: a plurality of transistor stacks; and a switch circuit configured to selectively connect one or more of the plurality of transistor stacks to the reference voltage node. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a schematic block diagram showing an exemplary semiconductor device according to various embodiments of the present disclosure.

[0007] Figure 2is a schematic circuit diagram illustrating another exemplary semiconductor device according to various embodiments of the present disclosure.

[0008] Figure 3 is a schematic circuit diagram illustrating an exemplary transistor module of a semiconductor device according to various embodiments of the present disclosure.

[0009] Figure 4 is a schematic circuit diagram illustrating another exemplary transistor module of a semiconductor device according to various embodiments of the present disclosure.

[0010] Figure 5 is a schematic circuit diagram illustrating another exemplary transistor module of a semiconductor device according to various embodiments of the present disclosure.

[0011] Figure 6 is a schematic circuit diagram illustrating another exemplary transistor module of a semiconductor device according to various embodiments of the present disclosure.

[0012] Figure 7 is a schematic circuit diagram illustrating another exemplary transistor module of a semiconductor device according to various embodiments of the present disclosure.

[0013] Figure 8 is a schematic circuit diagram illustrating another exemplary transistor module of a semiconductor device according to various embodiments of the present disclosure.

[0014] Figure 9 is a schematic circuit diagram illustrating another exemplary transistor module of a semiconductor device according to various embodiments of the present disclosure.

[0015] Figure 10 is a schematic circuit diagram illustrating another semiconductor device according to various embodiments of the present disclosure.

[0016] Figure 11 is a schematic circuit diagram illustrating another semiconductor device according to various embodiments of the present disclosure.

[0017] Figure 12 is a flow diagram illustrating an exemplary method of generating a temperature-independent reference voltage according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] The following detailed description provides many different embodiments, or examples, for implementing different features of the provided subject matter. For purposes of explanation and as provided in the description of the embodiments of the present disclosure, various examples or aspects of the subject matter are described in connection with the detailed description. Of course, it is understood that the subject matter is not limited to the embodiments described, and is intended to include any changes to processes, machines, articles of manufacture, etc. that fall within the scope of the claimed subject matter. Furthermore, it is understood that the following description is intended to provide examples of the subject matter and is not intended to limit the scope of the subject matter.

[0019] A reference voltage with zero (or near zero) temperature coefficient or temperature independence is advantageous for devices that benefit from a stable voltage, as the reference voltage remains constant despite temperature variations. This helps provide accuracy and stability in various devices, such as analog-to-digital converters, voltage regulators, and sensor interfaces. A temperature-independent reference voltage can be generated using a temperature-dependent voltage generator that generates a temperature-dependent voltage, i.e., a voltage that can vary with temperature. In some cases, the temperature-dependent voltage can be a voltage proportional to absolute temperature (PTAT) that has a positive temperature coefficient and increases with temperature, or a voltage complementary to absolute temperature (CTAT) that has a negative temperature coefficient and decreases with temperature. In some cases, the temperature-dependent voltage generator is implemented with a combination of bipolar junction transistors (BJTs) and / or transistors with different voltage thresholds, such as standard voltage threshold (SVT), low voltage threshold (LVT), high voltage threshold (HVT), ultra-low voltage threshold (ULVT), and ultra-high voltage threshold (UHVT). Implementations using different transistor combinations can result in inconsistent performance, i.e., 10-15% 3-sigma accuracy.

[0020] Systems and methods of embodiments described herein include temperature-dependent voltage generators, such as, Figure 1A temperature-dependent voltage generator 110, implemented with transistors such as field-effect transistors (FETs), has substantially the same threshold voltage and does not use BJTs, as well as a temperature-independent voltage generator based thereon, which can achieve 3-sigma accuracy of less than 5%. For example, the temperature-dependent voltage generator 110 includes one or more transistor stacks, such as those according to embodiments. Figure 3 The transistor stacks (M1') in the structure have a predetermined number of transistors connected in series. More specifically, Figure 1 This is a schematic block diagram illustrating an exemplary semiconductor device 100 according to various embodiments of the present disclosure.

[0021] like Figure 1 As shown, semiconductor device 100, such as a voltage generator, is in the form of a bandgap circuit and includes a first temperature-dependent voltage generator 110 and a second temperature-dependent voltage generator 120. Semiconductor device 100 is connected to a first supply voltage node 130, which receives a first supply voltage (Vdd), and a second supply voltage node 140 (e.g., an electrical ground point) receives a second supply voltage (Vss) lower than the first supply voltage (Vdd) (e.g., 0 volts).

[0022] The first temperature-dependent voltage generator 110 includes a PTAT circuit and generates a PTAT voltage (VPTAT) with a positive temperature coefficient that increases with increasing temperature. The second temperature-dependent voltage generator 120 includes a complementary CTAT circuit and generates a CTAT voltage (VCTAT) that is inversely proportional to temperature and decreases with increasing temperature. The semiconductor device 100 generates a temperature-independent reference voltage (Vref) at the reference voltage node 150 based on the PTAT voltage (VPTAT) and the CTAT voltage (VCTAT) (e.g., by combining these values). In some examples, this generates a reference voltage (e.g., about 0.1V to about 0.5V) with a substantially zero temperature coefficient (e.g., less than 100 ppm / °C).

[0023] Exemplary support circuitry of semiconductor device 100, such as Figure 2 As shown. It should be understood that this circuit is merely an example and not a limitation, and other suitable semiconductor device 100 circuits are included within the scope of this disclosure. Figure 2 This is a schematic circuit diagram of another exemplary semiconductor device 200 according to various embodiments of the present disclosure. Figure 2As shown, the semiconductor device 200 is connected between the first and second supply voltage (Vdd, Vss) nodes 130, 140 and includes a first current mirror circuit 210, a current source circuit 220, a second current mirror circuit 230, a first temperature dependent voltage generator 110, a resistor (R), and a second temperature dependent voltage generator 120. The first current mirror circuit 210 includes first, second, and third transistors (Tl, T2, T3), e.g., field effect transistors (FETs), each having a source terminal, a drain terminal, and a gate terminal. The source terminals of the first, second, and third transistors (Tl, T2, T3) are connected to each other and to the first supply voltage (Vdd) node 130. The gate terminals of the first, second, and third transistors (Tl, T2, T3) are connected to each other and to the drain terminal of the first transistor (Tl).

[0024] The current source circuit 220 has a first current source terminal connected to the first supply voltage (Vdd) node 130 and generates a substantially constant current (Ics) regardless of changes in the resistance of the load or changes in the first supply voltage (Vdd).

[0025] The second current mirror circuit 230 includes fourth and fifth transistors (T4, T5), e.g., field effect transistors, each having a source terminal, a drain terminal, and a gate terminal. The gate and drain terminals of the fourth transistor (T4) are connected to each other and to a second current source terminal of the current source circuit 220. The source terminal of the fourth transistor (T4) and the source terminal of the fifth transistor (T5) are connected to each other and to the second supply voltage (Vss) node 140.

[0026] The first temperature dependent voltage generator 110 is in the form of a PTAT circuit, generates a PTAT voltage, and includes first and second transistor modules (Ml, M2), e.g., FET modules, each having a source terminal, a drain terminal, and a gate terminal. The drain terminal of the first transistor module (Ml) is connected to the drain terminal of the first transistor (Tl). The gate terminal of the first transistor module (Ml) is connected to a reference voltage (Vref) node 150. The drain terminal of the second transistor module (M2) is connected to the drain terminal of the second transistor (T2). The gate terminal of the second transistor module (M2) is connected to the drain terminal of the third transistor (T3). The source terminal of the first transistor module (Ml) and the source terminal of the second transistor module (M2) are connected to each other and to the drain terminal of the fifth transistor (T5).

[0027] The resistor (R) is connected between the gate terminal of the first transistor module (Ml) and the gate terminal of the second transistor module (M2).

[0028] The second temperature dependent voltage generator 120 is in the form of a CTAT circuit, generates a CTAT voltage, and includes a third transistor module (M3), such as a FET module, having a source terminal, a drain terminal, and a gate terminal. The drain and gate terminals of the third transistor module (M3) are connected to each other and to a reference voltage (Vref) node 150. The source terminal of the third transistor module (M3) is connected to a second supply voltage (Vss) node 140.

[0029] In operation, the semiconductor device 200 receives a first supply voltage (Vdd) and a second supply voltage (Vss). As a result, the first, second, and third transistors (Tl, T2, T3) generate first, second, and third mirror currents (Il, I2, I3), respectively. These currents (Il, I2, I3) flow through the first and second transistor modules (Ml, M2) and the node between the gate of the second transistor module (M2) and the resistor (R). The first and third mirror currents (Il, I3) are proportional to the second mirror current (I2). In the exemplary embodiment, the first, second, and third transistors (Tl, T2, T3) have substantially the same characteristics, such as a W / L ratio, and thus the first, second, and third mirror currents (Il, I2, I3) are substantially equal to each other.

[0030] Next, the current source circuit 220 generates a substantially constant current (Ics) that flows through the fourth transistor (T4) and mirrors to the fifth transistor (T5), thereby biasing the first and second transistor modules (Ml, M2). As a result, the first temperature dependent voltage generator 110 generates a PTAT voltage. At this time, a PTAT current that is substantially equal to the voltage drop (Va-Vb) across the resistor (R) divided by the resistance value of the resistor (R) flows through the third transistor module (M3). As a result, the second temperature dependent voltage generator 120 generates a CTAT voltage, thereby establishing a temperature independent reference voltage (Vref) at the reference voltage (Vref) node 150.

[0031] Figure 3 is a schematic circuit diagram of exemplary transistor modules (Ml, M2, M3) of the semiconductor device 200 in accordance with various embodiments of the present disclosure. As Figure 3As shown, the exemplary transistor module (Ml, M2, M3) includes a transistor stack (Ml', M2', M3'). The transistor stack (Ml') includes a predetermined number of transistors (e.g., FETs) connected in series, each having a source terminal, a drain terminal, and a gate terminal connected in series. That is, the drain of the first transistor in the transistor stack (Ml') serves as the drain terminal of the transistor module (Ml). Further, the source terminal of the last transistor in the transistor stack (Ml') serves as the source terminal of the transistor module (Ml). In addition, the source terminal of each transistor in the transistor stack (Ml) is connected to the drain terminal of the next transistor in the transistor stack (Ml). The gate terminals of the transistors of the transistor stack (Ml') are connected to each other.

[0032] Similarly, the transistor stack (M2') includes a predetermined number of transistors, e.g., field effect transistors, connected in series and each having a source terminal, a drain terminal, and a gate terminal. That is, the drain of the first transistor in the transistor stack (M2') serves as the drain terminal of the transistor module (M2). Similarly, the source terminal of the last transistor in the transistor stack (M2') serves as the source terminal of the transistor module (M2). In addition, the source terminal of each transistor in the transistor stack (M2') is connected to the drain terminal of the next transistor in the transistor stack (M2'). The gate terminals of the transistors of the transistor stack (M2') are connected to each other.

[0033] In the present exemplary embodiment, the number of transistors of the transistor stack (M2') is greater than the number of transistors of the transistor stack (Ml'). In other words, the transistor module (M2) has a longer channel length than the transistor module (Ml).

[0034] Similarly, the transistor stack (M3') includes a plurality of transistors, e.g., field effect transistors, connected in series and each having a source terminal, a drain terminal, and a gate terminal. That is, the drain of the first transistor in the transistor stack (M3') serves as the drain terminal of the transistor module (M3). Similarly, the source of the last transistor in the transistor stack (M3') serves as the source terminal of the transistor module (M3). In addition, the source of each transistor in the transistor stack (M3) is connected to the drain of the next transistor in the transistor stack (M3). The gates of the transistors of the transistor stack (M3') are connected to each other and to the drain of the first transistor in the transistor stack (M3').

[0035] While the transistor modules (Ml, M2, M3) are merely exemplary of a single transistor stack, it should be apparent after reading this disclosure that the transistor modules (Ml, M2, M3) can include one or more transistor stacks. For example, Figure 4is a schematic circuit diagram showing another exemplary transistor module (M1, M2, M3) of the semiconductor device 200 according to various embodiments of the present disclosure. As Figure 4 shown, the exemplary transistor module (M1, M2, M3) includes a plurality of transistor stacks (M1', M2', M3'). The transistor stacks (M1') are connected in parallel. For example, the drain terminals of the first transistors in the transistor stacks (M1') are connected to each other. The source terminals of the last transistors in the transistor stacks (M1') are connected to each other. The gate terminals of the transistors of the transistor stacks (M1') are connected to each other.

[0036] Similarly, the transistor stacks (M2') are connected in parallel. For example, the drain terminals of the first transistors in the transistor stacks (M2') are connected to each other. The source terminals of the last transistors in the transistor stacks (M2') are connected to each other. The gate terminals of the transistors of the transistor stacks (M2') are connected to each other.

[0037] In the present exemplary embodiment, the number of the transistor stacks (M2') is the same as the number of the transistor stacks (M1').

[0038] Similarly, the transistor stacks (M3') are connected in parallel. For example, the drain terminals of the first transistors in the transistor stacks (M3') are connected to each other. The source terminals of the last transistors in the transistor stacks (M3') are connected to each other. The gate terminals of the transistors of the transistor stacks (M3') are connected to each other and to the drain terminals of the first transistors in the transistor stacks (M3').

[0039] Although the transistor module (M1, M2, M3) is exemplified with a predetermined number of transistor stacks (M1', M2', M3'), it should be apparent that the number of the transistor stacks (M1', M2', M3') can be changed after reading the present disclosure to better align the PTAT voltage / current generated by the first temperature dependent voltage generator 110 and the CTAT voltage / current generated by the second temperature dependent voltage generator 120 with each other. Adjusting the number of the transistor stacks (M1', M2', M3') helps to provide a more stable temperature independent reference voltage (Vref) for the semiconductor device 200 of the present disclosure. For example, Figure 5 is a schematic circuit diagram showing another exemplary transistor module (M3) of the semiconductor device 200 according to various embodiments of the present disclosure.

[0040] As Figure 5As shown, the exemplary transistor module (M3) includes a plurality of transistor stacks (M3') and a plurality of switching circuits 510. The transistor stacks (M3') are connected in parallel. For example, the transistor stacks (M3') have a drain terminal connected to a reference voltage (Vref) node 150 and a source terminal connected to a second supply voltage (Vss) node 140.

[0041] The semiconductor device 200 receives a control signal (CS <x:0>) The generator receives a plurality of control signals (CS <x:0>). Each of the switching circuits 510 receives a control signal (CS <x:0>) to a corresponding one of logical "1", e.g. Vdd, or logical "0", e.g. Vss, and according to its received control signal (CS <x:0>), the gate terminal of a corresponding one of the transistor stack (M3') is connected to either the reference voltage (Vref) node 150 or the second supply voltage (Vss) node 140. For example, Figure 6 and Figure 7 is a schematic circuit diagram showing another exemplary transistor module (M3) of the semiconductor device 200 according to various embodiments of the present disclosure.

[0042] As shown in Figure 6 , the switching circuit 510 is in the form of a buffer. The buffer 510 is connected between the reference voltage (Vref) node 150 and the second supply voltage (Vss) node 140 and includes a control signal (CS <x:0>an input terminal connected to the gate terminal of the transistor stack (M3') and an output terminal connected to the gate terminal of the transistor stack (M3').

[0043] In the present exemplary embodiment, as shown in Figure 7 The buffer 510 includes a pair of inverters 710, 720, each connected between a reference voltage (Vref) node 150 and a second supply voltage (Vss) node 140. The inverter 710 has a control signal (CS <x:0>The inverter 720 has an input terminal connected to the output terminal of the inverter 710 and an output terminal connected to the gate terminal of the transistor stack (M3'). In an exemplary embodiment, each inverter 710, 720 includes a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor.

[0044] During operation, when the control signal (CS) <x:0>) is logic "1", e.g. Vdd, the PMOS transistor and the NMOS transistor of the inverter 710 are deactivated and activated, respectively, connecting the input terminal of the inverter 720 to the second supply voltage (Vss) node 140. This activates the PMOS transistor of the inverter 720 and substantially simultaneously deactivates the NMOS transistor of the inverter 720, connecting the gate terminal of the transistor stack (M3') to the reference voltage (Vref) node 150. This in turn activates the transistor stack (M3').

[0045] Conversely, when the control signal (CS <x:0>) is a logic "0", e.g. Vss, the PMOS transistor and the NMOS transistor of the inverter 710 are enabled and disabled, respectively, connecting the input terminal of the inverter 720 to the first supply voltage (Vdd) node 150. This disables the PMOS transistor of the inverter 720 and substantially simultaneously enables the NMOS transistor of the inverter 720, connecting the gate terminal of the transistor stack (M3') to the second supply voltage (Vss) node 140. This in turn disables the transistor stack (M3').

[0046] According to the foregoing, by virtue of the control signal (CS <x:0>Enabling and disabling transistor stacks (M3') allows adjustment or fine-tuning of the number of transistor stacks (M3') of the transistor module (M3) connected between the reference voltage (Vref) node 150 and the second supply voltage (Vss) node 140.

[0047] Figure 8 This is a schematic circuit diagram illustrating another exemplary transistor module (M3) of a semiconductor device 200 according to various embodiments of the present disclosure. Figure 8 As shown, the switching circuit 510 includes a transmission gate 810 connected between the reference voltage (Vref) node 150 and the gate terminal of the transistor stack (M3'), and a sixth transistor (T6) connected between the gate terminal of the transistor stack (M3') and the second supply voltage (Vss) node 140. The transmission gate 810 has a receiving control signal (CS) <x:0>The first input terminal of the signal and the receiver of the complementary control signal (CS') <x:0>The second input terminal of ).

[0048] In this exemplary embodiment, the transistor (T6) is an NMOS transistor, its drain terminal is connected to the gate terminal of the transistor stack (M3'), its source terminal is connected to the second supply voltage (Vss) node 140, and its gate terminal receives a complementary control signal (CS'). <x:0>). In another embodiment, the transistor (T6) is a PMOS transistor.

[0049] In operation, when the control signal (CS <x:0>) is a logic "1", e.g. Vdd, and the complementary control signal (CS <x:0>) is logic "0", e.g., Vss, the pass gate 810 connects the gate terminal of the transistor stack (M3') to the reference voltage (Vref) node 150. This turns on the transistor stack (M3'). At this time, the transistor (T6) turns off.

[0050] Conversely, when the control signal (CS <x:0>) is a logic "0", e.g. Vss, i.e. the complementary control signal (CS <x:0>) is logic "1", e.g. Vdd, the transmission gate 810 disconnects the gate terminal of the transistor stack (M3') from the reference voltage (Vref) node 150. At this time, the transistor (T6) is on, connecting the gate terminal of the transistor stack (M3') to the second supply voltage (Vss) node 140. This turns off the transistor stack (M3').

[0051] According to the foregoing, by virtue of the fact that the control signal (CS <x:0>) and turning on and off the transistor stack (M3'), the number of transistor stacks (M3') in the transistor module (M3) connected between the reference voltage (Vref) node 150 and the second supply voltage (Vss) node 140 can be adjusted or fine-tuned.

[0052] Figure 9 is a schematic circuit diagram showing another exemplary transistor module (M3) of the semiconductor device 200 according to various embodiments of the present disclosure. As shown, the switch circuit 510 includes seventh and eighth transistors (T7, T8) connected in series between the reference voltage (Vref) node 150 and the second supply voltage (Vss) node 140. In the present exemplary embodiment, the seventh transistor (T7) is an NMOS transistor having its drain terminal connected to the reference voltage (Vref) node 150, its source terminal connected to the gate terminal of the transistor stack (M3'), and its gate terminal receiving a control signal (CS Figure 9 <x:0>). The eighth transistor (T8) is an NMOS transistor whose drain terminal is connected to the gate terminal of the transistor stack (M3'), whose source terminal is connected to the second supply voltage (Vss), and whose gate terminal receives a complementary control signal (CS <x:0>). In another embodiment, at least one of the first and second transistors (T7, T8) is a PMOS transistor.

[0053] In operation, when the control signal (CS <x:0>) is a logic "1" (e.g., Vdd), i.e., the complementary control signal (CS <x:0>) is a logic "0" (e.g., Vss), the seventh transistor (T7) turns on, while the eighth transistor (T8) turns off. This connects the gate terminal of the transistor stack (M3') to the reference voltage (Vref) node 150, and substantially simultaneously disconnects the gate terminal of the transistor stack (M3') from the second supply voltage (Vss) node 140, thereby turning on the transistor stack (M3').

[0054] Conversely, when the control signal (CS <x:0>) is a logic "0" (e.g., Vss), i.e., the complementary control signal (CS <x:0>) is logic "1" (e.g., Vdd), the seventh transistor (T7) is turned off, and the eighth transistor (T8) is turned on. This disconnects the gate terminal of the transistor stack (M3') from the reference voltage (Vref) node 150 and substantially simultaneously connects the gate terminal of the transistor stack (M3') to the second supply voltage (Vss) node 140, thereby turning off the transistor stack (M3').

[0055] According to the foregoing, by virtue of the control signal (CS' <x:0>Turning the transistor stack (M3') on and off can adjust or fine-tune the number of transistor stacks (M3') in the transistor module (M3) connected between the reference voltage (Vref) node 150 and the second supply voltage (Vss) node 140.

[0056] Figure 10 This is a schematic circuit diagram illustrating another exemplary semiconductor device 1000 according to various embodiments of the present disclosure. Figure 10 As shown, a semiconductor device 1000 is connected between first and second supply voltage nodes 130 and 140, and includes a first current mirror circuit 1010, a second current mirror circuit 1020, a resistor (R), a first temperature-dependent voltage generator 110, and a second temperature-dependent voltage generator 120. The first current mirror circuit 1010 includes transistors (T9-T12), such as FETs, each having a source, a drain, and a gate terminal. The source terminals of transistors (T9-T12) are connected to each other and to the first supply voltage (Vdd) node 130. The gate terminals of transistors (T9-T12) are connected to each other and to the drain terminal of transistor (T9).

[0057] The second current mirror circuit 1020 includes transistors (T13, T15), such as FETs, each transistor having a source terminal, a drain terminal, and a gate terminal. The drain terminal of transistor (T13) is connected to the drain terminal of transistor (T9). The gate and drain terminals of transistor (T14) and the gate terminal of transistor (T13) are connected to each other and to the drain terminal of transistor (T10). The source terminal of transistor (T14) is connected to the second supply voltage (Vss) node 140.

[0058] The resistor (R) has a first resistor terminal connected to the source terminal of the transistor (T13) and a second resistor terminal connected to the second supply voltage (Vss) node 140.

[0059] The first temperature-dependent voltage generator 110 includes transistor modules (M1, M2), such as FET modules, each having a source terminal, a drain terminal, and a gate terminal. The drain and gate terminals of transistor module (M1) and the gate terminal of transistor module (M2) are connected to each other and to the drain terminal of transistor (T11). The source terminal of transistor module (M2) is connected to the second supply voltage (Vss) node 140.

[0060] The second temperature-dependent voltage generator 120 includes a transistor module (M3), e.g., a FET module, having a source terminal, a drain terminal, and a gate terminal. The drain and gate terminals of the transistor module (M3) and the drain terminal of the transistor (T12) are connected to each other and to the reference voltage (Vref) node 150. The source terminal of the transistor module (M3) is connected to the source terminal of the transistor module (Ml) and to the drain terminal of the transistor module (M2).

[0061] Because the configuration and operation of the transistor modules (Ml, M2, M3) of the semiconductor 1000 are similar to those described above with respect to the semiconductor device 200, a detailed description thereof will be omitted herein for the sake of brevity.

[0062] Figure 11 is a schematic circuit diagram illustrating another exemplary semiconductor device 1100 according to various embodiments of the present disclosure. As shown, the semiconductor device 1100 is connected between first and second supply voltage nodes 130, 140 and includes a current mirror circuit 1110, a transistor (T18), a first temperature-dependent voltage generator 110, and a second temperature-dependent voltage generator 120. The current mirror circuit 1110 includes transistors (T15-T17), e.g., FETs, each having a source, a drain, and a gate terminal. The source terminals of the transistors (T15-T17) are connected to each other and to the first supply voltage (Vdd) node 130. The gate terminals of the transistors (T15-T17) are connected to each other and to the drain terminal of the transistor (T15). Figure 11

[0063] The transistor (T18), e.g., a field effect transistor, has a source terminal, a drain terminal, and a gate terminal. The drain terminal of the transistor (T18) is connected to the drain terminal of the transistor (T15). The source terminal of the transistor (T18) is connected to the second supply voltage (Vss) node 140.

[0064] The first temperature-dependent voltage generator 110 includes transistor modules (Ml, M2), e.g., FET modules, each module having a source terminal, a drain terminal, and a gate terminal. The drain and gate terminals of the transistor module (Ml) and the gate terminal of the transistor module (M2) are connected to each other and to the drain terminal of the transistor (T16). The source terminal of the transistor module (M2) is connected to the second supply voltage (Vss) node 140.

[0065] ​The second temperature-dependent voltage generator 120 includes a transistor module (M3), such as a FET module, having a source terminal, a drain terminal, and a gate terminal. The drain terminal of the transistor module (M3), the gate terminal of the transistor module (M3), and the drain terminal of the transistor (T17) are connected to each other and to the reference voltage (Vref) node 150. The source terminal of the transistor module (M3) is connected to the gate terminal of the transistor (T18), the source terminal of the transistor module (Ml), and the drain terminal of the transistor module (M2).

[0066] Since the configuration and operation of the transistor modules (Ml, M2, M3) of the semiconductor 1100 are similar to those described above with respect to the semiconductor device 200, a detailed description thereof will be omitted herein for the sake of brevity.

[0067] Figure 12 is a flowchart of an exemplary embodiment of a method 1200 of generating a temperature-independent reference voltage (Vref) in accordance with various embodiments of the present disclosure. For ease of understanding, reference will now be made to the semiconductor device 200 of FIG. 2. Figure 2-5 The exemplary method 1200 will be further described. It should be understood that the method 1200 is applicable to the semiconductor device 1100 of FIG. 11, the semiconductor device 1200 of FIG. 12, and other structures besides. Figure 2-5 In addition, it should be understood that in alternative embodiments of the method 1200, additional operations can be provided before, during, and after the method 1200, and that some operations described below can be replaced or eliminated.

[0068] In operation 1210, the current mirror circuit 210 generates a first mirror current and a second mirror current substantially equal to the first mirror current.

[0069] In operation 1220, the first temperature-dependent voltage generator 110 generates a PTAT voltage from the first and second mirror currents.

[0070] In operation 1230, a resistance generates a current proportional to absolute temperature (PTAT) current.

[0071] In operation 1240, the second temperature-dependent voltage generator 120 generates a CTAT voltage from the PTAT current. In particular embodiments, the second temperature-dependent voltage generator 120 includes a plurality of transistor stacks (M3') and a plurality of switch circuits 510. In these particular embodiments, the transistor stacks (M3') are connected in parallel. For example, the transistor stacks (M3') have drain terminals connected to the reference voltage (Vref) node 150 and source terminals connected to the second supply voltage (Vss) node 140. Each switch circuit 510 receives a respective control signal (CS <x:0>), and in accordance with its received control signal (CS <x:0>), the gate terminals of the respective transistor stacks (M3') are connected to a reference voltage (Vref) node 150 or a second supply voltage (Vss) node 140.

[0072] In operation 1250, a reference voltage (Vref) node provides a temperature independent reference voltage (Vref) from PTAT and CTAT voltages.

[0073] In one embodiment, a voltage generator includes a temperature dependent voltage generator and a reference voltage node. The temperature dependent voltage generator generates a voltage that increases with temperature and includes a first transistor stack and a second transistor stack. The first transistor stack and the second transistor stack each have a predetermined number of transistors. The number of transistors of the second transistor stack is greater than the number of transistors of the first transistor stack. The reference voltage node is connected to the temperature dependent voltage generator and provides a reference voltage that is substantially temperature independent.

[0074] In a related embodiment, the voltage generator further includes a first current mirror circuit configured to generate a first current and a second current proportional to the first current, and a second current mirror circuit configured to generate a third current and a fourth current proportional to the third current, wherein the first transistor stack has a first source / drain terminal connected to the first current mirror circuit, a second source / drain terminal connected to the second current mirror circuit, and a gate terminal connected to the reference voltage node, and the second transistor stack has a first source / drain terminal connected to the first current mirror circuit, a second source / drain terminal connected to the second current mirror circuit, and a gate terminal connected to the first current mirror circuit.

[0075] In a related embodiment, the voltage generator further includes a supply voltage node configured to receive a supply voltage, and a current source circuit configured to generate a substantially constant current and connected between the supply voltage node and the second current mirror circuit.

[0076] In a related embodiment, the voltage generator further includes a resistor connected between the gate terminal of the first transistor stack and the gate terminal of the second transistor stack.

[0077] In a related embodiment, wherein the temperature dependent voltage generator further includes one or more transistor stacks connected in parallel with the first transistor stack.

[0078] In a related embodiment, wherein the temperature dependent voltage generator further includes one or more transistor stacks connected in parallel with the second transistor stack.

[0079] In a related embodiment, the voltage generator has a temperature coefficient less than 100 ppm / °C.

[0080] In another embodiment, a semiconductor device includes a first temperature dependent voltage generator, a second temperature dependent voltage generator, and a reference voltage node. The first temperature dependent voltage generator generates a voltage that increases with increasing temperature. The second temperature dependent voltage generator generates a voltage that decreases with increasing temperature. The reference voltage node is connected to the first and second temperature dependent voltage generators and provides a reference voltage that is substantially independent of temperature. The second temperature dependent voltage generator includes a plurality of transistor stacks and a switching circuit configured to selectively connect one or more of the plurality of transistor stacks to the reference voltage node.

[0081] In a related embodiment, the semiconductor device further includes a first current mirror circuit configured to generate a first current and a second current proportional to the first current, and a second current mirror circuit configured to generate a third current and a fourth current proportional to the third current, wherein a first transistor stack of the plurality of transistor stacks has a first source / drain terminal connected to the first current mirror circuit, a second source / drain terminal connected to the second current mirror circuit, and a gate terminal connected to the reference voltage node, and a second transistor stack of the plurality of transistor stacks has a first source / drain terminal connected to the first current mirror circuit, a second source / drain terminal connected to the second current mirror circuit, and a gate terminal connected to the first current mirror circuit.

[0082] In a related embodiment, the semiconductor device further includes a supply voltage node configured to receive a supply voltage, and a current source circuit configured to generate a substantially constant current and connected between the supply voltage node and the second current mirror circuit.

[0083] In a related embodiment, the semiconductor device further includes a resistor connected between the gate terminal of the first transistor stack and the gate terminal of the second transistor stack.

[0084] In a related embodiment, the second temperature dependent voltage generator further includes a transistor stack connected in parallel with the first transistor stack.

[0085] In a related embodiment, the second temperature dependent voltage generator further includes a transistor stack connected in parallel with the second transistor stack.

[0086] In a related embodiment, the second temperature dependent voltage generator further comprises one or more first transistor stacks connected in parallel with the first transistor stack, and one or more second transistor stacks connected in parallel with the second transistor stack, wherein the number of the second transistor stacks is the same as the number of the first transistor stacks.

[0087] In a related embodiment, the semiconductor device of 8 further comprises a supply voltage node configured to receive a supply voltage, wherein the plurality of transistor stacks have first source / drain terminals and gate terminals connected to each other and to the reference voltage node, and second source / drain terminals connected to the supply voltage node.

[0088] In another embodiment, a method of generating a temperature independent reference voltage comprises: generating a first temperature dependent voltage via a first transistor module and a second transistor module, the first temperature dependent voltage increasing with increasing temperature, wherein the second transistor module has a longer channel length than the first transistor module; generating a second temperature dependent voltage via a third transistor module, the second temperature dependent voltage decreasing with increasing temperature; and providing a temperature independent reference voltage at a reference voltage node based on the first temperature dependent voltage and the second temperature dependent voltage.

[0089] In a related embodiment, the method further comprises: generating a first mirror current flowing through the first transistor module; generating a second mirror current flowing through the second transistor module and proportional to the first mirror current; and generating a temperature dependent current flowing through the third transistor module.

[0090] In a related embodiment, the method further comprises: generating a substantially constant current; generating a third mirror current proportional to the substantially constant current; and biasing the first transistor module and the second transistor module with the third mirror current.

[0091] In a related embodiment, the method further comprises generating a temperature dependent current flowing through the third transistor module, the temperature dependent current based on a voltage drop across a resistor and a resistance value of the resistor.

[0092] In a related embodiment, the method further comprises generating a mirror current flowing through the resistor.

[0093] The foregoing summary has outlined features of the present embodiments in order that the skilled person can better understand aspects of the present disclosure. It will be appreciated by persons skilled in the art that they can readily apply the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages that the embodiments described herein introduce. It will be appreciated that changes can be made to the embodiments described herein without departing from the broad disclosure and description of them as set out in the following claims, the spirit of which can be sought to be maintained only as the scope of the claims. ​

Claims

1. A voltage generator, characterized by comprises: a temperature dependent voltage generator configured to generate a voltage that increases with rising temperature, the temperature dependent voltage generator comprising a first transistor stack and a second transistor stack, the first transistor stack and the second transistor stack each having a predetermined number of transistors, wherein the number of transistors of the second transistor stack is greater than the number of transistors of the first transistor stack; and a reference voltage node connected to the temperature dependent voltage generator and configured to provide a reference voltage that is substantially temperature independent. further comprises:

2. The voltage generator of claim 1, wherein, a first current mirror circuit configured to generate a first current and a second current proportional to the first current; and a second current mirror circuit configured to generate a third current and a fourth current proportional to the third current, wherein the first transistor stack has a first source / drain terminal connected to the first current mirror circuit, a second source / drain terminal connected to the second current mirror circuit, and a gate terminal connected to the reference voltage node, and the second transistor stack has a first source / drain terminal connected to the first current mirror circuit, a second source / drain terminal connected to the second current mirror circuit, and a gate terminal connected to the first current mirror circuit. further comprises:

3. The voltage generator of claim 2, wherein, a supply voltage node configured to receive a supply voltage; and a current source circuit configured to generate a substantially constant current and connected between the supply voltage node and the second current mirror circuit. a resistance connected between the gate terminal of the first transistor stack and the gate terminal of the second transistor stack. wherein the temperature dependent voltage generator further comprises one or more transistor stacks connected in parallel with the first transistor stack.

4. The voltage generator of claim 2, wherein, wherein the temperature dependent voltage generator further comprises one or more transistor stacks connected in parallel with the second transistor stack.

5. The voltage generator of claim 1, wherein, wherein the voltage generator has a temperature coefficient less than 100 ppm / °C.

6. The voltage generator of claim 1, wherein, comprises:

7. The voltage generator of claim 1, wherein, a first temperature dependent voltage generator configured to generate a voltage that increases with rising temperature; 8. A semiconductor device, characterized by comprising: a second temperature dependent voltage generator configured to generate a voltage that decreases with rising temperature; and a reference voltage node connected to the first temperature dependent voltage generator and the second temperature dependent voltage generator and configured to provide a reference voltage that is substantially temperature independent, wherein the second temperature dependent voltage generator comprises: a plurality of transistor stacks; and a switch circuit configured to selectively connect one or more of the plurality of transistor stacks to the reference voltage node. further comprises: a first current mirror circuit configured to generate a first current and a second current proportional to the first current; and a second current mirror circuit configured to generate a third current and a fourth current proportional to the third current, wherein a first transistor stack of the plurality of transistor stacks has a first source / drain terminal connected to the first current mirror circuit, a second source / drain terminal connected to the second current mirror circuit, and a gate terminal connected to the reference voltage node, and 9. The semiconductor device according to claim 8, wherein a second transistor stack of the plurality of transistor stacks has a first source / drain terminal connected to the first current mirror circuit, a second source / drain terminal connected to the second current mirror circuit, and a gate terminal connected to the first current mirror circuit. ​ ​ ​ A second one of the plurality of transistor stacks has a first source / drain terminal connected to the first current mirror circuit, a second source / drain terminal connected to the second current mirror circuit, and a gate terminal connected to the first current mirror circuit.

10. The semiconductor device according to claim 9, wherein wherein the second temperature-dependent voltage generator further comprises: one or more first transistor stacks connected in parallel with the first transistor stack; and one or more second transistor stacks connected in parallel with the second transistor stack, wherein the number of the second transistor stacks is the same as the number of the first transistor stacks.

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