Power brick and electronic equipment

Abstract

According to the power brick and the electronic equipment provided by the utility model, the direct current bus capacitor, the power half-bridge unit and the alternating current connecting copper bar in the power brick are integrally packaged by adopting the integrated packaging shell, so that the complexity of a product production process is remarkably reduced. A plurality of components are integrated in one packaging body, and connection points among the components are reduced, so that the assembly process is simplified, and the connection complexity is reduced. According to the integrated design, the space utilization is optimized, the system can realize higher power output in a smaller volume, the power density is improved, and the efficiency of the system is further improved by reducing the use of heat dissipation parts. Meanwhile, the overall packaging serves as a connection and barrier between the internal elements and the external environment, the internal elements can be protected against interference and damage of the external environment, fault points are reduced, and the reliability of the whole power system is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor, concretely relates to a power brick and electronic equipment. BACKGROUND

[0002] Power brick generally refers to an electronic component that integrates power semiconductor modules (such as IGBT or SiC), which has high power density and low thermal resistance, and is suitable for various high-power application scenarios. With the rapid development of electric vehicles and new energy industries, the market demand for power bricks is also increasing. In the future, power bricks will develop towards higher power density, lower thermal resistance, and more extensive application scenarios. At the same time, with the continuous emergence of new materials and new technologies, the performance of power bricks will also be continuously improved.

[0003] The essence of power brick is a power module, Figure 1 It is a front view of a power module disclosed in the prior art, Figure 2 It is Figure 1 The circuit topology diagram of the inverter main power system is shown, which is Figure 1 And Figure 2 It can be seen that the shell in the power module has a cooling cavity and at least one accommodating cavity, and the cooling cavity is arranged around the outer periphery of the at least one accommodating cavity; at least one bus capacitor is arranged in one accommodating cavity; at least one IGBT module is arranged on the outer surface of the cooling cavity. The applicant found that the power module of this design will produce strong vibration and noise during operation. UTILITY MODEL CONTENT

[0004] Therefore, the utility model embodiment provides a power brick and electronic equipment to provide a seismic power brick.

[0005] To achieve the above object, the utility model embodiment provides the following technical scheme:

[0006] A power brick comprises:

[0007] The direct current bus capacitor, the power half-bridge unit and the alternating current connecting copper bar are integrally packaged by using an integral packaging shell, wherein at least part of the alternating current connecting copper bar is exposed on the surface of the integral packaging shell;

[0008] The direct current bus capacitor comprises:

[0009] A bus capacitor core;

[0010] A positive copper bar connected with the positive port of the bus capacitor core, and one end of the positive copper bar not connected with the positive port of the bus capacitor core is exposed outside the integral packaging shell;

[0011] a negative copper bar connected with a negative port of the bus capacitor core;

[0012] the upper D terminal of the power half bridge unit is connected with a positive port of the bus capacitor core, the lower S terminal of the power half bridge unit is connected with a negative port of the bus capacitor core, and the upper D terminal and the lower S terminal are arranged in an upper-lower stacking manner in a three-dimensional space;

[0013] the AC connection copper bar is connected with the D pole of the lower tube chip of the power half bridge unit.

[0014] Optionally, in the power half bridge unit in the power brick, the D poles of the upper tube chips of the single-core power half bridges are connected with equal impedances, the S poles of the upper tube chips of the single-core power half bridges are connected with equal impedances, the D poles of the lower tube chips of the single-core power half bridges are connected with equal impedances, and the S poles of the lower tube chips of the single-core power half bridges are connected with equal impedances.

[0015] Optionally, in the power brick, the power half bridge unit comprises:

[0016] at least one single-core power half bridge;

[0017] the single-core power half bridge comprises:

[0018] a ceramic substrate;

[0019] an upper tube chip arranged on an upper tube ceramic substrate first copper clad layer of the ceramic substrate;

[0020] a lower tube chip arranged on a lower tube ceramic substrate first copper clad layer of the ceramic substrate, and an S pole of the upper tube chip is connected with a D pole of the lower tube chip through an upper tube S pole connection conductor;

[0021] an upper tube D pole terminal, one end of which is connected with the upper tube ceramic substrate first copper clad layer;

[0022] an AC connection copper bar connected with the D pole of the lower tube chip through the lower tube ceramic substrate first copper clad layer of the ceramic substrate;

[0023] a lower tube S pole terminal connected with an S pole of the lower tube chip through a lower tube S pole connection conductor, and the lower tube S pole terminal is arranged in a stacking manner with the upper tube D pole terminal;

[0024] The D poles of the upper die chips of each single-core power half-bridge are connected with equal impedance, the S poles of the upper die chips of each single-core power half-bridge are connected with equal impedance, the D poles of the lower die chips of each single-core power half-bridge are connected with equal impedance, and the S poles of the lower die chips of each single-core power half-bridge are connected with equal impedance.

[0025] Optionally, in the power brick, an insulating layer is used to cover the region of the upper die chip that is not connected with the first copper layer of the upper die ceramic substrate and the upper die S pole connecting conductor.

[0026] The lower die chip is not connected with the first copper layer of the lower die ceramic substrate and the lower die S pole connecting conductor.

[0027] Optionally, the power brick further comprises:

[0028] A driving circuit board connected with the power half-bridge unit.

[0029] Optionally, in the power brick, the bus capacitor core is formed by parallel connection of N sub capacitor cores, and N is a positive integer not less than 2.

[0030] Optionally, in the power brick, the number of power half-bridge units in the power brick is greater than 1, and all the power half-bridge units are arranged side by side.

[0031] Optionally, the power brick further comprises:

[0032] A heat sink connected with the ceramic substrate of the power half-bridge unit through the integrated packaging shell, for dissipating heat of the power half-bridge unit.

[0033] An electronic device comprising the power brick.

[0034] Based on the above technical solution, the DC bus capacitor, the power half-bridge unit and the AC connecting copper bar in the power brick are integrally packaged by using an integrated packaging shell, which significantly reduces the complexity of the product production process. Integrating multiple components in one packaging body reduces the connection points between components, thereby simplifying the assembly process and reducing the connection complexity. This integrated design not only optimizes the space utilization, enabling the system to achieve higher power output in a smaller volume and improving the power density, but also further improves the system efficiency by reducing the use of heat dissipation components. At the same time, the integrated packaging serves as a connection and barrier between internal elements and the external environment, protecting the internal elements from interference and damage from the external environment, reducing the failure points and improving the reliability of the entire power system. In addition, by strengthening the structural strength of the packaging body and using anti-vibration materials, the integrated packaging also significantly improves the anti-vibration performance of the system. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0036] Figure 1 A design scheme diagram of the power semiconductor device package and the power system disclosed in the prior art;

[0037] Figure 2 A circuit topology diagram of the existing inverter main power system;

[0038] Figure 3 A circuit symbol diagram of IGBT;

[0039] Figure 4 A chip structure diagram of IGBT;

[0040] Figure 5 A circuit symbol diagram of MOSFET;

[0041] Figure 6 A chip structure diagram of MOSFET;

[0042] Figure 7 A structure diagram of a power brick provided by the embodiment of the present application;

[0043] Figure 8 A structure diagram of a single-core power half-bridge in a power half-bridge unit provided by the embodiment of the present application;

[0044] Figure 9 A structure diagram of a single-core power half-bridge; Figure 8 A side view of the single-core power half-bridge;

[0045] Figure 10 A layout mode diagram of a power half-bridge unit in a power brick disclosed by another embodiment of the present application;

[0046] Figure 11 A structure diagram of a single-core power half-bridge; Figure 10 A side view of the power brick.

[0047] DC bus capacitor 000; positive copper bar 001; negative copper bar 002; first capacitor core connecting copper bar 003; second capacitor core connecting copper bar 003; bus capacitor core 005; power half-bridge unit 100; integrated package shell 101; upper tube D terminal 102; upper tube S terminal 103; sintered silver welding area 104; sintered silver welding area 105; sintered silver welding area 106; upper tube chip 107; insulation layer 108; insulation layer 109; upper tube S terminal connecting conductor 110; lower tube S terminal connecting conductor 111; sintered silver welding area 112; sintered silver welding area 113; sintered silver welding area 114; lower tube chip 115; polyimide 116; AC connecting copper bar 117; upper tube ceramic substrate first copper clad layer 118; ceramic substrate ceramic layer 119; lower tube ceramic substrate first copper clad layer 120; ceramic substrate second copper clad layer 121; heat sink 122; upper tube D terminal passage 123; upper tube chip S terminal passage 124; lower tube chip S terminal passage 125; lower tube D terminal passage 126; AC output passage 127; single-core power half-bridge 200; upper tube D terminal monitoring terminal connecting conductor 201; upper tube D terminal monitoring terminal 202; upper tube G terminal monitoring terminal connecting conductor 203; upper tube G terminal 204; upper tube S terminal monitoring terminal connecting conductor 205; upper tube S terminal 206; lower tube G terminal monitoring terminal connecting conductor 207; lower tube G terminal 208; lower tube S terminal monitoring terminal connecting conductor 209; lower tube S terminal 210; temperature monitoring terminal 211; first temperature detection terminal 212; temperature detection element 213; second temperature detection terminal 214; control monitoring terminal 215; power brick system 300; drive circuit board 301. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0049] First, the related terms in the present application are explained:

[0050] Power electronic device: a device composed of power semiconductor devices, passive devices (inductors, capacitors), structural components, heat dissipation systems and control devices, which can realize conversion and control of electric energy.

[0051] Power system: a system composed of high-voltage and high-power parts in a power electronic converter device, mainly including power semiconductor devices, passive devices (inductors or capacitors), electrical connection components (such as copper bars, wires, etc.).

[0052] Power Semiconductor Chip: Made of semiconductor materials such as silicon (Si), silicon carbide (SiC), and gallium nitride (GaN), it can quickly turn on and off to transform and control electrical energy. Mainly includes IGBT (usually made of Si), MOSFET (usually made of Si, SiC, and GaN), diode (made of Si or SiC), etc. This application is referred to as "chip".

[0053] Power Semiconductor Package: Power semiconductor chips cannot be used directly and must be installed in a module through a series of process to achieve chip connection, external electrical connection, heat dissipation, protection (insulation, waterproof, dustproof, oxidation prevention, mechanical damage prevention), etc. The structure of this module is called power semiconductor package. This application is referred to as "package".

[0054] Power Semiconductor Device: The module composed of power semiconductor chips and power semiconductor packages is called power semiconductor device. This application is referred to as "device".

[0055] Inverter: A power electronic device that converts DC power into AC power, its main power system is as shown in Figure 2 . Figure 2 DC input on the left side of the inverter, generally DC power supply such as battery, Figure 2 AC output on the right side. The inverter is composed of three-phase inverter bridge arms, power semiconductor devices S1 and S2 (MOSFET shown in the figure) form A-phase inverter bridge arm, S1 is the upper tube of the inverter bridge arm, the D pole of S1 is connected with DC+ bus; S2 is the lower tube of the inverter bridge arm, the S pole of S2 is connected with DC- bus, A point is the connection point of the S pole of S1 and the D pole of S2, which is the AC output point of A-phase inverter bridge arm; S1 and S2 are alternately and complementarily turned on, which can output AC voltage at A point. Similarly, B-phase and C-phase have the same working principle.

[0056] IGBT: Insulated Gate Bipolar Transistor (IGBT) is a power semiconductor device, its symbol is as shown in Figure 3 and Figure 4 . IGBT has three terminals, collector (C pole), emitter (E pole) and gate (G pole). When the voltage between G pole and E pole exceeds a certain value (threshold voltage), IGBT turns on, and current can flow from C pole to E pole, but cannot conduct in reverse direction. To provide a path for reverse conduction of IGBT, a diode is usually connected in anti-parallel with IGBT.

[0057] MOSFET: Metal Oxide Semiconductor FET is a kind of power semiconductor device, its symbol is as shown in Figure 5 And Figure 6 MOSFET has three terminals, drain (D, Drain), source (S, Source) and gate (G, Gate), when the voltage between G and S exceeds a certain value (threshold voltage), MOSFET is turned on, and current can flow from D to S. Due to the structure of MOSFET, there is a reverse parallel diode, so whether MOSFET is in on state or not, current can flow from S to D.

[0058] Referring to Figure 7 , the power brick disclosed in the embodiments of the application can include:

[0059] DC bus capacitor 000, power half-bridge unit 100 and AC connection copper bar 117, the DC bus capacitor 000, power half-bridge unit 100 and AC connection copper bar 117 are integrally packaged by integral packaging shell 101, wherein at least part of the area of the AC connection copper bar 117 is exposed on the surface of the integral packaging shell 101.

[0060] Referring to Figure 7 , the DC bus capacitor 000 includes:

[0061] bus capacitor core 005;

[0062] Positive copper bar 001, the positive copper bar 001 is connected with the positive port of the bus capacitor core 005, and the end of the positive copper bar 001 not connected with the positive port of the bus capacitor core 005 is exposed outside the integral packaging shell 101; referring to Figure 7 , the positive copper bar 001 can be connected with the positive port of the bus capacitor core 005 through the second capacitor core connecting copper bar 003, and the positive copper bar 001 and the second capacitor core connecting copper bar 003 can be connected by welding;

[0063] Negative copper bar 002, the negative copper bar 002 is connected with the negative port of the bus capacitor core 005; the end of the negative copper bar 002 not connected with the negative port of the bus capacitor core 005 is exposed outside the integral packaging shell 101; referring to Figure 7 , the negative copper bar 002 can be connected with the negative port of the bus capacitor core 005 through the first capacitor core connecting copper bar 003, and the negative copper bar 002 and the first capacitor core connecting copper bar 003 can be connected by welding;

[0064] The upper tube D terminal 102 of the power half-bridge unit 100 is connected with the positive terminal of the bus capacitor core 005, and the upper tube S terminal 103 of the power half-bridge unit 100 is connected with the negative terminal of the bus capacitor core 005. The upper tube D terminal 102 and the upper tube S terminal 103 are arranged in a vertical space in a top-down stacked manner. See Figure 7 The upper tube D terminal 102 is connected with the positive terminal of the bus capacitor core 005 through the second capacitor core connecting copper bar 003, and the upper tube S terminal 103 is connected with the negative terminal of the bus capacitor core 005 through the second capacitor core connecting copper bar 003.

[0065] The AC connecting copper bar 117 is connected with the D pole of the lower tube chip of the power half-bridge unit 100.

[0066] The DC bus capacitor 000, the power half-bridge unit 100 and the AC connecting copper bar 117 are integrally packaged by the integrated packaging shell 101, which significantly reduces the complexity of the product production process. Integrating multiple components in one package reduces the connection points between components, simplifies the assembly process and reduces the connection complexity. This integrated design not only optimizes the space utilization, enabling the system to achieve higher power output in a smaller volume and improving the power density, but also further improves the system efficiency by reducing the use of heat dissipation components. At the same time, the overall packaging serves as a connection and barrier between internal elements and the external environment, protecting internal elements from external environmental interference and damage, reducing failure points and improving the reliability of the entire power system. In addition, by strengthening the structural strength of the package and using shock-resistant materials, the overall packaging significantly improves the shock resistance of the system.

[0067] In the embodiment, the bus capacitor core 005 is composed of N sub-capacitor cores in parallel, and N is a positive integer not less than 2. The N sub-capacitor cores can be connected in parallel through the first capacitor core connecting copper bar 003 and the second capacitor core connecting copper bar 004. These sub-capacitor cores can be vertically connected in parallel, horizontally connected in parallel, or mixed vertically and horizontally connected in parallel, and the specifications of each sub-capacitor core can be set and combined arbitrarily according to design requirements, as long as the designed bus capacitor core 005 can be assembled.

[0068] In the technical scheme disclosed in the embodiment, the number of single-core power half bridges 200 in the power half bridge unit 100 can be set according to actual needs. In order to ensure the current sharing performance between chips in the power half bridge unit 100 and improve the reliability and service life of the power half bridge, in the power half bridge unit 100, the D-pole connection impedance of the upper chip of each single-core power half bridge 200 is equal, the S-pole connection impedance of the upper chip of each single-core power half bridge 200 is equal, the D-pole connection impedance of the lower chip of each single-core power half bridge 200 is equal, and the S-pole connection impedance of the lower chip of each single-core power half bridge 200 is equal. In the scheme, the distance from each chip (upper chip and lower chip) in the single-core power half bridge 200 to the electrical connection terminal can be made equal by controlling the design structure inside the single-core power half bridge 200,

[0069] The structure of the single-core power half bridge 200 in the power half bridge unit 100 can be designed according to design needs. For example, in an embodiment of the present application, as shown in Figure 7 The single-core power half bridge 200 can include:

[0070] The ceramic substrate includes a ceramic substrate second copper clad layer 121, a ceramic substrate ceramic layer 119 arranged on the ceramic substrate second copper clad layer 121, an upper tube ceramic substrate first copper clad layer 118 and a lower tube ceramic substrate first copper clad layer 120 arranged on the side of the ceramic substrate ceramic layer 119 away from the ceramic substrate second copper clad layer 121.

[0071] The upper tube chip 107 is arranged on the upper tube ceramic substrate first copper clad layer 118.

[0072] The lower tube chip 115 is arranged on the lower tube ceramic substrate first copper clad layer 120. The S-pole of the upper tube chip 107 is connected to the D-pole of the lower tube chip 115 through an upper tube S-pole connection conductor 110.

[0073] The upper tube D terminal 102 is connected with the upper tube ceramic substrate first copper coating layer 118 at one end, the upper tube ceramic substrate first copper coating layer 118 and the lower tube ceramic substrate first copper coating layer 120 are arranged on the same side of the ceramic substrate ceramic layer 119 and are in the same horizontal plane, and the upper tube ceramic substrate first copper coating layer 118 and the lower tube ceramic substrate first copper coating layer 120 are electrically isolated, and when the upper tube ceramic substrate first copper coating layer 118 and the lower tube ceramic substrate first copper coating layer 120 are generated, the first copper coating layer can be directly generated on the ceramic substrate ceramic layer 119, and then the first copper coating layer is divided into two independent regions by etching, one of which is the upper tube ceramic substrate first copper coating layer 118, and the other is the lower tube ceramic substrate first copper coating layer 120;

[0074] The alternating current connecting copper bar 117 is connected with the D pole of the lower tube chip 115 through the lower tube ceramic substrate first copper coating layer 120 of the ceramic substrate;

[0075] The upper tube S terminal 103 is connected with the S pole of the lower tube chip 115 through the lower tube S pole connecting conductor 111, and the upper tube S terminal 103 is arranged in a stack with the upper tube D terminal 102;

[0076] In the single-core power half-bridge 200, the D pole connecting impedance of the upper tube chip is equal, the S pole connecting impedance of the upper tube chip is equal, the D pole connecting impedance of the lower tube chip is equal, and the S pole connecting impedance of the lower tube chip is equal.

[0077] The upper tube S terminal 103 is arranged in a stack with the upper tube D terminal 102, which is easy to integrate the single-core power half-bridge 200 with an external power supply, a bus capacitor and the like, ensures the integrity of the stack part of the system design, and further reduces the parasitic inductance of the power integrated system; meanwhile, the copper bar connection in the design scheme can be welded, the welding process is easy to implement, the difficulty of power system design is reduced, and the production process is simplified.

[0078] In the structure, the upper tube D terminal 102, the sintered silver soldering area 105, and the first copper-coated layer 118 of the upper tube ceramic substrate jointly form the upper tube chip D pole passage 123, realizing the electrical connection function of the upper tube chip D pole. The sintered silver soldering area 106, the upper tube S pole connecting conductor 110, and the sintered silver soldering area 112 jointly form the upper tube chip S pole passage 124, which is connected with the D pole of the lower tube chip 115, realizing the electrical connection function of the upper tube chip S pole. Similarly, the lower tube chip S pole passage 125 is composed of the upper tube S pole terminal 103, the sintered silver soldering area 104, the lower tube S pole connecting conductor 111, and the sintered silver soldering area 114, realizing the electrical connection function of the S pole of the lower tube chip. The lower tube D pole passage 126 is composed of the sintered silver soldering area 113, the first copper-coated layer 120 of the lower tube ceramic substrate, and the alternating current connecting copper bar 117, realizing the electrical connection function of the D pole of the lower tube chip.

[0079] As can be seen from the above structure, the packaging structure of the single-core power half-bridge 200 mainly includes two layers, the lower layer is connected with the positive pole of the external power supply through the upper tube D terminal 102, and the current flows through the conductive components in turn, i.e., the upper tube chip D pole passage 123, the upper tube chip 107, the upper tube chip S pole passage 124, the first copper-coated layer 120 of the lower tube ceramic substrate, and the alternating current connecting copper bar 117, and finally connected with the external through the alternating current connecting copper bar 117. The upper layer flows back to the negative pole of the external power supply through the upper tube S terminal 103, and the current flows through the conductive components of the upper layer, i.e., the lower tube D pole passage 126, the lower tube chip 115, and the lower tube chip S pole passage 125, realizing the electrical connection between the upper tube S terminal 103 and the alternating current connecting copper bar 117. The upper layer passage and the lower layer passage are arranged in a three-dimensional space, and the electromagnetic fields generated thereby can be offset, reducing the parasitic inductance of the entire power half-bridge.

[0080] As can be seen from the above scheme, the single-core power half-bridge 200 disclosed in the above embodiments includes at least one single-core power half-bridge 200, and the ceramic substrate, the upper tube chip, the upper tube D terminal, the lower tube S terminal, the lower tube chip, and the alternating current connecting copper bar in each single-core power half-bridge 200 are arranged in a stacked manner, realizing the efficient stacking of the conductive components. This design not only optimizes the performance and efficiency of the system, but also significantly improves the space utilization and integration. Through precise manufacturing and assembly processes, the conductive components are accurately stacked together to form a continuous conductive path, ensuring the physical and electrical integrity of the stacked structure. Not only does it help to reduce the size and weight of the system, but it also enhances the connection reliability and stability between the conductive components. More importantly, the stacked manner effectively shortens the distance between the conductive components, significantly reducing the parasitic inductance of the device itself and the entire power system, reducing energy loss, signal distortion, and electromagnetic interference, and further improving the efficiency and reliability of the system.

[0081] In the embodiment, the distance between the lower tube chip 115 and the upper tube D terminal 102 and the upper tube S terminal 103 is greater than the distance between the upper tube chip 107 and the upper tube D terminal 102 and the upper tube S terminal 103, as shown in Figure 7 When the upper tube D terminal 102 and the upper tube S terminal 103 are located on the left side of the packaging structure, the lower tube chip 115 is located on the right side of the upper tube chip 107, and when the upper tube D terminal 102 and the upper tube S terminal 103 are located on the right side of the packaging structure, the lower tube chip 115 is located on the left side of the upper tube chip 107, so that the current path in the packaging module can be shorter, and the size of the parasitic capacitance is further reduced.

[0082] In the embodiment, in order to ensure the reliability of the single-core power half-bridge 200 and prevent the upper tube chip 107 and the lower tube chip 115 in the single-core power half-bridge 200 from short-circuiting and other problems, as shown in Figure 7 , the area of the upper tube chip 107 that is not connected to the upper tube ceramic substrate first copper layer 118 and the upper tube S terminal connecting conductor 110 is covered with an insulating layer, and the area of the lower tube chip 115 that is not connected to the lower tube ceramic substrate first copper layer 120 and the lower tube S terminal connecting conductor 111 is covered with an insulating layer. In the present application, the material of the insulating layer can be selected according to design requirements as long as it can achieve electrical isolation, for example, in the present solution, the material of the insulating layer can be polyimide, which has high dielectric strength and good electrical insulation performance, can effectively prevent current leakage and electromagnetic interference, and ensure the safety and reliability of the chip.

[0083] Figure 7 In the embodiment, the material of the insulating layer can be polyimide, the insulating layer 109 plays an insulating protection role for the upper tube chip 107, the insulating layer 116 plays an insulating protection role for the lower tube chip 115, and the insulating layer 108 plays an insulating protection role for the upper tube S terminal connecting conductor 110 and the lower tube S terminal connecting conductor 111.

[0084] In the technical solution disclosed in the embodiment, the power half-bridge unit can include a plurality of single-core power half-bridges 200, and the structure of each single-core power half-bridge 200 can be as shown in Figure 8 Further, the arrangement mode of each single-core power half-bridge 200 can be set according to user design requirements, as shown in Figure 8 Each single-core power half-bridge 200 can share the same upper tube D terminal, lower tube S terminal, and AC connecting copper bar.

[0085] In the technical solution disclosed in the embodiment, in order to improve the consistency of each single-core power half-bridge 200, the related impedances of each single-core power half-bridge 200 need to be kept equal, which can include the D-pole connection impedance of the upper tube chip, the S-pole connection impedance of the upper tube chip, the D-pole connection impedance of the lower tube chip, and the S-pole connection impedance of the lower tube chip, that is, the D-pole connection impedance of the upper tube chip of each single-core power half-bridge 200 is equal; the S-pole connection impedance of the upper tube chip of each single-core power half-bridge 200 is equal; the D-pole connection impedance of the lower tube chip of each single-core power half-bridge 200 is equal; and the S-pole connection impedance of the lower tube chip of each single-core power half-bridge 200 is equal.

[0086] In the embodiment, the D-pole connection impedance of the upper tube chip of each single-core power half-bridge 200 can be equal by making the distance of the upper tube D-pole path 123 of the upper tube chip in all single-core power half-bridges 200 equal, as shown in FIG. 2, the upper tube D-pole path 123 is composed of the upper tube D-pole terminal 102, the sintered silver soldering area 105 (the connection area of the upper tube chip and the first copper-coated layer of the upper tube ceramic substrate), and the first copper-coated layer 118 of the upper tube ceramic substrate, in order to make the length of the upper tube D-pole path 123 of the upper tube chip of each single-core power half-bridge 200 equal, the length of the upper tube D-pole terminal in each single-core power half-bridge 200 needs to be equal, the size of the connection area of the upper tube chip and the first copper-coated layer of the upper tube ceramic substrate in each single-core power half-bridge 200 needs to be equal (the connection between the upper tube chip and the first copper-coated layer of the upper tube ceramic substrate is through sintered silver soldering in Table 1 below), and the length of the first copper-coated layer of the upper tube ceramic substrate in each single-core power half-bridge 200 needs to be equal. Figure 7

[0087] In the embodiment, the S-pole connection impedance of the upper tube chip of each single-core power half-bridge 200 can be equal by making the distance of the upper tube chip S-pole path 124 in all single-core power half-bridges 200 equal, as shown in FIG. 2, the upper tube chip S-pole path 124 is composed of the sintered silver soldering area 106 (the connection area of the upper tube S-pole connection conductor and the upper tube chip), the upper tube S-pole connection conductor 110, and the sintered silver soldering area 112 (the connection area of the upper tube S-pole connection conductor and the first copper-coated layer of the lower tube ceramic substrate), in order to make the length of the upper tube chip S-pole path 124 of each single-core power half-bridge 200 equal, the length of the upper tube S-pole connection conductor in each single-core power half-bridge 200 needs to be equal, the size of the connection area of the upper tube S-pole connection conductor and the upper tube chip in each single-core power half-bridge 200 needs to be equal, and the size of the connection area of the upper tube S-pole connection conductor and the first copper-coated layer of the lower tube ceramic substrate in each single-core power half-bridge 200 needs to be equal. Figure 7

[0088] ​​In this embodiment, the drain connection impedance of the lower transistor chip in each single-core power half-bridge 200 can be made equal by ensuring that the distance between the drain paths 126 of the lower transistor in all single-core power half-bridges 200 is equal. See [link to relevant documentation]. Figure 7 The lower transistor D-terminal passage 126 is composed of a sintered silver soldering area 113 (the connection area between the lower transistor chip and the first copper plating layer of the lower transistor ceramic substrate), the first copper plating layer 120 of the lower transistor ceramic substrate, and an AC connection copper busbar 117. In order to make the length of the lower transistor D-terminal passage 126 of each single-core power half-bridge 200 equal, the size of the connection area between the lower transistor chip and the first copper plating layer of the lower transistor ceramic substrate in each single-core power half-bridge 200 needs to be equal (in Table 1 below, the lower transistor chip and the first copper plating layer of the lower transistor ceramic substrate are connected by sintered silver soldering), the length of the first copper plating layer of the lower transistor ceramic substrate in each single-core power half-bridge 200 is equal, and the length of the AC connection copper busbar in each single-core power half-bridge 200 is equal.

[0089] In this embodiment, the equalization of the source-side connection impedance of the lower transistor in each single-core power half-bridge 200 can be achieved by ensuring that the distance between the source-side paths 125 of the lower transistor in all single-core power half-bridges 200 is equal. See [link to relevant documentation]. Figure 7 The lower transistor chip S-terminal path 125 is composed of the upper transistor S-terminal terminal 103, the sintered silver soldering area 104 (the connection area between the lower transistor S-terminal connecting conductor and the lower transistor S-terminal terminal), the lower transistor S-terminal connecting conductor 111, and the sintered silver soldering area 114 (the connection area between the lower transistor chip and the lower transistor S-terminal connecting conductor). In order to make the length of the lower transistor chip S-terminal path 125 of each single-core power half-bridge 200 equal, it is necessary to make the length of the lower transistor S-terminal terminal in each single-core power half-bridge 200 equal, the size of the connection area between the lower transistor S-terminal connecting conductor and the lower transistor S-terminal terminal the same, the length of the lower transistor S-terminal connecting conductor equal, and the size of the connection area between the lower transistor chip and the lower transistor S-terminal connecting conductor the same.

[0090] By configuring the upper transistor's drain path 123, the upper transistor's source path 124, the lower transistor's source path 125, and the lower transistor's drain path 126 in the above manner, a balanced design of the parallel electrical connection impedance of the chips is achieved, improving the current sharing consistency among each single-core power half-bridge 200.

[0091] In the technical solution disclosed in the embodiment, in order to facilitate the connection of the single-core power half-bridge 200 and external devices, the distribution positions of the various connection terminals in the single-core power half-bridge 200 can also be planned, specifically, the upper tube D pole terminal and the lower tube S pole terminal are distributed on the first side of the single-core power half-bridge 200, the AC connection copper bar is arranged on the second side of the single-core power half-bridge 200, and the first side and the second side are two symmetrical sides of the single-core power half-bridge 200; the monitoring terminal and the temperature detection element of the single-core power half-bridge 200 are arranged on the third side or the fourth side of the single-core power half-bridge 200, and the first side, the second side, the third side and the fourth side are four sides of the single-core power half-bridge 200, and the first side, the second side, the third side and the fourth side form a closed rectangular area.

[0092] In the embodiment, the monitoring terminal includes an upper tube D pole monitoring terminal 202, an upper tube G pole terminal 204, an upper tube S pole terminal 206, a lower tube G pole terminal 208, a lower tube S pole terminal 210, a first temperature detection terminal 212 and a second temperature detection terminal 214; wherein the first temperature detection terminal 212 and the second temperature detection terminal 214 together constitute a temperature monitoring terminal of the single-core power half-bridge 200, and the first temperature detection terminal 212 and the second temperature detection terminal 214 are respectively connected to the input end and the output end of the temperature detection element, for providing a temperature detection signal to an external detection unit.

[0093] The upper tube D pole monitoring terminal 202 is connected to the first copper clad layer 118 of the upper tube ceramic substrate through an upper tube D pole monitoring terminal connecting conductor, the upper tube G pole terminal 204 is connected to the G pole of each upper tube chip 107 through an upper tube G pole monitoring terminal connecting conductor 203, the upper tube S pole terminal 206 is connected to the S pole of each upper tube chip 107 through an upper tube S pole monitoring terminal connecting conductor 205, the lower tube G pole terminal 208 is connected to the G pole of each lower tube chip through a lower tube G pole monitoring terminal connecting conductor 207, and the lower tube S pole terminal 210 is connected to the S pole of each lower tube chip 115 through a lower tube S pole monitoring terminal connecting conductor 209.

[0094] In the embodiment, the monitoring terminal and the temperature detection element of the single-core power half-bridge 200 are arranged in the side direction of the electrical connection terminal (the upper tube D pole terminal 102, the upper tube S pole terminal 103 and the AC connection copper bar 117), for example, the temperature detection element 213, the temperature monitoring terminal 211 (the first temperature detection terminal 212 and the second temperature detection terminal 214) and the control monitoring terminal 215 are arranged on the right side of the electrical connection terminal, or are arranged on the left side of the electrical connection terminal, the first temperature detection terminal and the second temperature detection terminal are respectively connected to the input end and the output end of the temperature detection element, for providing a temperature detection signal to an external detection unit, as shown inFigure 9 The monitoring terminals can be led out from the top or side of the one-piece package shell 101 of the single-core power half-bridge 200, and the side is the third side or the fourth side. Of course, the temperature detection element 213 and the control monitoring terminal 215 can also be arranged on the two sides of the electrical connection terminal respectively, for example, the temperature detection element 213 and the control monitoring terminal 211 are arranged on the left side of the electrical connection terminal, and the control monitoring terminal 215 is arranged on the right side of the electrical connection terminal, or the temperature detection element 213 and the control monitoring terminal 211 are arranged on the right side of the electrical connection terminal, and the control monitoring terminal 215 is arranged on the left side of the electrical connection terminal.

[0095] In the embodiment, the materials of the lower tube S pole connecting conductor and the upper tube S pole connecting conductor can be selected according to design requirements, for example, the flexible layer connecting conductor.

[0096] In the embodiment, in order to make the single-core power half-bridge 200 have excellent heat dissipation effect, the single-core power half-bridge 200 further comprises a heat sink 122; the heat sink 122 is arranged on the side of the ceramic substrate away from the lower tube ceramic substrate, and the ceramic substrate directly contacts the heat sink for heat dissipation, the heat transfer thermal resistance is low, and the heat dissipation efficiency of the device can be improved.

[0097] In the technical scheme disclosed in the embodiment, in order to meet design requirements, referring to Figure 10 The power brick can comprise a plurality of power half-bridge units, and the power units can be arranged side by side in the one-piece package shell, and the power units can share a direct-current bus capacitor and an alternating-current connecting copper bar. Of course, a corresponding independent direct-current bus capacitor and alternating-current connecting copper bar can also be configured respectively.

[0098] In the embodiment, the power brick can further comprise a driving circuit board 301, and the driving circuit board is used for controlling the working state of the power half-bridge unit 100, referring to Figure 11 The driving circuit board can be arranged on the surface of the one-piece package shell, and each terminal led out from the surface of the one-piece package shell is connected with the power half-bridge unit 100.

[0099] In a specific embodiment, the composition of the single-core power half-bridge 200 and the labels, names and functions of each component are shown in Table 1:

[0100]

[0101]

[0102]

[0103]

[0104]

[0105]

[0106] Table 1

[0107] The application also provides an electronic device comprising any of the power bricks described above, the electronic device being a household appliance or a car.

[0108] It should be noted that each of the above-described examples of the present specification are described in progressive manner, and each example focuses on the differences from other examples, and the same or similar parts between examples can be mutually referred to.

[0109] It should also be noted that in this document, the terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, and also include other elements not explicitly listed, or further include elements inherent to such an article or device. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of other identical elements in the article or device comprising the element.

[0110] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application should not be limited to the embodiments shown herein, but should be consistent with the widest scope of principles and novel features disclosed herein.

[0111] The above description is only the preferred embodiments of the present application, and it should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A power brick, characterized by, The DC bus capacitor, the power half-bridge unit and the AC connection copper bar are integrally packaged by using an integrated packaging shell, wherein at least part of the AC connection copper bar is exposed on the surface of the integrated packaging shell. The DC bus capacitor comprises: a bus capacitor core; a positive copper bar connected to the positive port of the bus capacitor core, one end of the positive copper bar not connected to the positive port of the bus capacitor core being exposed outside the integrated packaging shell; a negative copper bar connected to the negative port of the bus capacitor core; the upper tube D terminal of the power half-bridge unit is connected to the positive port of the bus capacitor core, and the lower tube S terminal of the power half-bridge unit is connected to the negative port of the bus capacitor core, the upper tube D terminal and the lower tube S terminal being arranged in a vertical space in an upper and lower stack manner; the AC connection copper bar is connected to the D pole of the lower tube chip of the power half-bridge unit. The power half-bridge unit comprises at least one single-core power half-bridge, the D poles of the upper tube chips of each single-core power half-bridge are connected to equal impedance, the S poles of the upper tube chips of each single-core power half-bridge are connected to equal impedance, the D poles of the lower tube chips of each single-core power half-bridge are connected to equal impedance, and the S poles of the lower tube chips of each single-core power half-bridge are connected to equal impedance.

2. The power brick of claim 1, wherein, The power half-bridge unit comprises: at least one single-core power half-bridge; 3. The power brick of claim 1, wherein, The single-core power half-bridge comprises: a ceramic substrate; an upper tube chip arranged on the upper tube ceramic substrate first copper clad layer of the ceramic substrate; a lower tube chip arranged on the lower tube ceramic substrate first copper clad layer of the ceramic substrate, the S pole of the upper tube chip being connected to the D pole of the lower tube chip through an upper tube S pole connection conductor; an upper tube D pole terminal connected to the upper tube ceramic substrate first copper clad layer at one end; an AC connection copper bar connected to the D pole of the lower tube chip through the lower tube ceramic substrate first copper clad layer of the ceramic substrate; a lower tube S pole terminal connected to the S pole of the lower tube chip through a lower tube S pole connection conductor, the lower tube S pole terminal being arranged in a stack manner with the upper tube D pole terminal; wherein the D poles of the upper tube chips of each single-core power half-bridge are connected to equal impedance, the S poles of the upper tube chips of each single-core power half-bridge are connected to equal impedance, the D poles of the lower tube chips of each single-core power half-bridge are connected to equal impedance, and the S poles of the lower tube chips of each single-core power half-bridge are connected to equal impedance. The region of the upper tube chip not connected to the upper tube ceramic substrate first copper clad layer and the upper tube S pole connection conductor is covered with an insulating layer; The region of the lower tube chip not connected to the lower tube ceramic substrate first copper clad layer and the lower tube S pole connection conductor is covered with an insulating layer.

4. The power brick of claim 3, wherein, Further comprising: a driving circuit board connected to the power half-bridge unit.

5. The power brick of claim 1, wherein, The bus capacitor core is composed of N sub-capacitor cores connected in parallel, and N is a positive integer not less than 2. The number of power half-bridge units in the power brick is greater than 1, and all the power half-bridge units are arranged side by side.

6. The power brick of claim 1, wherein, Further comprising:

7. The power brick of claim 1, wherein, ​ 8. The power brick of claim 1, wherein, ​ A heat sink connected through the one-piece package housing to the ceramic substrate of the power half-bridge cell for dissipating heat from the power half-bridge cell.

9. An electronic device, comprising: A power brick comprising the power brick of any of claims 1-8.

10. The electronic device of claim 9, wherein, The electronic device is a car.

Images